JP4724017B2 - 半導体装置の微細パターン形成方法 - Google Patents
半導体装置の微細パターン形成方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 69
- 239000004065 semiconductor Substances 0.000 title claims description 30
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 57
- 229920005591 polysilicon Polymers 0.000 claims description 57
- 238000005530 etching Methods 0.000 claims description 44
- 229920002120 photoresistant polymer Polymers 0.000 claims description 44
- 238000005498 polishing Methods 0.000 claims description 31
- 229910003481 amorphous carbon Inorganic materials 0.000 claims description 30
- 150000004767 nitrides Chemical class 0.000 claims description 24
- 239000011241 protective layer Substances 0.000 claims description 22
- 125000006850 spacer group Chemical group 0.000 claims description 17
- 239000010410 layer Substances 0.000 claims description 15
- 230000007261 regionalization Effects 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 9
- 238000000059 patterning Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 238000007517 polishing process Methods 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 description 4
- 238000007667 floating Methods 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- 230000018109 developmental process Effects 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000035772 mutation Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0338—Process specially adapted to improve the resolution of the mask
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
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- H—ELECTRICITY
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
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- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Inorganic Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Photosensitive Polymer And Photoresist Processing (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Electrodes Of Semiconductors (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
1)研磨停止膜によってCMP工程が停止し、CMP工程の均一度が向上するので、CMP工程の不均一性によるパターン不良を防止することができる。
21 トンネル酸化膜
22 浮遊ゲート用導電膜
23 誘電体膜
24 制御ゲート用導電膜24
25 ハードマスク窒化膜
27 第1保護層
28 第1ポリシリコン膜
29 バッファ酸化膜
30 第2ポリシリコン膜
31 研磨停止膜
32 第1酸化膜
33 第2アモルファスカーボン膜
34 第2保護層
35 窒化膜スペーサ
36 第2酸化膜
37 第2反射防止膜
Claims (16)
- (a)被エッチング層を有する半導体基板上に第1ポリシリコン膜とバッファ酸化膜を順次形成し、前記バッファ酸化膜の所定の領域上に第2ポリシリコン膜、研磨停止膜及び第1酸化膜が積層された構造のハードマスクを形成する段階と、
(b)前記ハードマスクの側面に窒化膜スペーサを形成し、前記全体構造物上に第2酸化膜を形成する段階と、
(c)前記研磨停止膜が露出されるように前記第2酸化膜、前記窒化膜スペーサ及び前記第1酸化膜を研磨し、前記研磨停止膜と前記窒化膜スペーサを除去する段階と、
(d)前記第2ポリシリコン膜と前記第2酸化膜をマスクとして前記バッファ酸化膜をエッチングし、前記第2酸化膜を除去する段階と、
(e)前記第2ポリシリコン膜と前記バッファ酸化膜をマスクとして第1ポリシリコン膜をエッチングし、前記第2ポリシリコン膜を除去する段階と、
(f)前記バッファ酸化膜と前記第1ポリシリコン膜をマスクとして前記被エッチング層をエッチングする段階とを含むことを特徴とする、半導体素子の微細パターン形成方法。 - 前記(d)段階と前記(e)段階との間に、パターン形成を所望しない部分に形成された前記バッファ酸化膜の所定の部分を除去する(g)段階をさらに含むことを特徴とする、請求項1に記載の半導体素子の微細パターン形成方法。
- 前記(g)段階は、全体構造物上に第2反射防止膜と第2フォトレジストを順次形成する段階と、
パターン形成を所望しない部分に形成されたバッファ酸化膜上の第2反射防止膜が露出されるように前記第2フォトレジストをパターニングする段階と、
前記パターニングされた第2フォトレジストをマスクとして前記第2反射防止膜と前記バッファ酸化膜をエッチングする段階と、
前記第2フォトレジストと前記第2反射防止膜を除去する段階とを含むことを特徴とする、請求項2に記載の半導体素子の微細パターン形成方法。 - 前記第1ポリシリコン膜を形成する前に、下部の被エッチングを保護するための保護層を形成する段階をさらに含むことを特徴とする、請求項1に記載の半導体素子の微細パターン形成方法。
- 前記保護層を厚さ200〜400ÅのSiON膜を用いて形成することを特徴とする、請求項4に記載の半導体素子の微細パターン形成方法。
- 前記保護層を形成する前に、第1アモルファスカーボン膜を形成する段階をさらに含むことを特徴とする、請求項4に記載の半導体素子の微細パターン形成方法。
- 前記第1アモルファスカーボン膜を1500〜2500Åの厚さに形成することを特徴とする、請求項6に記載の半導体素子の微細パターン形成方法。
- 前記第1ポリシリコン膜を500〜600Åの厚さに形成し、前記第2ポリシリコン膜を500〜700Åの厚さに形成することを特徴とする、請求項1に記載の半導体素子の微細パターン形成方法。
- 前記バッファ酸化膜を400〜500Åの厚さに形成し、前記第1酸化膜を800〜1000Åの厚さに形成することを特徴とする、請求項1に記載の半導体素子の微細パターン形成方法。
- 前記研磨停止膜を厚さ200〜400ÅのSiON膜を用いて形成することを特徴とする、請求項1に記載の半導体素子の微細パターン形成方法。
- 前記ハードマスクは、
前記バッファ酸化膜の全面に前記第2ポリシリコン膜、前記研磨停止膜及び前記第1酸化膜を順次形成する段階と、
前記第1酸化膜上に第2アモルファスカーボン膜を形成する段階と、
前記第2アモルファスカーボン膜上に第1フォトレジストを塗布しパターニングする段階と、
前記パターニングされた第1フォトレジストをマスクとして前記第2アモルファスカーボン膜、前記第1酸化膜、前記研磨停止膜及び前記第2ポリシリコン膜をエッチングする段階と、
前記エッチング工程の後に残留する第1フォトレジスト及び前記第2アモルファスカーボン膜を除去する段階とを用いて形成することを特徴とする、請求項1に記載の半導体素子の微細パターン形成方法。 - 前記第2アモルファスカーボン膜を1500〜2500Åの厚さに形成することを特徴とする、請求項11に記載の半導体素子の微細パターン形成方法。
- 前記第1フォトレジストを塗布する前に、第2保護層と反射防止膜を順次形成する段階をさらに含むことを特徴とする、請求項11に記載の半導体素子の微細パターン形成方法。
- 前記第2保護層を厚さ200〜400ÅのSiON膜を用いて形成し、前記反射防止膜を200〜400Åの厚さに形成することを特徴とする、請求項13に記載の半導体素子の微細パターン形成方法。
- 前記(c)段階において、前記研磨停止膜を、過度な研磨工程を用いて除去した後、前記窒化膜スペーサを除去することを特徴とする、請求項1に記載の半導体素子の微細パターン形成方法。
- 前記(c)段階において、前記研磨停止膜を前記窒化膜スペーサと共に除去することを特徴とする、請求項1に記載の半導体素子の微細パターン形成方法。
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Application Number | Priority Date | Filing Date | Title |
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KR1020060010154A KR100672123B1 (ko) | 2006-02-02 | 2006-02-02 | 반도체 소자의 미세 패턴 형성방법 |
KR10-2006-0010154 | 2006-02-02 |
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JP2007208224A JP2007208224A (ja) | 2007-08-16 |
JP4724017B2 true JP4724017B2 (ja) | 2011-07-13 |
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JP2006047060A Expired - Fee Related JP4724017B2 (ja) | 2006-02-02 | 2006-02-23 | 半導体装置の微細パターン形成方法 |
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US (1) | US7202174B1 (ja) |
JP (1) | JP4724017B2 (ja) |
KR (1) | KR100672123B1 (ja) |
CN (1) | CN100505152C (ja) |
TW (1) | TWI296420B (ja) |
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TW200731348A (en) | 2007-08-16 |
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