JP4668868B2 - Pll回路 - Google Patents
Pll回路 Download PDFInfo
- Publication number
- JP4668868B2 JP4668868B2 JP2006224041A JP2006224041A JP4668868B2 JP 4668868 B2 JP4668868 B2 JP 4668868B2 JP 2006224041 A JP2006224041 A JP 2006224041A JP 2006224041 A JP2006224041 A JP 2006224041A JP 4668868 B2 JP4668868 B2 JP 4668868B2
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- JP
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- Prior art keywords
- current
- voltage
- output
- circuit
- charge pump
- Prior art date
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- Expired - Fee Related
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- 238000006243 chemical reaction Methods 0.000 claims description 40
- 239000003990 capacitor Substances 0.000 claims description 38
- 230000010354 integration Effects 0.000 claims description 30
- 230000010355 oscillation Effects 0.000 claims description 8
- 230000007423 decrease Effects 0.000 description 16
- 238000010586 diagram Methods 0.000 description 11
- 230000001360 synchronised effect Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
- H03L7/0893—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump the up-down pulses controlling at least two source current generators or at least two sink current generators connected to different points in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Description
v(s)=R×i(s)+i(s)/sC ・・・ 式1
以下、図面を参照して本発明の実施の形態について説明する。図1に実施の形態1にかかるPLL回路1のブロック図を示す。図1に示すように、PLL回路1は、分周器10、11、21、位相比較器12、第1のチャージポンプ回路13、積分フィルタ14、第1の電圧電流変換回路15、第2のチャージポンプ回路16、リップルフィルタ17、第2の電圧電流変換回路18、基準電圧生成回路19、電流制御発振器20を有している。
v1(s)=αi(s)/sαC ・・・ 式2
v2(s)=R×i(s) ・・・ 式3
v(s)=v2(s)+v1(s)
=R×i(s)+αi(s)/sαC
=R×i(s)+i(s)/sC ・・・ 式4
10、11、21 分周器
12 位相比較器
13 第1のチャージポンプ回路
14 積分フィルタ
15 第1の電圧電流変換回路
16 第2のチャージポンプ回路
17 リップルフィルタ
18 第2の電圧電流変換回路
19 基準電圧生成回路
20 電流制御発振器
Claims (7)
- 位相比較器の出力信号に応じて出力電流を制御する第1のチャージポンプ回路と、
前記第1のチャージポンプ回路が出力する電流に基づき発生する電圧信号から所定の周波数成分を除去する積分フィルタと、
前記位相比較器の出力信号に応じて前記第1のチャージポンプ回路より大きな電流を出力し、当該電流を制御する第2のチャージポンプ回路と、
前記第2のチャージポンプ回路が出力する電流に基づき発生する電圧信号からリップル成分を除去するリップルフィルタと、
前記積分フィルタの出力電圧を電流に変換する第1の電圧電流変換回路と、
前記リップルフィルタの出力電圧を電流に変換する第2の電圧電流変換回路と、
前記第1及び第2の電圧電流変換回路の出力電流の合計値に基づいた発振周波数で発振する電流制御発振器とを備え、
前記電流制御発振器の出力信号を前記位相比較器に帰還させ、
前記リップルフィルタは、前記第2のチャージポンプ回路の出力と第1の電源との間に接続された第1の抵抗と、前記第2のチャージポンプ回路の出力と第2の電源との間に接続された第2の抵抗と、前記第2のチャージポンプ回路の出力と第3の電源との間に接続されたコンデンサとを含むPLL回路。 - 前記積分フィルタは、前記第1のチャージポンプ回路の出力と第4の電源との間に接続されたコンデンサを含むことを特徴とする請求項1に記載のPLL回路。
- 前記第1のチャージポンプ回路が出力する電流と、前記第2のチャージポンプ回路が出力する電流とは、所定の比率を有しており、前記所定の比率に基づいて、前記積分フィルタのコンデンサ値が決定されることを特徴とする請求項2に記載のPLL回路。
- 前記第2乃至第4の電源は、同電位であることを特徴とする請求項2に記載のPLL回路。
- 前記第2の電圧電流変換回路は、前記リップルフィルタの出力電圧と基準電圧とを比較し、その差電圧を電流に変換する電圧電流変換回路であることを特徴とする請求項1乃至4いずれか1項に記載のPLL回路。
- 前記基準電圧は、基準電圧配線を介して前記第2の電圧電流変換回路に供給され、前記基準電圧配線と前記第1の電源との間に接続された第3の抵抗と、前記基準電圧配線と前記第2の電源との間に接続された第4の抵抗とによって、値が設定されることを特徴とする請求項5に記載のPLL回路。
- 前記第1乃至第4の抵抗は、同じ抵抗値であることを特徴とする請求項6に記載のPLL回路。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006224041A JP4668868B2 (ja) | 2006-08-21 | 2006-08-21 | Pll回路 |
US11/892,092 US20080042759A1 (en) | 2006-08-21 | 2007-08-20 | PLL circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006224041A JP4668868B2 (ja) | 2006-08-21 | 2006-08-21 | Pll回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008048320A JP2008048320A (ja) | 2008-02-28 |
JP4668868B2 true JP4668868B2 (ja) | 2011-04-13 |
Family
ID=39100851
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006224041A Expired - Fee Related JP4668868B2 (ja) | 2006-08-21 | 2006-08-21 | Pll回路 |
Country Status (2)
Country | Link |
---|---|
US (1) | US20080042759A1 (ja) |
JP (1) | JP4668868B2 (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7990225B1 (en) * | 2008-07-08 | 2011-08-02 | Marvell International Ltd. | Low-jitter phase-locked loop |
JP4683088B2 (ja) * | 2008-07-31 | 2011-05-11 | ソニー株式会社 | 位相同期回路並びに記録再生装置および電子機器 |
JP2010252094A (ja) * | 2009-04-16 | 2010-11-04 | Renesas Electronics Corp | Pll回路 |
JP5448870B2 (ja) * | 2009-04-23 | 2014-03-19 | ルネサスエレクトロニクス株式会社 | Pll回路 |
JP5738749B2 (ja) * | 2011-12-15 | 2015-06-24 | ルネサスエレクトロニクス株式会社 | Pll回路 |
US9973197B2 (en) | 2016-09-07 | 2018-05-15 | Toshiba Memory Corporation | Phase-locked loop circuit |
EP4106205A4 (en) * | 2020-03-03 | 2023-04-19 | Huawei Technologies Co., Ltd. | PHASE LOCKED CIRCUIT |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02244821A (ja) * | 1989-03-16 | 1990-09-28 | Fujitsu Ltd | 位相同期ループ発振器 |
JPH04260219A (ja) * | 1991-02-14 | 1992-09-16 | Nec Corp | 位相同期ループシンセサイザ |
WO1998020407A1 (fr) * | 1996-11-07 | 1998-05-14 | Hitachi, Ltd. | Circuit integre a semi-conducteurs et micro-ordinateur |
JP2001119296A (ja) * | 1999-10-19 | 2001-04-27 | Nec Corp | Pll回路 |
JP2001144610A (ja) * | 1999-11-15 | 2001-05-25 | Nec Corp | Pll回路及びデータ読み出し回路 |
JP2005184771A (ja) * | 2003-12-19 | 2005-07-07 | Renesas Technology Corp | Pll回路を内蔵する半導体集積回路 |
WO2005114844A1 (en) * | 2004-05-07 | 2005-12-01 | Lattice Semiconductor Corporation | Control signal generation for a low jitter switched-capacitor frequency synthesizer |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4883992A (en) * | 1988-09-06 | 1989-11-28 | Delco Electronics Corporation | Temperature compensated voltage generator |
JPH0964727A (ja) * | 1995-08-23 | 1997-03-07 | Toshiba Corp | 同期回路 |
US5727037A (en) * | 1996-01-26 | 1998-03-10 | Silicon Graphics, Inc. | System and method to reduce phase offset and phase jitter in phase-locked and delay-locked loops using self-biased circuits |
US6329882B1 (en) * | 1999-12-20 | 2001-12-11 | Intel Corporation | Third-order self-biased phase-locked loop for low jitter applications |
JP4270339B2 (ja) * | 2000-12-27 | 2009-05-27 | 富士通株式会社 | Pll回路及びこれに用いられる自動バイアス調整回路 |
US6998923B2 (en) * | 2003-09-18 | 2006-02-14 | Cirrus Logic, Inc. | Low-noise loop filter for a phase-locked loop system |
JP3863522B2 (ja) * | 2003-12-25 | 2006-12-27 | Necエレクトロニクス株式会社 | ディジタルvco、vco回路、pll回路、情報記録装置及び同期クロック信号生成方法 |
JP4605433B2 (ja) * | 2004-03-02 | 2011-01-05 | 横河電機株式会社 | チャージポンプ回路およびこれを用いたpll回路 |
US7095287B2 (en) * | 2004-12-28 | 2006-08-22 | Silicon Laboratories Inc. | Method and apparatus to achieve a process, temperature and divider modulus independent PLL loop bandwidth and damping factor using open-loop calibration techniques |
US20060141963A1 (en) * | 2004-12-28 | 2006-06-29 | Adrian Maxim | Method and apparatus to reduce the jitter in wideband PLL frequency synthesizers using noise attenuation |
US20060267644A1 (en) * | 2005-05-24 | 2006-11-30 | Edward Youssoufian | Method and apparatus for loop filter size reduction |
US20070247234A1 (en) * | 2006-04-04 | 2007-10-25 | Honeywell International Inc. | Method for mitigating single event effects in a phase locked loop |
-
2006
- 2006-08-21 JP JP2006224041A patent/JP4668868B2/ja not_active Expired - Fee Related
-
2007
- 2007-08-20 US US11/892,092 patent/US20080042759A1/en not_active Abandoned
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02244821A (ja) * | 1989-03-16 | 1990-09-28 | Fujitsu Ltd | 位相同期ループ発振器 |
JPH04260219A (ja) * | 1991-02-14 | 1992-09-16 | Nec Corp | 位相同期ループシンセサイザ |
WO1998020407A1 (fr) * | 1996-11-07 | 1998-05-14 | Hitachi, Ltd. | Circuit integre a semi-conducteurs et micro-ordinateur |
JP2001119296A (ja) * | 1999-10-19 | 2001-04-27 | Nec Corp | Pll回路 |
JP2001144610A (ja) * | 1999-11-15 | 2001-05-25 | Nec Corp | Pll回路及びデータ読み出し回路 |
JP2005184771A (ja) * | 2003-12-19 | 2005-07-07 | Renesas Technology Corp | Pll回路を内蔵する半導体集積回路 |
WO2005114844A1 (en) * | 2004-05-07 | 2005-12-01 | Lattice Semiconductor Corporation | Control signal generation for a low jitter switched-capacitor frequency synthesizer |
Also Published As
Publication number | Publication date |
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US20080042759A1 (en) | 2008-02-21 |
JP2008048320A (ja) | 2008-02-28 |
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