WO1998020407A1 - Circuit integre a semi-conducteurs et micro-ordinateur - Google Patents

Circuit integre a semi-conducteurs et micro-ordinateur Download PDF

Info

Publication number
WO1998020407A1
WO1998020407A1 PCT/JP1996/003252 JP9603252W WO9820407A1 WO 1998020407 A1 WO1998020407 A1 WO 1998020407A1 JP 9603252 W JP9603252 W JP 9603252W WO 9820407 A1 WO9820407 A1 WO 9820407A1
Authority
WO
WIPO (PCT)
Prior art keywords
clock
circuit
frequency
serial communication
generation circuit
Prior art date
Application number
PCT/JP1996/003252
Other languages
English (en)
Japanese (ja)
Inventor
Toshio Yamada
Shigezumi Matsui
Kozaburo Kurita
Kiyoshi Hasegawa
Ikuo Kudoh
Original Assignee
Hitachi, Ltd.
Hitachi Ulsi Engineering Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi, Ltd., Hitachi Ulsi Engineering Corp. filed Critical Hitachi, Ltd.
Priority to PCT/JP1996/003252 priority Critical patent/WO1998020407A1/fr
Publication of WO1998020407A1 publication Critical patent/WO1998020407A1/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code

Definitions

  • the present invention relates to a clock formation technology in a semiconductor integrated circuit, and a technology effective when applied to a semiconductor integrated circuit in which a PLL (Phase 'Locked' Loop) circuit is incorporated as a clock generation circuit, and particularly to a frequency which is not a power of two.
  • PLL Phase 'Locked' Loop
  • an LSI incorporating a serial communication circuit is provided with a clock generation circuit that generates a clock having a frequency suitable for a transfer rate in the serial communication circuit.
  • a technique using a PLL circuit as a clock generation circuit has been proposed to reduce clock skew (for example, IEEE Journal of Solid-State Circuits, Vol. SC-22, No. 2). (1987) pp255-261 "Design of PLL-Based Clock Generation Circuits"). If a PLL circuit is used, the basic clock signal is input to one input terminal, and the clock signal supplied to the terminal circuit is returned to the other input terminal (reference side), so that the final clock signal is obtained. Can be made to coincide with the phase of the basic clock signal, so that clock skew can be reduced.
  • the transfer rate frequency in the conventional serial communication is, for example, IrDA
  • An object of the present invention is to provide a semiconductor integrated circuit having a built-in clock generation circuit capable of generating a clock for serial communication using a clock having a frequency of 2 such as a clock for a clock. Accordingly, a system having a serial communication function can be realized at low cost.
  • the clock generation circuit receives a clock having a frequency of a power of 2 from the outside as a reference clock.
  • the external magnification is set so as to generate a clock having a frequency that is a common multiple of the frequency of the external input clock and the frequency of the transfer rate, and the serial communication circuit is supplied from the clock generation circuit. It is configured to operate based on a clock obtained by dividing a non-power-of-two clock and transmit and receive serial data at a transfer rate according to a non-power-of-two frequency.
  • a clock for serial communication can be generated using a clock having a frequency of 2 such as a clock for a clock, thereby realizing a system having a serial communication function at low cost. And the number of clock input pins can be reduced.
  • the clock generation circuit comprises a charge pump type PLL circuit, and is configured to change the oscillation cycle during the external input clock cycle in proportion to the detected phase error. And good. This results in reduced jitter.
  • FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit incorporating a clock generation circuit using a PLL circuit and a serial communication circuit according to the present invention.
  • FIG. 2 is a timing chart showing the timing of a reference clock input from the outside and a clock generated internally.
  • FIG. 3 is a block diagram showing an example of a specific circuit configuration of the PLL circuit.
  • FIG. 4 is a circuit diagram showing a specific example of the charge pump circuit and the voltage-current conversion circuit.
  • FIG. 5 is a circuit diagram showing a specific example of the oscillation circuit.
  • FIG. 6 is a circuit diagram showing a specific example of the frequency divider.
  • FIG. 7 is a circuit diagram showing a specific example of the selector circuit of the frequency divider.
  • FIG. 8 is a block diagram showing an embodiment in which the present invention is applied to a single-chip microcomputer incorporating a clock generation circuit using a PLL circuit and a serial communication circuit.
  • FIG. 9 is a block diagram showing a schematic configuration of an application system using LSI to which the present invention is applied.
  • FIG. 1 is a block diagram showing an embodiment of a semiconductor integrated circuit according to the present invention which incorporates a clock generation circuit of a PLL circuit type and a serial communication circuit.
  • circuit elements constituting each block in the figure are formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.
  • Oscillator circuit, 20 is a frequency divider that divides clock 01 output from PLL circuit 10 and inputs it to PLL circuit 10 as feedback clock ⁇ f
  • PLL circuit 10 is an external terminal Compare the reference clock ⁇ 0 input to IN with the feedback clock ⁇ f from the frequency divider 20 and automatically adjust the oscillation frequency and phase so that the phase of the feedback clock ⁇ f matches the reference clock ⁇ 0. Correct it to.
  • the signal processing circuit 50 includes a serial-to-parallel conversion circuit for converting data to be transmitted from parallel data to serial data and for converting received data from serial data to parallel data.
  • the frequency divider circuit 40 that divides the clock ⁇ 1 output from the PLL circuit 10 and supplies a clock suitable for the transfer rate of serial communication to the serial communication circuit 30 In addition, it is configured to supply the PLL circuit output clock ⁇ 1 before frequency division to the signal processing circuit 50. Further, the frequency dividing circuit 40 divides the PLL circuit output clock ⁇ 1 into lZn and supplies it to the receiving unit 32, and further divides the clock used in the receiving unit 32 into lZm and transmits it to the transmitting unit. 3 It is configured to supply to 1.
  • the clock output from the PLL circuit 10 is output in the form of a tree that branches sequentially into an H-shape toward the terminal. Distributed through the system.
  • a clock of 32.768 kHz for a clock (FIG. 2 (a)) is externally input to the PLL circuit 10 as a reference clock 00, and the PLL circuit 10 receives the clock of the reference clock 00.
  • a clock ⁇ 1 (Fig. 2 (b)) with a frequency of 450 times is formed and output, and the frequency divider 40 divides the clock ⁇ 1 output from the PLL circuit 10 into, for example, 1/8 to generate a clock. It is configured to form ⁇ 2 (FIG. 2 (c)) and supply it to the receiving unit 32 of the serial communication circuit 30.
  • the PLL circuit 10 forms and outputs a clock ⁇ 1 having a frequency 450 times the frequency of the reference clock 00 in order to operate the signal processing circuit 50 with a clock such as 15 MHz.
  • a clock By increasing the frequency of the reference clock 00 by 450 times, a clock of 14.4756 MHz can be obtained.
  • a 1.843 2MHz clock is obtained, which is further divided into 1 16 '.
  • a clock with a frequency of 15.2 kHz corresponding to the transfer rate of the serial communication of the IrDA standard can be obtained.
  • the 16 cycles of the clock ⁇ 2 give one bit width of the transmission / reception data.
  • FIG. 3 shows a specific configuration example of the PLL circuit 10.
  • the PLL circuit 10 of this embodiment is provided with a control circuit 91 that changes the oscillation cycle for the period of the external input clock cycle evenly within the external input clock cycle in proportion to the detected phase error in the so-called charge pump PLL circuit 90. It is made from kafun.
  • the comparator 90 includes a phase comparator 11, a charge pump circuit 12 A, a capacitance C a, a voltage-current converter 13 A, and an oscillator 14.
  • the control circuit 91 is composed of a charge pump circuit 12B, a capacitance Cb, a voltage / current conversion circuit 13B, and a reset circuit.
  • the phase comparator 11 detects the phase difference between the externally input reference clock signal ⁇ 0 and the feedback clock signal ⁇ f.
  • Charge pump circuit 12A, 13B are phase Charge and discharge are performed according to the phase difference detected by the comparator 11 to change the voltage of the capacitors C a and C b.
  • the voltage-current converters 13 A and 13 8 convert the current into an amount corresponding to the voltage of the capacitors &.
  • the oscillator 14 oscillates at a frequency corresponding to the combined current of the voltage / current conversion circuits 13A and 13B.
  • the reset circuit 15 resets the electric charge of the capacitor Cb.
  • the configuration is such that the oscillation frequency is mainly determined on the route of the capacitor C a and the phase is adjusted mainly on the route of the capacitor C b.
  • the elements of the charge pump circuits 12A and 12B are designed so that the size of the 12B side is larger, so that the sensitivity to the phase difference is higher for the 12B side. Is done.
  • the reason why the charge pump circuits 12 A and 12 B have different sensitivities is to adjust the frequency on the 12 A side and the phase on the 12 B side.
  • the frequency pull-in by the PLL circuit 10 is because it is not preferable to change the oscillation frequency of the oscillator 14 abruptly when the phases are shifted once the frequencies match.
  • control circuit 91 for adjusting the phase component changes the oscillation frequency (period) evenly within the period of the external input clock, and changes the oscillation period only during that period by the operation described below. It is configured. This will not cause a sudden change.
  • the charge pump circuit 12A and the voltage-to-current conversion circuit 13 A have the same configuration as the charge pump circuit 12 B and the voltage-to-current conversion circuit 13 B in the present embodiment, so that illustration and description are omitted. I do.
  • the charge pump circuit 12 B includes a constant current source I 1, I 2 connected in series between the power supply voltage V cc and the ground point, and a P channel MO SFETQ 1 And an N-channel MO SFET Q 2, and the up signal D "and the down signal D OWN output from the preceding stage phase comparator 1 are applied to the gate terminals of Q 1 and Q 2, respectively.
  • the connection node 2 becomes an output and is connected to the capacitor Cb.
  • the voltage-current conversion circuit 13 B is connected between the differential MO SFETs Q 31 and Q 32 connected to the common source and the constant current sources I 3 and Q 31 and Q 32 connected to the common source terminal.
  • a differential current switch circuit 31 composed of a power rent mirror type load MO SFETs Q 3 3 and Q 3 4 connected to the drain terminal side, and a current combining circuit 32 having a constant current source I 4, Current mirror connected
  • a current output circuit 33 composed of MOS FETs Q35 and Q36, and a reference voltage generator 34 composed of MOS FETs Q37 and Q38 connected in series between Vcc and the ground point.
  • the charging voltage of the capacitor Cb is applied to the gate terminal of the dynamic MOS FET Q31, and the reference voltage Vref is applied to the gate terminal of the other differential MOSFET Q32, and the current according to the voltage difference is synthesized. It is configured to be pulled in or out from the circuit 32.
  • the first-stage phase comparator 11 detects the phase difference between the reference clock signal 00 and the feedback clock signal 0 f, and keeps the low level while the phase of the feedback clock signal ⁇ f is behind the phase of the reference clock signal ⁇ 0.
  • a low-level down signal DOWN and a low-level down signal DOWN are output, and while the phase of the feedback clock signal 0 f is ahead of the phase of the reference clock signal ⁇ 0, the high-level up signal U and the high-level It is configured to output a down signal DOWN and converts the phase error into a pulse signal. Since a comparator having such a function is well known, a description of a specific configuration thereof will be omitted. ⁇
  • the voltage-to-current conversion circuit 13 B is configured such that the voltage Vc supplied from the capacitor Cb connected to the output terminal of the charge pump 12 B in the preceding stage is equal to the voltage Vc of the MOS FET Q32 of the differential circuit 31.
  • the reference voltage Vref applied to the gate terminal is the same, the same current (half the current of the constant current source I3) flows through Q31 and Q32, and the load MOS FETs Q33 and Q34 In each case, half the current of I 3 flows.
  • the control voltage Vc of the gate of the MOSFET Q31 becomes lower than the reference voltage Vref, a drain current smaller than Q32 tends to flow in Q31.
  • the load MOSFETs Q33 and Q34 are current-mirror connected, and a current larger than one half of I3 tends to flow through Q33.
  • the current flows into the constant current source I 4.
  • a current of I 4 minus ⁇ ⁇ ⁇ obtained by subtracting the current ⁇ I flowing from the differential circuit 31 from the current of the constant current source I 4 flows into the MOS FET Q 35, and this current flows through the MOS FET Q 36.
  • the output current I v decreases.
  • the current IV supplied to the oscillator 4 decreases, and as described later, the current flowing through each inverter constituting the oscillator 14 decreases, and the oscillation frequency decreases.
  • the current combining circuit 32 is also configured so that the current from the voltage-to-current conversion circuit 13 A located at the route of the capacitance C a in FIG. 3 is also combined, and the frequency of the oscillator 14 is changed to the voltage-to-current conversion. Determined by the combined current of circuits 3A and 3B.
  • the rising edge of ⁇ 0 and the rising edge of ⁇ f (falling edge may be used) when the reference peak signal 0 and the feedback peak signal ⁇ f are input. And outputs an up signal UP and a down signal DOWN corresponding to the phase difference. Therefore, each time the phase is compared, the current draw amount ⁇ I or the current discharge amount ⁇ I by the voltage-current conversion circuit 3B is determined, and the control current of the oscillator 4 changes accordingly to change the oscillation frequency. Then, the correction to the direction in which the phase of the feedback clock ⁇ f matches the reference clock ⁇ 0 is performed every time the phase comparison is performed.
  • the reset circuit 15 has a channel connected in series between the input terminals of the voltage-current conversion circuit 13 B, that is, between the gate terminals of the differential MOS FETs Q 31 and Q 32.
  • the transmission gate 50 composed of the complementary MOS FETs Q51 and Q52 connected in such a manner as described above, and the above-mentioned base clock signal ⁇ 0 and feedback clock signal ⁇ f are input signals.
  • the reset circuit 15 of this embodiment is configured to output a one-shot pulse having a pulse width corresponding to the delay time set in the delay circuit 53 by the earlier signal of the reference clock signal 00 and the feedback clock signal ⁇ f. A reset signal is generated and output.
  • the MOS gates Q51 and Q52 constituting the transmission gate 50 are turned on by this pulse, the input terminals of the voltage-current conversion circuit 13B are short-circuited to charge the capacitor Cb. Reset the charged charge. That is, the reset circuit 15 resets the capacitor Cb of the charge pump in parallel with the phase comparator 11 comparing the phase difference between the reference clock signal ⁇ 0 and the feedback clock signal ⁇ f. It is.
  • the value of the delay time set in the delay circuit 53 is not particularly limited, but is, for example, about 3 ns.
  • the reset signal is formed by the earlier signal of the reference clock signal 00 and the feedback clock signal ⁇ f.
  • the reset signal is output from the phase comparator 11 according to the result of the phase comparison. This is because the charge of the capacitor Cb is reset before the changed up signal or down signal is changed. Thus, the voltage value of the capacitor Cb charged or discharged by the previous phase comparison does not affect the result of the next phase comparison.
  • the phase comparator 11 outputs the reference cut signal ⁇ 0 and the feedback cut signal ⁇ f.
  • phase comparison is made and output signals UP and DOWN are formed, so that the capacitance due to the previous phase comparison remains in the capacitance C a of the charge pump 12 A and the capacitance due to the next phase comparison. Charge or discharge is performed, and it can be seen that the medium force and phase do not match.
  • the phase can be adjusted by uniformly controlling the oscillation circuit 14 with the voltage held in the capacitor Cb.
  • the phase is adjusted immediately when the up signal or the down signal is output from the phase comparator 11, so that the phase may advance due to sudden phase adjustment.
  • FIG. 5 shows a specific circuit configuration example of the oscillation circuit 14 in which the oscillation frequency is controlled by receiving the control currents of the voltage-current conversion circuits 13A and 13B.
  • the oscillation circuit 14 of this embodiment has a ring structure in which an odd number of CMOS inverters G 1 to G 5 each having N-channel MOS FETs connected to current control MOS FETs Q 11 to Q 15 are cascaded.
  • 3A and 13B output currents IV are input as control currents, so that the MOSs for flowing a current of the same magnitude as the current Iv to the above-mentioned constant-current MOS FETs Q11 to Q15.
  • FET Q10 A CMOS inverter can be used for the buffer gate 42.
  • the above-described ring oscillator type oscillation circuit 14 is a time required to charge and discharge the parasitic capacitance existing at the output node of each of the CMOS inverters G1 to G5 constituting the ring oscillator 41. It is determined.
  • the charging time of each parasitic capacitance is determined by the impedance of the cascode type MOS FETs Q21 to Q25 connected to the PMOS side of the CMOS inverters G1 to G5, and is constant.
  • the discharge time of each parasitic capacitance is determined by the current flowing through the current control MOSFET Ql1 to Q15 on the NMOS side of the CMOS inverter. These currents are the voltage-current converters 13A and 13B.
  • FIG. 6 shows an embodiment of the frequency divider 20.
  • the frequency divider of this embodiment has a register 21 that can hold 10-bit data, and a value of “1” when the 10-bit data held in the register 21 is input.
  • a subtracter 22 that outputs a value that is smaller than the above value, and either the output value of the 10-bit of the subtractor 22 or the frequency division value set in a setting unit (not shown) is selected and stored in the register 21. It comprises a selector 23 to be supplied, and a latch circuit 24 that latches a Por signal Br output from the subtracter 22 in synchronization with the clock ⁇ 1 to form an output clock ⁇ f.
  • the clock ⁇ ⁇ from the PLL circuit 10 is supplied to the register 21 and the latch circuit 24, and the latch operation is performed in synchronization with the clock ⁇ 1.
  • the selector 23 is controlled by a borrow signal Br output when the output of the subtractor 22 becomes "0". In a normal state in which the borrow signal Br is at a low level, the selector 23 is selected. Is selected and input to the register 21. When the borrow signal Br changes to the high level, the frequency division value set in the setting unit (not shown) is selected and supplied to the register 21. Thus, for example, when the division value set in a setting device (eg, a register or a memory) not shown is “450”, “450” is first synchronized with the clock ⁇ 1.
  • a setting device eg, a register or a memory
  • the borrow signal Br changes to a high level, so that the selector 23 changes the output value of the subtractor 22 to a design unit (not shown). Select the set dividing value and supply it to register 21 above. Further, the latch circuit 24 latches the borrow signal Br in synchronization with the clock 01. With this operation, the clock ff having a cycle obtained by multiplying the cycle of the clock 11 by 450 is output from the latch circuit 24.
  • the frequency divider of this embodiment can be operated as a variable frequency divider having an arbitrary frequency division ratio in the range of “2” to “10 24” by changing the frequency division value set from the outside. it can.
  • the pulse width of the clock ⁇ f output from the latch circuit 24 is one cycle of the clock ⁇ 1, that is, the duty is 1 / 450 signals.
  • the comparator itself operates normally.
  • the reset circuit 15 when the reset circuit 15 is provided as in the PLL circuit of the above embodiment, when the phase of the feedback clock ⁇ f is earlier than the phase of the reference clock ⁇ 0 by more than the pulse width of ⁇ , the reset pulse is generated. Two will be formed.
  • a predetermined 2-bit signal (2 bits on the MSB side) of the output value of the 10-bit of the subtractor 22 is input to the latch circuit 24.
  • a clock ⁇ f with a duty of almost 50% is formed and output.
  • the frequency divider 20 may be configured by a preset down counter instead of the subtractor 22.
  • a down counter has, for example, a configuration in which 10 flip-flops are connected in cascade, and counts down by “1” by a clock ⁇ 1, and the stage in the middle (for example, the fifth stage or the sixth stage).
  • the configuration is such that the output signal of the flip-flop of the second stage) is input to the latch circuit 24 in FIG. 6, and thus has a cycle 450 times the cycle of the clock ⁇ 1, similarly to the frequency divider of the embodiment of FIG. 6.
  • the clock ⁇ f is obtained.
  • FIG. 7 shows a specific configuration example of the selector 23 that enables the frequency division ratio of the frequency divider 2 ° to be set in two stages.
  • the selector 23 includes eight pairs of transmission MOSFETs Qa1, Qbl to Qa7, and Qb7, and is provided with an external terminal 25 to which a mode setting signal MOD is input.
  • the mode setting signal MOD input to the external terminal 25 and the signal inverted by the inverter 26 are applied to the gates of the transmission MOS FETs Qa and Qb.
  • the operation can be performed by switching to the two-stage division ratio. it can.
  • FIG. 8 shows a configuration of an embodiment of a single-chip microcomputer having a built-in clock generation circuit including the PLL circuit 10 and the frequency divider 20 of the above embodiment.
  • 110 is a clock generation circuit composed of a PLL circuit 10 and a frequency divider 20
  • 120 is a second clock generation circuit
  • 130 is a serial communication module
  • 140 is a frequency division circuit
  • 151 is arithmetic control
  • 152 is a cache memory
  • 153 is a 0/8
  • 154 is a DMA controller that performs 0 MA transfer control
  • 155 is a data bus
  • 156 is an address bus.
  • a clock of 32.768 kHz (power of 2) for a clock is input as a reference clock ⁇ 0 to the PLL circuit 10 from the outside, and the PLL circuit 10 is synchronized with the clock.
  • a clock 01 having a frequency that is not a power of 2 and is, for example, 450 times 1 4.74 56 MHz is formed and output.
  • the generated clock ⁇ 1 is divided by the frequency divider 20 and input to the PLL circuit 10 as the feedback clock ⁇ f, and the oscillation frequency is automatically adjusted so that the phase of the feedback clock 0f matches the reference clock ⁇ 0. To fix.
  • the clock ⁇ 1 is supplied as a system clock to peripheral circuits such as the cache memory 15 2, ⁇ / ⁇ , A / D conversion circuit 15 3, and the DMA controller 154, and the frequency divider 1 40 Is divided by 1Z8 and supplied to the serial communication module 130 as a clock ⁇ 2. Further, the clock ⁇ ⁇ is supplied to a second clock generation circuit 120 including a PLL circuit 122 and a frequency divider 122, and based on this, for example, 18 OMH having a frequency twice as large as ⁇ 1 is obtained. A clock 0c such as z is formed, and the clock 0c is supplied to the CPU 151 as an operation clock of the CPU.
  • the serial communication module 130 of this embodiment has a transmission unit 13 1 and a reception unit 13 2 in the same manner as in the above-described embodiment, and also has a parallel unit transmitted from the CPU 15 1 via the data bus 15 5.
  • the transmission data is converted to serial transmission data and passed to the transmission unit 13 1, or the serial reception data received by the reception unit 13 2 is converted to parallel data and converted to the CPU 15 5 1 via the data bus 15 5 SCIF (Serial Communication Interface) circuit to transfer to 1/3.
  • the SCIF 133 has a built-in frequency divider that further divides the clock ⁇ 2 supplied from the frequency divider 140 into 1Z16, and forms clocks ⁇ t and ⁇ r suitable for transmission and reception, respectively, and the transmission unit.
  • the clock ⁇ r suitable for reception is a clock having a pulse width equivalent to three clocks of 1.84 2MHz clock ⁇ 2 as shown in Fig. 2 (d '), and a clock suitable for transmission.
  • tt is a clock having a pulse width equivalent to one clock of clock 02, as shown in Fig. 2 (e,).
  • the transmission enable EN indicating transmission permission is supplied from the CPU 15 1 to the serial communication module 130, and the reception unit 13 2 is transmitted from the serial communication module 130 to the CPU 15 1.
  • Receive when data is received A signal RQ indicating that there has been received is input.
  • FIG. 9 shows a schematic configuration of an application system using LSI to which the present invention is applied.
  • reference numeral 100 denotes an LSI such as a single-chip microcomputer incorporating a serial communication circuit 30 or a serial communication module 130 to which the present invention is applied.
  • the IC 200 for photoelectric conversion is connected to the transmission data terminal TX and the serial reception data terminal RX, respectively.
  • the photo-electric conversion IC 200 includes a photodiode 210 that converts transmission data into an optical signal in the infrared region and outputs the signal, and a photo transistor 220 that converts received infrared light into an electric signal.
  • the infrared light emitted from the photodiode 210 of one photoelectric conversion IC is arranged to be able to be received by the phototransistor 220 of the other photoelectric conversion IC.
  • a clock of a power of 2 is input from the outside as a reference clock to the clock generation circuit.
  • the serial communication circuit is a power of 2 supplied from the clock generation circuit. It is configured to transmit and receive serial data at a transfer rate according to a frequency that is not a power of 2 and that is operated based on a clock obtained by dividing a clock that is not a power of 2.
  • a clock for serial communication can be generated using the There is an effect that it is possible to inexpensively realize a system having a serial communication function Te.
  • the clock generated by the clock generation circuit is supplied as an operating clock to signal processing circuits other than the serial communication circuit (for example, the CPU and its peripheral circuits), so the number of clock input pins can be reduced. effective.
  • the clock generation circuit is composed of a charge pump type PLL circuit, and is configured to change the oscillation period during the period of the external input clock evenly within the period of the external input clock substantially in proportion to the detected phase error.
  • the transfer rate of a serial communication circuit is not limited to 115.2 kHz, and any standard may be used as long as the transfer rate follows a frequency that is not a power of 2.
  • the communication can be applied even if it is a communication.
  • This provides a semiconductor integrated circuit with a built-in clock generation circuit that can generate a clock for serial communication using a clock having a frequency of 2 such as a clock for a clock, and has a serial communication function.
  • the system can be realized at low cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

Dans un circuit intégré à semi-conducteurs doté d'un circuit générateur d'horloge qui utilise un circuit à verrouillage de phase et un circuit de communication sériel, on fait entrer depuis l'extérieur dans le circuit générateur d'horloge une horloge dont la fréquence est une puissance de 2 qui sert d'horloge de référence et le multiplicateur est déterminé de sorte que le circuit génère une horloge dont la fréquence est le multiple commun de la fréquence de l'horloge introduite dans le circuit générateur d'horloge depuis l'extérieur et de la vitesse de transfert. Le circuit de communication sériel est mis en oeuvre sur la base d'une horloge dont la fréquence est un sous-multiple entier de la fréquence d'une horloge fournie par le circuit générateur d'horloge mais qui n'est pas une puissance de 2, ce même circuit de communication sériel envoyant et recevant des données sérielles à la vitesse de transfert suivant la fréquence qui n'est pas une puissance de 2.
PCT/JP1996/003252 1996-11-07 1996-11-07 Circuit integre a semi-conducteurs et micro-ordinateur WO1998020407A1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/003252 WO1998020407A1 (fr) 1996-11-07 1996-11-07 Circuit integre a semi-conducteurs et micro-ordinateur

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP1996/003252 WO1998020407A1 (fr) 1996-11-07 1996-11-07 Circuit integre a semi-conducteurs et micro-ordinateur

Publications (1)

Publication Number Publication Date
WO1998020407A1 true WO1998020407A1 (fr) 1998-05-14

Family

ID=14154067

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP1996/003252 WO1998020407A1 (fr) 1996-11-07 1996-11-07 Circuit integre a semi-conducteurs et micro-ordinateur

Country Status (1)

Country Link
WO (1) WO1998020407A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004091108A1 (fr) * 2003-04-01 2004-10-21 Nec Corporation Systeme de terminal de traitement d'information et procede de transmission/reception mettant en oeuvre un tel systeme
JP2008048320A (ja) * 2006-08-21 2008-02-28 Nec Electronics Corp Ｐｌｌ回路
CN111092609A (zh) * 2019-12-30 2020-05-01 西北工业大学 一种无参考电压的rc张弛振荡器

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0378298U (fr) * 1989-12-04 1991-08-07
JPH05143530A (ja) * 1991-11-20 1993-06-11 Mitsubishi Electric Corp バス競合制御装置
JPH06290281A (ja) * 1993-04-01 1994-10-18 Nec Ic Microcomput Syst Ltd マイクロプロセッサ
JPH07170178A (ja) * 1993-09-10 1995-07-04 Sun Microsyst Inc Ｐｌｌ減衰回路

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0378298U (fr) * 1989-12-04 1991-08-07
JPH05143530A (ja) * 1991-11-20 1993-06-11 Mitsubishi Electric Corp バス競合制御装置
JPH06290281A (ja) * 1993-04-01 1994-10-18 Nec Ic Microcomput Syst Ltd マイクロプロセッサ
JPH07170178A (ja) * 1993-09-10 1995-07-04 Sun Microsyst Inc Ｐｌｌ減衰回路

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004091108A1 (fr) * 2003-04-01 2004-10-21 Nec Corporation Systeme de terminal de traitement d'information et procede de transmission/reception mettant en oeuvre un tel systeme
US7471926B2 (en) 2003-04-01 2008-12-30 Nec Corporation Information processing terminal system and transmission/reception method using the same
CN1771668B (zh) * 2003-04-01 2010-06-16 日本电气株式会社 数据处理终端系统以及使用其的发射和接收方法
US8447224B2 (en) 2003-04-01 2013-05-21 Nec Corporation Data processing terminal system and transmitting and receiving method using the same
JP2008048320A (ja) * 2006-08-21 2008-02-28 Nec Electronics Corp Ｐｌｌ回路
JP4668868B2 (ja) * 2006-08-21 2011-04-13 ルネサスエレクトロニクス株式会社 Ｐｌｌ回路
CN111092609A (zh) * 2019-12-30 2020-05-01 西北工业大学 一种无参考电压的rc张弛振荡器
CN111092609B (zh) * 2019-12-30 2023-03-21 西北工业大学 一种无参考电压的rc张弛振荡器

Similar Documents

Publication Publication Date Title
JP3415304B2 (ja) クロック発生回路とプロセッサ
US5923715A (en) Digital phase-locked loop circuit
JP3403551B2 (ja) クロック分配回路
US8334725B2 (en) Circuit and method for controlling mixed mode controlled oscillator and CDR circuit using the same
US8232822B2 (en) Charge pump and phase-detecting apparatus, phase-locked loop and delay-locked loop using the same
US7379521B2 (en) Delay circuit with timing adjustment function
JP2012523181A (ja) 非重複クロック生成のための技術
JP2008079274A (ja) 周波数比較器、周波数合成器及び関連方法
JPH07202649A (ja) 逓倍回路
JP2008135835A (ja) Ｐｌｌ回路
CN110752846A (zh) 异步逐次逼近模拟-数字转换器的延迟控制电路
US6919750B2 (en) Clock signal generation circuit used for sample hold circuit
JP5959422B2 (ja) クロック再生回路、受光回路、光結合装置、並びに周波数シンセサイザ
WO1998020407A1 (fr) Circuit integre a semi-conducteurs et micro-ordinateur
CN113162586B (zh) 一种时钟占空比修调方法及系统
JP2004328280A (ja) スペクトラム拡散クロック発生回路
JP2001024485A (ja) Ｐｌｌ回路
JP3607026B2 (ja) ディジタルｐｌｌ回路
JP2003229764A (ja) 半導体集積回路
TWI314397B (en) Phase locked loop circuit
JPH0846497A (ja) 周波数位相比較器
US6940331B2 (en) Delayed tap signal generating circuit for controlling delay by interpolating two input clocks
CN210518272U (zh) 异步逐次逼近模拟-数字转换器的延迟控制电路
JP2003289248A (ja) Ｐｌｌ回路
Deepthi et al. A 0.49-9.8 Gb/s 0.1-1V Output Swing Transmitter with 38.4 MHz Reference and< 30 ns Turn-On Time

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): CN JP KR SG US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase