JP4553765B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4553765B2
JP4553765B2 JP2005087644A JP2005087644A JP4553765B2 JP 4553765 B2 JP4553765 B2 JP 4553765B2 JP 2005087644 A JP2005087644 A JP 2005087644A JP 2005087644 A JP2005087644 A JP 2005087644A JP 4553765 B2 JP4553765 B2 JP 4553765B2
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Japan
Prior art keywords
metal plate
silicon substrate
resin layer
sealing resin
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2005087644A
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English (en)
Japanese (ja)
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JP2006269861A (ja
JP2006269861A5 (https=
Inventor
吉浩 佐伯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Semiconductor Co Ltd filed Critical Oki Semiconductor Co Ltd
Priority to JP2005087644A priority Critical patent/JP4553765B2/ja
Priority to US11/386,841 priority patent/US7679175B2/en
Publication of JP2006269861A publication Critical patent/JP2006269861A/ja
Publication of JP2006269861A5 publication Critical patent/JP2006269861A5/ja
Application granted granted Critical
Publication of JP4553765B2 publication Critical patent/JP4553765B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/288—Configurations of stacked chips characterised by arrangements for thermal management of the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
JP2005087644A 2005-03-25 2005-03-25 半導体装置の製造方法 Expired - Lifetime JP4553765B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2005087644A JP4553765B2 (ja) 2005-03-25 2005-03-25 半導体装置の製造方法
US11/386,841 US7679175B2 (en) 2005-03-25 2006-03-23 Semiconductor device including substrate and upper plate having reduced warpage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005087644A JP4553765B2 (ja) 2005-03-25 2005-03-25 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2006269861A JP2006269861A (ja) 2006-10-05
JP2006269861A5 JP2006269861A5 (https=) 2008-01-24
JP4553765B2 true JP4553765B2 (ja) 2010-09-29

Family

ID=37034369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005087644A Expired - Lifetime JP4553765B2 (ja) 2005-03-25 2005-03-25 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US7679175B2 (https=)
JP (1) JP4553765B2 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005027582A1 (ja) * 2003-09-10 2005-03-24 Fujitsu Limited 表示装置及びその製造方法
JP4553813B2 (ja) * 2005-08-29 2010-09-29 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
MY153017A (en) * 2007-02-16 2014-12-31 Sumitomo Bakelite Co Circuit board manufacturing method, semiconductor manufacturing apparatus, circuit board and semiconductor device
JP4825784B2 (ja) * 2007-12-13 2011-11-30 新光電気工業株式会社 半導体装置用パッケージおよびその製造方法
JP5543086B2 (ja) 2008-06-25 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
JP2010245383A (ja) 2009-04-08 2010-10-28 Elpida Memory Inc 半導体装置および半導体装置の製造方法
JP5543125B2 (ja) 2009-04-08 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 半導体装置および半導体装置の製造方法
JP5579402B2 (ja) 2009-04-13 2014-08-27 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法並びに電子装置
JP5149881B2 (ja) * 2009-09-30 2013-02-20 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8541886B2 (en) * 2010-03-09 2013-09-24 Stats Chippac Ltd. Integrated circuit packaging system with via and method of manufacture thereof
JP2011192781A (ja) * 2010-03-15 2011-09-29 Disco Corp パッケージ基板の加工方法
KR102066015B1 (ko) 2013-08-13 2020-01-14 삼성전자주식회사 반도체 패키지 및 이의 제조방법
JP2015056563A (ja) * 2013-09-12 2015-03-23 株式会社東芝 半導体装置およびその製造方法
JP2015177061A (ja) * 2014-03-14 2015-10-05 株式会社東芝 半導体装置の製造方法および半導体装置
JP2014112742A (ja) * 2014-03-25 2014-06-19 Ps4 Luxco S A R L 切断前支持基板
US9768149B2 (en) * 2015-05-19 2017-09-19 Micron Technology, Inc. Semiconductor device assembly with heat transfer structure formed from semiconductor material
JP6582783B2 (ja) * 2015-09-16 2019-10-02 富士電機株式会社 半導体装置
US9941186B2 (en) * 2016-06-30 2018-04-10 Taiwan Semiconductor Manufacturing Company Ltd. Method for manufacturing semiconductor structure
KR102506698B1 (ko) * 2018-02-19 2023-03-07 에스케이하이닉스 주식회사 보강용 탑 다이를 포함하는 반도체 패키지 제조 방법
US10685937B2 (en) * 2018-06-15 2020-06-16 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit package having dummy structures and method of forming same
CN118471830A (zh) * 2023-02-02 2024-08-09 长鑫存储技术有限公司 封装结构及其制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5834339A (en) 1996-03-07 1998-11-10 Tessera, Inc. Methods for providing void-free layers for semiconductor assemblies
US5886396A (en) 1995-06-05 1999-03-23 Motorola, Inc. Leadframe assembly for conducting thermal energy from a semiconductor die disposed in a package
US5726079A (en) * 1996-06-19 1998-03-10 International Business Machines Corporation Thermally enhanced flip chip package and method of forming
JP3674179B2 (ja) 1996-10-04 2005-07-20 株式会社デンソー ボールグリッドアレイ半導体装置及びその製造方法
JPH10116936A (ja) * 1996-10-09 1998-05-06 Toshiba Microelectron Corp 半導体パッケージ
US6127724A (en) * 1996-10-31 2000-10-03 Tessera, Inc. Packaged microelectronic elements with enhanced thermal conduction
US5990418A (en) * 1997-07-29 1999-11-23 International Business Machines Corporation Hermetic CBGA/CCGA structure with thermal paste cooling
JP4078033B2 (ja) * 1999-03-26 2008-04-23 株式会社ルネサステクノロジ 半導体モジュールの実装方法
JP3673442B2 (ja) * 2000-03-16 2005-07-20 ローム株式会社 半導体装置の製造方法
JP4574118B2 (ja) 2003-02-12 2010-11-04 株式会社半導体エネルギー研究所 半導体装置及びその作製方法
JP2004304622A (ja) 2003-03-31 2004-10-28 Fujitsu Media Device Kk 弾性表面波デバイス及びその製造方法
US7180165B2 (en) 2003-09-05 2007-02-20 Sanmina, Sci Corporation Stackable electronic assembly
US7170188B2 (en) * 2004-06-30 2007-01-30 Intel Corporation Package stress management
JP4553813B2 (ja) 2005-08-29 2010-09-29 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法

Also Published As

Publication number Publication date
JP2006269861A (ja) 2006-10-05
US7679175B2 (en) 2010-03-16
US20060214277A1 (en) 2006-09-28

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