JP4538107B2 - 半導体素子及び金属化層を有する絶縁層が接着剤により取付られているガラス支持体を有する半導体装置 - Google Patents

半導体素子及び金属化層を有する絶縁層が接着剤により取付られているガラス支持体を有する半導体装置 Download PDF

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JP4538107B2
JP4538107B2 JP54443799A JP54443799A JP4538107B2 JP 4538107 B2 JP4538107 B2 JP 4538107B2 JP 54443799 A JP54443799 A JP 54443799A JP 54443799 A JP54443799 A JP 54443799A JP 4538107 B2 JP4538107 B2 JP 4538107B2
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Japan
Prior art keywords
layer
semiconductor device
insulating layer
thickness
glass support
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JP54443799A
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Japanese (ja)
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JP2001526842A (ja
JP2001526842A5 (https=
Inventor
ロナルド デッケル
ヘンリクス ヘー エル マース
デュールゼン マリア ハー ウェー アー ファン
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NXP BV
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NXP BV
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Thin Film Transistor (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
JP54443799A 1998-03-02 1999-02-15 半導体素子及び金属化層を有する絶縁層が接着剤により取付られているガラス支持体を有する半導体装置 Expired - Lifetime JP4538107B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP98200644.7 1998-03-02
EP98200644 1998-03-02
PCT/IB1999/000254 WO1999045588A2 (en) 1998-03-02 1999-02-15 Semiconductor device comprising a glass supporting body onto which a substrate with semiconductor elements and a metallization is attached by means of an adhesive

Publications (3)

Publication Number Publication Date
JP2001526842A JP2001526842A (ja) 2001-12-18
JP2001526842A5 JP2001526842A5 (https=) 2006-06-22
JP4538107B2 true JP4538107B2 (ja) 2010-09-08

Family

ID=8233431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54443799A Expired - Lifetime JP4538107B2 (ja) 1998-03-02 1999-02-15 半導体素子及び金属化層を有する絶縁層が接着剤により取付られているガラス支持体を有する半導体装置

Country Status (4)

Country Link
US (1) US6177707B1 (https=)
EP (1) EP0985228A1 (https=)
JP (1) JP4538107B2 (https=)
WO (1) WO1999045588A2 (https=)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003503854A (ja) * 1999-06-29 2003-01-28 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 半導体デバイス
JP2001118927A (ja) * 1999-10-22 2001-04-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
EP1453097A4 (en) 2001-11-05 2008-01-23 Zycube Co Ltd TUBE-FREE IMAGE SENSOR AND METHOD FOR THE PRODUCTION THEREOF
EP1453093A4 (en) * 2001-11-05 2007-10-10 Zycube Co Ltd SEMICONDUCTOR COMPONENT WITH A LOW-DINE-CIRCULAR MATERIAL FILM AND METHOD FOR THE PRODUCTION THEREOF
JP4389626B2 (ja) * 2004-03-29 2009-12-24 ソニー株式会社 固体撮像素子の製造方法
US7714292B2 (en) * 2006-02-01 2010-05-11 Koninklijke Philips Electronics N.V. Geiger mode avalanche photodiode
US7829438B2 (en) 2006-10-10 2010-11-09 Tessera, Inc. Edge connect wafer level stacking
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7759166B2 (en) * 2006-10-17 2010-07-20 Tessera, Inc. Microelectronic packages fabricated at the wafer level and methods therefor
US7952195B2 (en) * 2006-12-28 2011-05-31 Tessera, Inc. Stacked packages with bridging traces
US7679187B2 (en) * 2007-01-11 2010-03-16 Visera Technologies Company Limited Bonding pad structure for back illuminated optoelectronic device and fabricating method thereof
CN101809739B (zh) 2007-07-27 2014-08-20 泰塞拉公司 具有后应用的衬垫延长部分的重构晶片堆封装
CN101861646B (zh) 2007-08-03 2015-03-18 泰塞拉公司 利用再生晶圆的堆叠封装
US8043895B2 (en) 2007-08-09 2011-10-25 Tessera, Inc. Method of fabricating stacked assembly including plurality of stacked microelectronic elements
JP2008113018A (ja) * 2007-12-03 2008-05-15 Sony Corp 固体撮像素子とその製造方法、及び半導体集積回路装置とその製造方法
KR101655897B1 (ko) * 2008-06-16 2016-09-08 테세라, 인코포레이티드 마이크로전자 조립체 및 적층형 마이크로전자 조립체의 제조 방법
TWI446498B (zh) * 2009-03-13 2014-07-21 泰斯拉公司 具有延伸穿越銲墊之通孔的堆疊微電子總成
US8207453B2 (en) 2009-12-17 2012-06-26 Intel Corporation Glass core substrate for integrated circuit devices and methods of making the same
US9420707B2 (en) 2009-12-17 2016-08-16 Intel Corporation Substrate for integrated circuit devices including multi-layer glass core and methods of making the same
WO2013133827A1 (en) 2012-03-07 2013-09-12 Intel Corporation Glass clad microelectronic substrate
US9001520B2 (en) 2012-09-24 2015-04-07 Intel Corporation Microelectronic structures having laminated or embedded glass routing structures for high density packaging
US9615453B2 (en) 2012-09-26 2017-04-04 Ping-Jung Yang Method for fabricating glass substrate package
US10622310B2 (en) 2012-09-26 2020-04-14 Ping-Jung Yang Method for fabricating glass substrate package

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5343064A (en) * 1988-03-18 1994-08-30 Spangler Leland J Fully integrated single-crystal silicon-on-insulator process, sensors and circuits
US5347154A (en) * 1990-11-15 1994-09-13 Seiko Instruments Inc. Light valve device using semiconductive composite substrate
JP2821830B2 (ja) * 1992-05-14 1998-11-05 セイコーインスツルメンツ株式会社 半導体薄膜素子その応用装置および半導体薄膜素子の製造方法
JP2773660B2 (ja) * 1994-10-27 1998-07-09 日本電気株式会社 半導体装置
EP0732757A3 (en) * 1995-03-15 1998-03-18 AT&T Corp. N-channel field-effect transistor including a thin-film fullerene
US6372534B1 (en) * 1995-06-06 2002-04-16 Lg. Philips Lcd Co., Ltd Method of making a TFT array with photo-imageable insulating layer over address lines
US5821621A (en) * 1995-10-12 1998-10-13 Texas Instruments Incorporated Low capacitance interconnect structure for integrated circuits

Also Published As

Publication number Publication date
US6177707B1 (en) 2001-01-23
JP2001526842A (ja) 2001-12-18
WO1999045588A3 (en) 1999-12-23
EP0985228A1 (en) 2000-03-15
WO1999045588A2 (en) 1999-09-10

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