JP4512125B2 - 応力分布検出用半導体パッケージ群及びそれを用いた半導体パッケージの応力分布検出方法 - Google Patents
応力分布検出用半導体パッケージ群及びそれを用いた半導体パッケージの応力分布検出方法 Download PDFInfo
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- JP4512125B2 JP4512125B2 JP2007233092A JP2007233092A JP4512125B2 JP 4512125 B2 JP4512125 B2 JP 4512125B2 JP 2007233092 A JP2007233092 A JP 2007233092A JP 2007233092 A JP2007233092 A JP 2007233092A JP 4512125 B2 JP4512125 B2 JP 4512125B2
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- 239000004065 semiconductor Substances 0.000 title claims description 241
- 238000000034 method Methods 0.000 title claims description 27
- 238000001514 detection method Methods 0.000 claims description 183
- 239000011347 resin Substances 0.000 claims description 38
- 229920005989 resin Polymers 0.000 claims description 38
- 238000007789 sealing Methods 0.000 claims description 35
- 238000005259 measurement Methods 0.000 claims description 19
- 239000010410 layer Substances 0.000 description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 27
- 229920005591 polysilicon Polymers 0.000 description 27
- 238000009792 diffusion process Methods 0.000 description 19
- 239000000758 substrate Substances 0.000 description 17
- 239000003990 capacitor Substances 0.000 description 14
- 239000011229 interlayer Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 230000008859 change Effects 0.000 description 8
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- 230000009471 action Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005538 encapsulation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000003938 response to stress Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 235000013599 spices Nutrition 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/16—Measuring force or stress, in general using properties of piezoelectric devices
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01L—MEASURING FORCE, STRESS, TORQUE, WORK, MECHANICAL POWER, MECHANICAL EFFICIENCY, OR FLUID PRESSURE
- G01L1/00—Measuring force or stress, in general
- G01L1/20—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress
- G01L1/22—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges
- G01L1/2287—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges constructional details of the strain gauges
- G01L1/2293—Measuring force or stress, in general by measuring variations in ohmic resistance of solid materials or of electrically-conductive fluids; by making use of electrokinetic cells, i.e. liquid-containing cells wherein an electrical potential is produced or varied upon the application of stress using resistance strain gauges constructional details of the strain gauges of the semi-conductor type
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Measuring Fluid Pressure (AREA)
- Pressure Sensors (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
ここで同一の樹脂封止構造とは、リードフレームや配線基板などの配線部材、電極パッドと配線部材を接続するためのボンディングワイヤーや半田バンプなどの接続端子、及び封止樹脂の構造が同一であることを意味する。
ここで4端子法とは、抵抗素子に電流を供給する回路と、抵抗素子の2箇所の電圧を測定する回路を独立させて抵抗素子の抵抗値の測定を行なう方法である。電圧計の内部抵抗は非常に高く、電圧測定回路には電流がほとんど流れないので、4端子法によれば配線抵抗や接触抵抗等による電圧降下を無視して抵抗値を精度よく測定できる。
1枚のウエハ内の任意の異なる場所(6領域)から図1に示した17個の応力検出用半導体チップ1をそれぞれ採取し、合計102個の応力検出用半導体チップについてピエゾ抵抗素子の抵抗値変化率を測定して、測定データの精度及び再現性を検証した。
本願発明者らは、他のチップサイズに対しても同様の結果を得ており、本願発明の応力分布検出用半導体パッケージ群及びそれを用いた半導体パッケージの応力分布検出方法が十分な測定精度と再現性をもっていることが確認できた。
さらに、トランジスタのチャネル幅:Wとチャネル長:Lの比=W/Lが同じであれば同じチャネル抵抗が得られることから、トランジスタサイズの縮小が可能であり、結果として微小エリアの応力測定が可能となる。
3 応力検出用のピエゾ抵抗素子
5 電極パッド
9 仮想半導体チップ
11 応力分布検出用半導体パッケージ
17 モールド樹脂(封止樹脂)
23 応力検出用のMOSトランジスタ
31 応力検出用のバイポーラトランジスタ
33 応力検出用の2層ポリシリコン容量素子
Claims (4)
- 複数個の応力分布検出用半導体パッケージによって構成され、
それらの応力分布検出用半導体パッケージは同一サイズの応力検出用半導体チップを同一の樹脂封止構造で樹脂封止したものであり、
前記応力検出用半導体チップは、応力検出用のピエゾ素子と、前記ピエゾ素子の電気特性を測定するために前記ピエゾ素子に電気的に接続された少なくとも2つの電極パッドを備え、
それらの応力分布検出用半導体パッケージで前記ピエゾ素子は前記応力検出用半導体チップ上で互いに異なる位置に形成されている応力分布検出用半導体パッケージ群。 - 前記ピエゾ素子は拡散抵抗からなるピエゾ抵抗素子であり、
4端子法による前記ピエゾ抵抗素子の抵抗値測定を可能にすべく、前記応力検出用半導体チップは少なくとも4つの前記電極パッドを備え、前記ピエゾ抵抗素子に少なくとも4つの前記電極パッドが電気的に接続されている請求項1に記載の応力分布検出用半導体パッケージ群。 - 請求項1に記載された応力分布検出用半導体パッケージ群を用い、
各応力検出用半導体チップについて樹脂封止をする前に前記ピエゾ素子の電気特性を測定し、
前記応力検出用半導体チップをそれぞれ樹脂封止して前記応力分布検出用半導体パッケージを形成し、
各応力分布検出用半導体パッケージについて前記ピエゾ素子の電気特性を測定し、
樹脂封止前後での各ピエゾ素子の電気特性の変動を前記応力検出用半導体チップと同一平面サイズの1つの仮想半導体チップ平面内に重ね合わせることにより樹脂封止に伴って前記応力検出用半導体チップに加わる応力の分布を検出する半導体パッケージの応力分布検出方法。 - 前記ピエゾ素子は拡散抵抗からなるピエゾ抵抗素子であり、
4端子法による前記ピエゾ抵抗素子の抵抗値測定を可能にすべく、前記応力検出用半導体チップとして、少なくとも4つの前記電極パッドを備え、前記ピエゾ抵抗素子に少なくとも4つの前記電極パッドが電気的に接続されているものを用い、前記ピエゾ抵抗素子の抵抗値を測定する際に4端子法を用いる請求項3に記載の半導体パッケージの応力分布検出方法。
Priority Applications (3)
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JP2007233092A JP4512125B2 (ja) | 2007-09-07 | 2007-09-07 | 応力分布検出用半導体パッケージ群及びそれを用いた半導体パッケージの応力分布検出方法 |
US12/201,350 US7735375B2 (en) | 2007-09-07 | 2008-08-29 | Stress-distribution detecting semiconductor package group and detection method of stress distribution in semiconductor package using the same |
US12/758,549 US7934429B2 (en) | 2007-09-07 | 2010-04-12 | Stress-distribution detecting semiconductor package group and detection method of stress distribution in semiconductor package using the same |
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JP2007233092A JP4512125B2 (ja) | 2007-09-07 | 2007-09-07 | 応力分布検出用半導体パッケージ群及びそれを用いた半導体パッケージの応力分布検出方法 |
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JP4512125B2 true JP4512125B2 (ja) | 2010-07-28 |
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JP4512125B2 (ja) * | 2007-09-07 | 2010-07-28 | 株式会社リコー | 応力分布検出用半導体パッケージ群及びそれを用いた半導体パッケージの応力分布検出方法 |
KR20090055316A (ko) * | 2007-11-28 | 2009-06-02 | 삼성전자주식회사 | 반도체 패키지와, 이를 구비하는 전자 기기 및 반도체패키지의 제조방법 |
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JP2012064698A (ja) | 2010-09-15 | 2012-03-29 | Ricoh Co Ltd | 半導体装置及びそのレイアウト方法 |
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JP2005209827A (ja) * | 2004-01-22 | 2005-08-04 | Hitachi Ulsi Systems Co Ltd | 半導体装置 |
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JPH07235578A (ja) | 1994-02-25 | 1995-09-05 | Matsushita Electron Corp | 応力評価用半導体装置 |
US6332359B1 (en) * | 1997-04-24 | 2001-12-25 | Fuji Electric Co., Ltd. | Semiconductor sensor chip and method for producing the chip, and semiconductor sensor and package for assembling the sensor |
US6222145B1 (en) * | 1998-10-29 | 2001-04-24 | International Business Machines Corporation | Mechanical strength die sorting |
JP2007255953A (ja) * | 2006-03-22 | 2007-10-04 | Hitachi Ltd | 力学量測定装置 |
US7714433B2 (en) * | 2007-03-09 | 2010-05-11 | Intel Corporation | Piezoelectric cooling of a semiconductor package |
JP4491002B2 (ja) * | 2007-08-31 | 2010-06-30 | 株式会社東芝 | 半導体集積回路装置 |
JP4512125B2 (ja) * | 2007-09-07 | 2010-07-28 | 株式会社リコー | 応力分布検出用半導体パッケージ群及びそれを用いた半導体パッケージの応力分布検出方法 |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH11274229A (ja) * | 1998-03-24 | 1999-10-08 | Matsushita Electric Works Ltd | 半導体装置 |
JPH11304614A (ja) * | 1998-04-22 | 1999-11-05 | Matsushita Electric Works Ltd | 半導体装置 |
JP2002039888A (ja) * | 2000-07-26 | 2002-02-06 | Denso Corp | 半導体圧力センサのゲージ抵抗の位置設定方法 |
JP2005209827A (ja) * | 2004-01-22 | 2005-08-04 | Hitachi Ulsi Systems Co Ltd | 半導体装置 |
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US7735375B2 (en) | 2010-06-15 |
US20090064791A1 (en) | 2009-03-12 |
US7934429B2 (en) | 2011-05-03 |
JP2009065052A (ja) | 2009-03-26 |
US20100193887A1 (en) | 2010-08-05 |
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