JP2012253155A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2012253155A
JP2012253155A JP2011123719A JP2011123719A JP2012253155A JP 2012253155 A JP2012253155 A JP 2012253155A JP 2011123719 A JP2011123719 A JP 2011123719A JP 2011123719 A JP2011123719 A JP 2011123719A JP 2012253155 A JP2012253155 A JP 2012253155A
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Prior art keywords
semiconductor chip
sealing
distribution
plane distribution
impurity concentration
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JP2011123719A
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English (en)
Inventor
Yuichiro Suzuki
裕一郎 鈴木
Atsushi Narasaki
敦司 楢崎
Yoshiaki Terasaki
芳明 寺崎
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2011123719A priority Critical patent/JP2012253155A/ja
Priority to US13/358,868 priority patent/US20120309117A1/en
Priority to DE102012203928A priority patent/DE102012203928A1/de
Priority to KR1020120054028A priority patent/KR20120135042A/ko
Priority to CN201210175363XA priority patent/CN102810486A/zh
Publication of JP2012253155A publication Critical patent/JP2012253155A/ja
Withdrawn legal-status Critical Current

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Abstract

【課題】封止後の半導体チップの耐圧及びリーク電流の面内分布を均一にすることができる半導体装置の製造方法を得る。
【解決手段】封止後の半導体チップの耐圧及びリーク電流の面内分布が均一になるような、封止前の半導体チップのＰＮ接合部の不純物濃度の面内分布を求める。この求めた不純物濃度の面内分布を持つＰＮ接合部を半導体チップの裏面側に形成する。このＰＮ接合部を形成した後に、半導体チップを樹脂で封止する。
【選択図】図９

Description

本発明は、半導体チップが樹脂で封止された樹脂封止型の半導体装置の製造方法に関する。
半導体チップが樹脂で封止された樹脂封止型の半導体装置が広く用いられている。このような半導体装置において、樹脂と半導体チップの熱膨張係数の違いにより熱応力が発生する。また、ワイヤやリードフレームと半導体チップとの接合面に電流が集中して発熱する。従って、封止後の半導体チップの応力分布や温度分布が不均一になり、封止後の半導体チップの電気特性の面内分布がばらつくという問題がある。近年、高性能化・低コスト化のために、半導体チップ厚を２００ｕｍ以下とする極薄化や、電流密度を１００Ａ／ｃｍ２以上とする大電流密度化が進んでいるので、上記の問題は特に顕著である。
この問題に対して、封止後の半導体チップに加わる応力分布に基づいて不純物濃度の分布を変えることで、半導体チップのＯＮ状態での電気特性の面内分布を均一にする方法が提案されている（例えば、特許文献１参照）。
特開平２−１４５７５号公報
しかし、従来技術では、封止後の半導体チップのＯＦＦ状態での電気特性である耐圧及びリーク電流の面内分布を均一にすることはできなかった。このため、信頼性が低下するという問題があった。
本発明は、上述のような課題を解決するためになされたもので、その目的は封止後の半導体チップの耐圧及びリーク電流の面内分布を均一にすることができる半導体装置の製造方法を得るものである。
本発明は、半導体チップを樹脂で封止する半導体装置の製造方法において、封止前後の前記半導体チップの耐圧及びリーク電流の面内分布の変化を求める工程と、この計算の結果に基づいて、封止後の前記半導体チップの耐圧及びリーク電流の面内分布が均一になるように、封止前の前記半導体チップの耐圧及びリーク電流の面内分布を調整する工程とを備えることを特徴とする。
本発明により、封止後の半導体チップの耐圧及びリーク電流の面内分布を均一にすることができる。
本発明の実施の形態に係る半導体装置を示す断面図である。 本発明の実施の形態に係る半導体チップの製造工程を示す断面図である。 本発明の実施の形態に係る半導体チップの製造工程を示す断面図である。 本発明の実施の形態に係る半導体チップの製造工程を示す断面図である。 本発明の実施の形態に係る半導体チップの製造工程を示す断面図である。 本発明の実施の形態に係る半導体チップの製造工程を示す断面図である。 本発明の実施の形態に係る半導体チップの製造工程を示す断面図である。 本発明の実施の形態に係る半導体チップの製造工程を示す断面図である。 ＰＮ接合部の不純物濃度の面内分布を求める方法のフローチャートである。 半導体チップの耐圧及びリーク電流の面内分布と応力分布や温度分布との相関を求める方法を示す平面図である。 封止前の半導体チップを表面側から見た平面図である。 図１１のＩ−ＩＩに印加される応力を求めた結果を示す図である。 Ｎ型バッファ領域のＮ型不純物濃度、Ｐ型コレクタ領域のＰ型不純物濃度、及び半導体チップの温度に対する耐圧及びリーク電流の関係を示す図である。 封止後の半導体チップの耐圧及びリーク電流の面内分布が均一になるような、封止前の半導体チップのＮ型バッファ領域の不純物濃度の面内分布を裏面側から見た平面図である。
図１は、本発明の実施の形態に係る半導体装置を示す断面図である。半導体チップ１の裏面は、導電性接合材２により電極基板３に接合されている。導電性接合材２は、半田、Ａｇペースト、導電性接着剤などである。電極基板３は、熱伝導率の優れた絶縁シート４を介して放熱板５上に実装されている。半導体チップ１の表面は、ＡｌやＣｕなどのワイヤ６により外部配線端子７に接続されている。半導体チップ１、電極基板３の一部、絶縁シート４、放熱板５の一部、ワイヤ６、及び外部配線端子７の一部は、絶縁性の樹脂８で封止されている。
続いて、半導体チップ１の製造工程について図面を参照して説明する。図２〜図８は、本発明の実施の形態に係る半導体チップの製造工程を示す断面図である。ここでは、半導体チップ１はＩＧＢＴ（Insulated Gate Bipolar Transistor）である。ただし、半導体チップ１はＩＧＢＴに限らず、ＭＯＳＦＥＴ（Metal-Oxide-Semiconductor Field-Effect Transistor）やダイオードでもよい。
まず、図２に示すように、Ｎ−型半導体基板９の表面側にＰ型不純物イオンを注入して拡散させて、Ｐ型ベース領域１０を形成する。Ｎ−型半導体基板９はＳｉ、ＧａＡｓ、ＧａＮ、ＳｉＣなどからなる。次に、図３に示すように、Ｐ型ベース領域１０の一部にＮ型不純物イオンを注入して拡散させて、Ｎ＋型ソース領域１１を形成する。
次に、図４に示すように、Ｎ＋型ソース領域１１及びＰ型ベース領域１０を貫通するトレンチを形成して、トレンチ内にゲート絶縁膜１２を介してゲート電極１３を埋め込む。ゲート電極１３上に層間絶縁膜１４を形成し、表面全面にエミッタ電極１５を形成する。
次に、図５に示すように、Ｎ−型半導体基板９を裏面側から所定の厚さまで研削する。次に、図６に示すように、Ｎ−型半導体基板９の裏面全面にＮ型不純物イオンを注入して拡散させて、Ｎ＋型バッファ領域１６を形成する。次に、図７に示すように、Ｎ−型半導体基板９の裏面側全面にＰ型不純物イオンを注入して拡散させて、Ｐ＋型コレクタ領域１７を形成する。
最後に、図８に示すように、Ｎ−型半導体基板９の裏面全面にコレクタ電極１８を形成する。以上の工程により半導体チップ１が製造される。ここで、半導体チップ１の表面側にＭＯＳ構造１９が設けられ、半導体チップ１の裏面側にＰＮ接合部２０が設けられている。
続いて、本発明の実施の形態に係る半導体装置の製造方法を説明する。まず、半導体チップ１を樹脂８で封止する前に、封止後の半導体チップ１の耐圧及びリーク電流の面内分布が均一になるような、封止前の半導体チップ１のＰＮ接合部２０（Ｎ＋型バッファ領域１６及びＰ＋型コレクタ領域１７）の不純物濃度の面内分布を求める。
次に、この求めた不純物濃度の面内分布を持つＰＮ接合部２０を半導体チップ１の裏面側に形成する。その後に、半導体チップ１をワイヤ６により外部配線端子７に接続し、半導体チップ１を樹脂８で封止する。
なお、不純物濃度分布を形成する方法として、例えばイオン注入装置の走査スピードを変動させる方法がある。これにより、イオン注入装置のプロセス条件を変更するだけで新たな工程を追加すること無く、不純物濃度分布を形成することができる。または、不純物濃度分布に対応したフォトレジストマスクやステンシルマスクを用いて半導体基板に不純物イオンを打ち込んでもよい。この場合、既存の写真製版プロセスを用いるため、微細な不純物濃度分布を形成することができる。
続いて、ＰＮ接合部の不純物濃度の面内分布を求める方法について、図９のフローチャートを参照して詳細に説明する。
まず、パッケージ形状や樹脂８の材質に基づいて封止後の半導体チップ１に加わる応力分布を求める。（ステップＳ１）。例えば、ＦＥＭ解析を用いてシミュレーションにより応力分布を計算する。または、半導体チップ１の面内にピエゾ素子又は歪ゲージ等の応力測定素子を配置して応力分布を実測する。
また、ワイヤ６の位置に基づいて封止後の半導体チップ１に流れる電流の密度分布を求め、その電流の密度分布から封止後の半導体チップ１の温度分布を求める（ステップＳ２）。例えば、シミュレーションにより半導体チップ１の温度分布を計算する。または、サーモビューア等を用いて半導体チップ１の温度分布を実測する。
次に、半導体チップ１の耐圧及びリーク電流の面内分布と応力分布や温度分布との相関を求める（ステップＳ３）。例えば、図１０に示すように、半導体チップ１の面内の各領域に、ピエゾ素子等の応力測定素子２１、温度測定素子２２、及び半導体チップ１よりも大幅に小さな半導体素子２３を配置する。そして、半導体チップ１に応力を与えた状態で応力測定素子２１により応力を測定し、温度測定素子２２により温度を測定すると同時に、半導体素子２３の耐圧及びリーク電流を測定する。これにより、半導体チップ１の耐圧及びリーク電流の面内分布と応力分布や温度分布との相関を算出することができる。なお、温度測定素子２２を用いる代わりに、熱電対やサーモビューア等を用いて半導体チップ１の温度を測定してもよい。
次に、半導体チップ１の耐圧及びリーク電流と応力分布又は温度分布との相関から、封止後の半導体チップ１の耐圧及びリーク電流の面内分布を求める（ステップＳ４）。
最後に、封止後の半導体チップ１の耐圧及びリーク電流の面内分布が均一になるような、封止前の半導体チップ１のＰＮ接合部２０の不純物濃度の面内分布を求める（ステップＳ５）。
図１１は、封止前の半導体チップを表面側から見た平面図である。終端領域２４内に、エミッタ電極１５とゲートパッド２５が配置されている。エミッタ電極１５にワイヤ６が接合されている。
図１２は、図１１のＩ−ＩＩに印加される応力を求めた結果を示す図である。図１２には、Ａ，Ｂ，Ｃの応力を半導体チップ１に加えた場合の耐圧の変動値も示されている。封止後、半導体チップ１の中央部Ｉには角部ＩＩと比べて大きな圧縮応力が加わり、応力に比例して耐圧の変動幅も大きくなる。また、半導体チップ１のワイヤ６が接合される領域は、トランジスタ動作時に周辺の領域から電流が集まるため、周辺の領域よりも温度が上昇する。
図１３は、Ｎ＋型バッファ領域１６のＮ型不純物濃度、Ｐ＋型コレクタ領域１７のＰ型不純物濃度、及び半導体チップ１の温度に対する耐圧及びリーク電流の関係を示す図である。不純物濃度が下がるか又は温度が上がるほど、耐圧は下がり、リーク電流は上がる。
図１４は、封止後の半導体チップ１の耐圧及びリーク電流の面内分布が均一になるような、封止前の半導体チップ１のＮ＋型バッファ領域１６の不純物濃度の面内分布を裏面側から見た平面図である。中央の領域２６は不純物濃度が大きい。領域２７の不純物濃度は領域２６よりも小さく、領域２８の不純物濃度は領域２７よりも更に小さい。領域２９は、ワイヤ６が接合される領域であり、不純物濃度が大きい。なお、ここではＮ＋型バッファ領域１６について説明するが、Ｐ＋型コレクタ領域１７でも同様である。
半導体チップ１のＮ−型半導体基板９に応力が加わると、耐圧が下がり、リーク電流が上がる。そこで、封止後に応力が加わる領域２６のＮ＋型バッファ領域１６の不純物濃度を相対的に上げる。これにより、領域２６の封止前の耐圧が相対的に上がるため、封止後の半導体チップ１の耐圧及びリーク電流の面内分布が均一になる。
また、半導体チップ１のワイヤ６が接合される領域２９は、トランジスタ動作時に周辺の領域からワイヤ６に向かって電流が集まるため、周辺の領域よりも温度が上昇し、耐圧が下がり、リーク電流が上がる。そこで、領域２９のＮ＋型バッファ領域１６の不純物濃度を相対的に上げる。これにより、ワイヤ６に電流を流し温度が上昇した場合でも、封止後の半導体チップ１の耐圧及びリーク電流の面内分布が均一になる。
以上説明したように、本実施の形態では、封止後の半導体チップ１の耐圧及びリーク電流の面内分布が均一になるような、封止前の半導体チップ１のＰＮ接合部２０の不純物濃度の面内分布を予め求める。そして、この求めた不純物濃度の面内分布を持つＰＮ接合部２０を半導体チップ１の裏面側に形成する。その後に、半導体チップ１を樹脂８で封止する。これにより、封止後の半導体チップ１の耐圧及びリーク電流の面内分布を均一にすることができる。このため、半導体装置の信頼性を向上させることができる。
１ 半導体チップ
８ 樹脂
１９ ＭＯＳ構造
２０ ＰＮ接合部

Claims (3)

  1. 表面側にＭＯＳ構造が設けられ裏面側にＰＮ接合部が設けられた半導体チップを樹脂で封止する半導体装置の製造方法において、
    封止後の前記半導体チップの耐圧及びリーク電流の面内分布が均一になるような、封止前の前記半導体チップの前記ＰＮ接合部の不純物濃度の面内分布を求める工程と、
    この求めた不純物濃度の面内分布を持つ前記ＰＮ接合部を前記半導体チップの裏面側に形成する工程と、
    前記ＰＮ接合部を形成した後に前記半導体チップを前記樹脂で封止する工程とを備えることを特徴とする半導体装置の製造方法。
  2. 前記ＰＮ接合部の不純物濃度の面内分布を求める工程は、
    封止後の前記半導体チップに加わる応力分布を求める工程と、
    前記半導体チップの耐圧及びリーク電流と前記応力分布との相関から、封止後の前記半導体チップの耐圧及びリーク電流の面内分布を求める工程とを有することを特徴とする請求項１に記載の半導体装置の製造方法。
  3. 前記ＰＮ接合部の不純物濃度の面内分布を求める工程は、
    封止後の前記半導体チップに流れる電流の密度分布から封止後の前記半導体チップの温度分布を求める工程と、
    前記半導体チップの耐圧及びリーク電流と前記温度分布との相関から、封止後の前記半導体チップの耐圧及びリーク電流の面内分布を求める工程とを有することを特徴とする請求項１又は２に記載の半導体装置の製造方法。
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JPH0214575A (ja) 1988-06-30 1990-01-18 Mitsubishi Electric Corp 半導体装置
US20040026764A1 (en) * 2002-08-06 2004-02-12 Fumihiko Hirose Low-loss bipolar transistor and method of manufacturing the same
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