JP4495464B2 - 集積回路の製造方法 - Google Patents

集積回路の製造方法 Download PDF

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JP4495464B2
JP4495464B2 JP2003562972A JP2003562972A JP4495464B2 JP 4495464 B2 JP4495464 B2 JP 4495464B2 JP 2003562972 A JP2003562972 A JP 2003562972A JP 2003562972 A JP2003562972 A JP 2003562972A JP 4495464 B2 JP4495464 B2 JP 4495464B2
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JP2005516391A5 (US07060634-20060613-C00017.png
JP2005516391A (ja
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ランタラ ユハ
リード ジェイソン
トルマネン テーム
ヴィスワナタン ヌンガヴァラム
マーニネン アルト
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シレクス オサケユキチュア
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    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
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    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/101Forming openings in dielectrics
    • H01L2221/1015Forming openings in dielectrics for dual damascene structures
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    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
JP2003562972A 2002-01-17 2003-01-17 集積回路の製造方法 Expired - Fee Related JP4495464B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US34995502P 2002-01-17 2002-01-17
US39541802P 2002-07-13 2002-07-13
US41457802P 2002-09-27 2002-09-27
PCT/US2003/001490 WO2003063205A2 (en) 2002-01-17 2003-01-17 Poly(organosiloxane) materials and methods for hybrid organic-inorganic dielectrics for integrated circuit applications

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JP2005516391A JP2005516391A (ja) 2005-06-02
JP2005516391A5 JP2005516391A5 (US07060634-20060613-C00017.png) 2006-03-09
JP4495464B2 true JP4495464B2 (ja) 2010-07-07

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EP (1) EP1490454B1 (US07060634-20060613-C00017.png)
JP (1) JP4495464B2 (US07060634-20060613-C00017.png)
KR (1) KR100985272B1 (US07060634-20060613-C00017.png)
AU (1) AU2003216067A1 (US07060634-20060613-C00017.png)
WO (1) WO2003063205A2 (US07060634-20060613-C00017.png)

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