JP4473741B2 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

Info

Publication number
JP4473741B2
JP4473741B2 JP2005019293A JP2005019293A JP4473741B2 JP 4473741 B2 JP4473741 B2 JP 4473741B2 JP 2005019293 A JP2005019293 A JP 2005019293A JP 2005019293 A JP2005019293 A JP 2005019293A JP 4473741 B2 JP4473741 B2 JP 4473741B2
Authority
JP
Japan
Prior art keywords
silicon layer
layer
gate
semiconductor device
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2005019293A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006210555A5 (enExample
JP2006210555A (ja
Inventor
下 敦 寛 木
屋 義 規 土
賀 淳 二 古
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2005019293A priority Critical patent/JP4473741B2/ja
Priority to US11/211,746 priority patent/US20060163662A1/en
Priority to CNB2006100066428A priority patent/CN100448008C/zh
Publication of JP2006210555A publication Critical patent/JP2006210555A/ja
Priority to US12/193,668 priority patent/US20080308877A1/en
Publication of JP2006210555A5 publication Critical patent/JP2006210555A5/ja
Priority to US12/618,402 priority patent/US8357580B2/en
Application granted granted Critical
Publication of JP4473741B2 publication Critical patent/JP4473741B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28105—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor next to the insulator having a lateral composition or doping variation, or being formed laterally by more than one deposition step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28097—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a metallic silicide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0172—Manufacturing their gate conductors
    • H10D84/0179—Manufacturing their gate conductors the gate conductors having different shapes or dimensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3215—Doping the layers
    • H01L21/32155—Doping polycristalline - or amorphous silicon layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0278—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline channels on wafers after forming insulating device isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
JP2005019293A 2005-01-27 2005-01-27 半導体装置および半導体装置の製造方法 Expired - Lifetime JP4473741B2 (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP2005019293A JP4473741B2 (ja) 2005-01-27 2005-01-27 半導体装置および半導体装置の製造方法
US11/211,746 US20060163662A1 (en) 2005-01-27 2005-08-26 Semiconductor device and method of manufacturing semiconductor device
CNB2006100066428A CN100448008C (zh) 2005-01-27 2006-01-27 半导体器件和用于制造半导体器件的方法
US12/193,668 US20080308877A1 (en) 2005-01-27 2008-08-18 Semiconductor device and method of manufacturing semiconductor device
US12/618,402 US8357580B2 (en) 2005-01-27 2009-11-13 Semiconductor device and method of manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2005019293A JP4473741B2 (ja) 2005-01-27 2005-01-27 半導体装置および半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2006210555A JP2006210555A (ja) 2006-08-10
JP2006210555A5 JP2006210555A5 (enExample) 2009-10-15
JP4473741B2 true JP4473741B2 (ja) 2010-06-02

Family

ID=36695875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2005019293A Expired - Lifetime JP4473741B2 (ja) 2005-01-27 2005-01-27 半導体装置および半導体装置の製造方法

Country Status (3)

Country Link
US (3) US20060163662A1 (enExample)
JP (1) JP4473741B2 (enExample)
CN (1) CN100448008C (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4440080B2 (ja) * 2004-11-12 2010-03-24 株式会社東芝 半導体装置およびその製造方法
JP2007081249A (ja) * 2005-09-15 2007-03-29 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
CN1945852A (zh) * 2005-10-06 2007-04-11 松下电器产业株式会社 半导体装置及其制造方法
US20070090417A1 (en) * 2005-10-26 2007-04-26 Chiaki Kudo Semiconductor device and method for fabricating the same
JP2007173347A (ja) * 2005-12-20 2007-07-05 Renesas Technology Corp 半導体装置及びその製造方法
US20080093682A1 (en) * 2006-10-18 2008-04-24 Liang-Gi Yao Polysilicon levels for silicided structures including MOSFET gate electrodes and 3D devices
US20080237743A1 (en) * 2007-03-30 2008-10-02 Texas Instruments Incorporated Integration Scheme for Dual Work Function Metal Gates
US7482270B2 (en) * 2006-12-05 2009-01-27 International Business Machines Corporation Fully and uniformly silicided gate structure and method for forming same
US7550808B2 (en) * 2007-01-18 2009-06-23 International Business Machines Corporation Fully siliciding regions to improve performance
US20080173950A1 (en) * 2007-01-18 2008-07-24 International Business Machines Corporation Structure and Method of Fabricating Electrical Structure Having Improved Charge Mobility
JPWO2009101763A1 (ja) * 2008-02-12 2011-06-09 パナソニック株式会社 半導体装置及びその製造方法
US9934976B2 (en) * 2008-12-18 2018-04-03 Intel Corporation Methods of forming low interface resistance rare earth metal contacts and structures formed thereby
JP2010258124A (ja) * 2009-04-23 2010-11-11 Renesas Electronics Corp 半導体装置及び半導体装置の製造方法
US8642371B2 (en) * 2011-04-06 2014-02-04 Shamsoddin Mohajerzadeh Method and system for fabricating ion-selective field-effect transistor (ISFET)
US20140370643A1 (en) * 2011-08-22 2014-12-18 1366 Technologies Inc Formulation for acidic wet chemical etching of silicon wafers
US8629512B2 (en) 2012-03-28 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Gate stack of fin field effect transistor with slanted sidewalls
US9111783B2 (en) * 2012-04-13 2015-08-18 Renesas Electronics Corporation Semiconductor devices with self-aligned source drain contacts and methods for making the same
US8921178B2 (en) * 2012-05-16 2014-12-30 Renesas Electronics Corporation Semiconductor devices with self-aligned source drain contacts and methods for making the same
CN103854980B (zh) * 2012-11-29 2016-05-11 中国科学院微电子研究所 形成半导体器件替代栅的方法以及制造半导体器件的方法
EP3050103B1 (en) * 2013-09-27 2020-03-18 Intel Corporation Non-planar i/o and logic semiconductor devices having different workfunction on common substrate
US9520500B1 (en) * 2015-12-07 2016-12-13 International Business Machines Corporation Self heating reduction for analog radio frequency (RF) device
US10096596B2 (en) * 2015-12-15 2018-10-09 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device structure having a plurality of gate structures
KR102890787B1 (ko) * 2020-04-07 2025-11-26 삼성전자주식회사 게이트 스페이서를 갖는 반도체 소자들
US12490510B2 (en) * 2020-08-12 2025-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device and method of forming the same

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6335254B1 (en) * 2000-08-09 2002-01-01 Micron Technology, Inc. Methods of forming transistors
JP2002141420A (ja) * 2000-10-31 2002-05-17 Mitsubishi Electric Corp 半導体装置及びその製造方法
KR100495023B1 (ko) * 2000-12-28 2005-06-14 가부시끼가이샤 도시바 반도체 장치 및 그 제조 방법
US6372640B1 (en) * 2001-07-31 2002-04-16 Macronix International Co., Ltd. Method of locally forming metal silicide layers
ATE536634T1 (de) * 2002-12-20 2011-12-15 Nxp Bv Verfahren zur herstellung eines halbleiterbauelements

Also Published As

Publication number Publication date
US20100062575A1 (en) 2010-03-11
CN100448008C (zh) 2008-12-31
US8357580B2 (en) 2013-01-22
JP2006210555A (ja) 2006-08-10
US20080308877A1 (en) 2008-12-18
US20060163662A1 (en) 2006-07-27
CN1819200A (zh) 2006-08-16

Similar Documents

Publication Publication Date Title
JP4473741B2 (ja) 半導体装置および半導体装置の製造方法
US10741400B2 (en) Gate replacement structures in semiconductor devices
USRE45180E1 (en) Structure for a multiple-gate FET device and a method for its fabrication
CN104681615B (zh) 用于具有掩埋SiGe氧化物的FinFET器件的结构和方法
CN108666273B (zh) 半导体装置
TWI641135B (zh) 具有磊晶結構之鰭狀場效電晶體
CN103137705B (zh) 半导体装置及其制造方法
JP2009032955A (ja) 半導体装置、およびその製造方法
JP2009117557A (ja) 相補型半導体装置及びその製造方法
JP2014041974A (ja) 半導体装置およびその製造方法
CN101385150A (zh) 栅极具有不同功函数的双栅极半导体器件及其制造方法
JP2009152342A (ja) 半導体装置の製造方法
US20250359154A1 (en) Field effect transistor with dual silicide and method
JP3998665B2 (ja) 半導体装置およびその製造方法
CN114122135A (zh) 半导体结构
US8247279B2 (en) Method of fabricating semiconductor device using epitaxial growth inhibiting layers
CN115831752A (zh) 一种半导体器件及其制备方法
WO2014012263A1 (zh) 半导体器件及其制造方法
TW201135927A (en) Semiconductor device having metal gate and manufacturing methd thereof
US20250203955A1 (en) Field effect transistor having replacement source/drains and related methods
US20250063791A1 (en) Specialized transistors
US20250374611A1 (en) Protective hard mask and methods of making same
JP2006032712A (ja) 半導体装置及びその製造方法
JP2010050171A (ja) 半導体装置およびその製造方法
TW202221772A (zh) 填充結構及其製造方法

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090602

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090828

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20091104

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091216

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100209

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100305

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130312

Year of fee payment: 3

R151 Written notification of patent or utility model registration

Ref document number: 4473741

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130312

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130312

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140312

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term