201135927 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種具有金屬閘極(metal gate)之半導體 元件及其製作方法，尤指一種實施後閘極(gate last)製程之具 有金屬閘極之半導體元件及其製作方法。 【先前技術】 在習知半導體產業中，多晶矽係廣泛地應用於半導體元 件如金氧半導體（metal-oxide_semiconductor，MOS)電晶體 中，作為標準的閘極材料選擇。然而，隨著MOS電晶體尺 寸持續地微縮，傳統多晶石夕閘極因硼穿透(boron penetration) 效應導致元件效能降低，及其難以避免的空乏效應（depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容 值下降，進而導致元件驅動能力的衰退等困境。因此，半導 體業界更嘗以新的閘極材料，例如利用功函數(work function) 金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數 (High-K)閘極介電層的控制電極。 而在互補式金氧半導體（complementary metal-oxide semiconductor，CMOS)元件中，雙功函數金屬閘極一需與 201135927 NMOS元件搭配，一則需與pM〇s元件搭配，因此使得相關 元件的整合技術以及製程控制更形複雜，且各材料的厚度與 成为控制要求亦更形嚴苛。雙功函數金屬閘極之製作方法係 可概分為前閘極(gate first)製程及後閘極(gate last)製程兩大 類。其中前閘極製程會在形成金屬閘極後始進行源極/汲極超 淺接面活化回火以及形成金屬石夕化物等高熱預算製程，因此 使得材料的選擇與調整面對較多的挑戰。為避免上述高熱預 #算環境並獲得較寬的材料選擇，業界係提出以後閘極製程取 代前閘極製程之方法。 而習知後閘極製程中，係先形成一虛置閘極(dummy gate) 或取代閘極(replacement gate) ’並在完成一般M〇s電晶體的 製作後，將虛置/取代閘極移除而形成一閘極凹槽（gate trench)，再依電性需求於閘極凹槽内填入不同的金屬。由此 可知，後閘極製程雖可避免源極/汲極超淺接面活化回火以及 籲形成金屬石夕化物等高熱預算製程’而具有較寬廣的材料選 擇，但仍面臨複雜製程的整合性以及閘極凹槽填補能力等可 靠度要求。 【發明内容】 因此，本發明之一目的係在於提供一種實施後閘極製程 的具有金屬閘極之半導體元件製作方法。 201135927 艮據本發明所提供之申請專·圍，係提供—種且有金 屬閘極之半導體元件，該半導體元件包含有—半導體基底、 -形成於該半導體基底上之閘極介電層、以及至少—形成於 該閘極介電層上之第—導電型金屬閘極。該第—導電型金屬 閘極更包含有-填充金屬層，以及—設置於該閘極層斑 如真充金屬層之間的㈣金屬層，且該u型金屬層之一層最 南部分係低於該填充金屬層。 根據本發明所提供之巾料職圍，另提供—種且有全 屬閘極之半導體元狀製作綠。财时先提供-基底， 該基底表面形成有-第—導電型電晶體、—第二導電型電晶 體、以及-包圍該第-導電型電晶體與該第二導電型電晶體 之介電層。隨後，移除該第一導電型電晶體與該第二導電型 電晶體之-閘極導電層，而於第—導電型電晶體與該第二導 電型電晶體内分別形成—第-閘極溝渠(gate treneh)與-第 二閘極溝渠。接下來於該第—閘極溝渠與該第二閘極溝渠内 形成一阻障層；於該第—閘極溝渠内形成-U型金屬層，且 該U里金屬層係低於该第—閘極溝渠。最後於該第—間極溝 渠與該第二閘極溝渠内形成一第二金屬層。 根據本發明所提供之具有金屬閘極之半導體元件之製作 方法’各導電㉝電晶體皆是利用後閘極方法製作❿成，故此 201135927 時需要較高熱預算的製程皆已完成。且由於u型金屬層之設 -置’除可提供所需的功函數金屬，更可使後續填入閘極溝渠 •内的填充金屬層享有較佳的填補結果，確保半導體元件的可 靠度。 【實施方式】 請參閱第1圖至第8圖，第1圖至第8圖係為本發明所 ^供之具有金屬閘極之半導體元件之製作方法之一第一較 佳實施例之示意圖。如第1圖所示，首先提供一半導體基底 100，如一矽基底、含矽基底、或矽覆絕緣 (silicon-on-insulator，SOI)基底等，半導體基底100表面定 義有一第一主動區域110與一第二主動區域112,且半導體 基底100内係形成有複數個用以電性隔離第一主動區域110 與第二主動區域112之淺溝絕緣（shallow trench isolation， • STI) 102。接下來於第一主動區域110與第二主動區域112 内之半導體基底100上分別形成一第一導電型電晶體120與 一第二導電型電晶體122。在本較佳實施例中，第一導電型 電晶體120係為一 P型電晶體；而第二導電型電晶體122則 為一 N型電晶體，但熟習該項技藝之人士應知反之亦可。 如第1圖所示，第一導電型電晶體120與第二導電型電 晶體122各包含一閘極介電層104、一閘極導電層106如一 201135927 多晶石夕層、與一圖案化硬遮罩1〇8 ;其中閘極導電層1()6係 作為一虛置閘極或取代閘極。在本較佳實施例中，閘極介電 層104可為一傳統的二氧化矽層，亦可為一高介電常數 (high-K)閘極介電層，而此high_K閘極介電層係選自氮化 石夕（SiN)、氮氧化矽（Si〇N)以及金屬氧化物所組成之一群組， 其中金屬氧化物則包含氧化給(hafniuin oxide，HfO)、石夕酸給氧 化合物（hafnium silicon oxide，HfSiO)、石夕酸給氮氧化合物 (hafnium silicon oxynitride，HfSiON)、氧化！呂（aluminum oxide， A10)、乳化鑭（lanthanum oxide，LaO)、紹酸鑭（lanthanum aluminum oxide ’ LaAlO )、氧化組（tantalum oxide，TaO)、氧化錯（zirconium oxide ’ ZrO)、石夕酸錯氧化合物（zirconjum siiic〇n 〇xjde，ZrSiO)、 或錯酸給（hafnium zirconium oxide，HfZrO)等。 請繼續參閱第1圖。第一導電型電晶體12〇與第二導電 型電晶體122分別包含一第一輕摻雜汲極（light doped drain， LDD) 130與一第二LDD 132、一側壁子134、與一第一源極 /汲極140與一第二源極/汲極142。側壁子134可為一複合 膜層之結構，其可包含南溫氧化石夕層（high temperature oxide，ΗΤΟ)、SiN、SiO或使用六氣二矽烧 (hexachlorodisilane，Si2Cl6)形成的氮化矽（HCD-SiN)。另外， 在本較佳實施例中’亦可利用選擇性轰晶成長（selective epitaxial growth，SEG)方法來製作第一源極/汲極140與第二 源極/汲極142，例如，當第一導電型電晶體120為P型電晶 201135927 體，而第二導電型電晶體122為N型電晶體時，係可利用包 ' 含有鍺化矽（SiGe)之磊晶層以及包含碳化矽（si〇有之磊晶 - 層分別製作第一源極/汲極140與第二源極/汲極142，以利 用磊晶層與閘極通道矽之間的應力作用更改善電性表現。此 外，第一源極/沒極140與第二源極/汲極142表面係分別包 含有一金屬石夕化物144。而在形成第一導電型電晶體12〇與 第二導電型電晶體122之後，係於半導體基底1〇〇上依序形 ^ 成一接觸洞餘刻停止層（contact etch stop layer，CESL) 150 與一内層介電（inter-layer dielectric，ILD)層 152。 請參閱第2圖。接下來利用一平坦化製程，如一 CMP製 程，用以平坦化ILD層152與CESL 150，並移除圖案化硬 遮罩108，直至暴露出閘極導電層106。在平坦化製程後， 則利用一蝕刻製程移除第一導電型電晶體120與第二導電型 電晶體122之閘極導電層106，而於第一導電型電晶體120 • 與第二導電型電晶體122内分別形成一第一閘極溝渠(gate trench) 160與一第二閘極溝渠162。此時第一閘極溝渠160 與第二閘極溝渠162之開口係與ILD層152之表面共平面。 在本較佳實施例中’閘極介電層104係分別暴露於第一 閘極溝渠160與第二閘極溝渠162之底部，但熟習該項技藝 之人士應知，本第一較佳實施例所提供之方法亦不限於在移 除閘極導電層106後，更藉由一蝕刻製程移除閘極介電層 201135927 104。之後，再於第一閘極溝渠ι6〇與第二閘極溝渠ία之 底部重新形成一 high-K閘極介電層，以取代傳統的二氧化 矽層或氮氧化矽層作為閘極介電層，有效降地低物理極限厚 度。並期在相同的EOT下，有效降低漏電流並達成等效電 容以控制通道開關。 請參閱第3圖。接下來，於第一閘極溝渠160與第二閘 極溝渠162内依序形成一阻障層（barrier layer) 200與一第一 金屬層210。第一金屬層210可為一滿足P型電晶體所需功 函數要求的金屬，如氮化鈦(titanium nitride，TiN)或碳化組 (tantalum carbide，TaC)。然而值得注意的是，由於第一導電 型電晶體120為一 P型電晶體，而其金屬閘極之功函數係介 於4.8 eV與5.2 eV之間，因此本較佳實施例所提供的第一 金屬層210亦不限於任何適合的金屬材料。而阻障層200則 為一钱刻率異於第一金屬層210的膜層，如氮化组(tantalum nitride，TaN)。待上述膜層形成後，即於半導體基底1〇0上 再形成一填洞能力良好的犧牲層，如抗反射底層（bottom anti-reflective coating，BARC layer)、旋塗式玻璃（spin-on glass，SOG)、或光阻300，且光阻300係如第3圖所示填滿 第一閘極溝渠160與第二閘極溝渠162。 請參閱第4圖。接下來回蝕刻光阻3〇〇等之犧牲層，而 形成一圖案化光阻302。回蝕刻後的圖案化光阻302並未填 201135927 滿第一閘極溝渠160與第二閘極溝渠162，但須完整覆蓋並 保5蒦第一問極溝渠16〇與第二閘極溝渠162的底部；也就是 4 ’其向度並未超過第一閘極溝渠16〇與第二閘極溝渠162 的開口。值得注意的是，本較佳實施例所提供之圖案化光阻 302係如第4圖所示，用以定義一所欲獲得的u型金屬層所 形成的位置及高度。 φ 叫參閱第5圖。在形成圖案化光阻302之後，係於半導 體基底100上形成另一光阻（圖未示），並利用一微影製程 圖案化該光阻，而於第二主動區域112内形成一如第5圖所 不之圖案化光阻312。換句話說，圖案化光阻312係形成於 第二導電型電晶體122上，且暴露出第—主動區域11〇内的 第-閘極溝渠160。另外，熟f該項技藝之人士應知在形成 圖案化光阻312之前，係可對圖案化光阻3〇2進行一烘烤 (bake)步驟；甚或使用兩種關率不同的光阻材料分別形成 圖案化光阻302與圖案化光阻312，俾使形成圖案化光阻312 的微影製程不致影響到圖案化光阻3〇2。 睛繼續參閱第5圖。隨後進行一蝕刻製程，移除第一主 動區域110,即第-導電型電晶體12G上的部分第一金屬層 21〇。值得注意的是，第一閘極溝渠16〇内部分的第一金屬0 層210係由圖案化光阻302所保護，因此在钱刻製程後，係 於第一閘極溝渠160内形成一 u型金屬層212。且如第^圖 201135927 所不’U型金屬層212之任一 ϋ型最高部分係低於第一閘極 溝渠160之開口。另外，由於ILD層152之表面與第一問極 溝渠160及第二閘極溝渠162之開口共平面，因此口型金屬 層212之任一 U型最高部分亦可視為低於ILD層152。 請參閱第6圖。接下來，依序移除圖案化光阻312以及 第-閘極溝渠160與第二閘極溝渠162内的圖案化光阻 302 〇之後，係於第一主動區域11〇，即於第一導電型電晶體 120上再形成一圖案化光阻322 〇如第6圖所示，圖案化光 阻322係暴露出第二主動區域112。隨後係進行一钱刻製 私移除第一主動區域112内，詳細地說，係移除第二導電 型電日'體122上與第二閘極溝渠162内之第一金屬層21〇。 另外值得注意的是，由於阻障層細的存在，在移除第一金 屬層210的银刻製程中，第二閘極溝渠162底部的閘極介電 層104係受到阻障層2〇〇的保護而不致受到損害。 請參閱第7圖。接下來，移除圖案化光阻322,之後於半 導體基底1〇〇上依序形成一第二金屬122〇與一第三金屬層 230’且第三金屬層23〇係填滿第一間極溝渠⑽與第二閘 極溝渠162。此外’亦可依產品特性與製程所需，在形成第 -金屬層22〇與第三金屬層230之前先行移除阻障潛細。 請參閱第8圖。在形成第二金屬層22〇與一第三金屬層 12 201135927 230以填滿第1極溝渠16G與第二閘極溝渠162後，係可 進打另-平坦化製程’用以移除多餘的第三金屬層23〇、第 二金屬層22〇與阻障層細，而獲得—約略平坦之表面，並 完成第-導電型金屬閘極17G與第二導電型金屬閘極Μ之 製作。且平坦化製程之後，几㈣152之表面係與第一導電 型金屬閘極170與第二導電型金屬開極172之頂部表面共平 面。上述平坦化製程係為該熟f該技藝之人士所知者，故於 此係不再贅述。 請仍然參閱第8圖。如前所述，本較佳實施例中第 則為- Ν型電晶體。故在第一導電型金屬問極ΐ72中，㈣ 金屬層212係用以調節功函數，使第一導電型金屬閘極 ^力函數介於4.8電子伏特(eV)#52eV之間。由於口型金 層212係用以滿足第一導電型金屬閘極17〇的功函數要 ί第因=導電型金屬閘極Π〇來說，第二金屬層22〇 金:層230可視為一複合型態的填充金屬層。值得注 思金屬層212的形狀特徵’第一開極溝渠 =的上半部開口可維持原來大小’並有效降低第一間極溝 渠160的深寬比(aspect rati〇)，故第二金屬層咖盘第三金 =30可順利填入，得以避免填補第一間極溝渠 生縫隙(細），確保第一導電型金屬閘極17〇的可靠产 13 201135927 另外’由於覆蓋第一閘極溝渠160底部之部分U型金屬 層212對於功函數的影響係大於與覆蓋第一閘極溝渠160側 壁之部分U型金屬層212，因此圖案化光阻302更可選自一 钱刻率與第一金屬層210約略相同的光阻材料，甚或其他合 適的犧牲材料。據此，圖案化光阻302與覆蓋第一閘極溝渠 160側壁之部分第一金屬層210可能在蝕刻製程中一併消 耗’並以不傷害覆蓋第一閘極溝渠160底部的第一金屬層 210為蝕刻製程控制考量，降低U型金屬層212的最高點與 最低點高度差異’故可獲得一較扁平的U型金屬層212，使 得後續形成的第二金屬層220與第三金屬層230更易填入第 一閘極溝渠160。 請繼續參閱第8圖。第二金屬層220係選自鋁化鈦 (TiAl)、鋁化錯(ZrAl)、鋁化鎢（WA1)、鋁化鈕（TaAl)或鋁化 銓(HfAl)所組成之一群組。第三金屬層230則選自鋁(Ai)、 鈦(Ti)、钽(Ta)、鎢(W)、鈮(Nb)、鉬（Mo)、銅（Cu)、氮化鈦 (TiN)、碳化鈦(TiC)、氮化鈕(TaN)、鈦鎢（Ti/W) '或鈦與氮 化鈦(Ti/TiN)等複合金屬所組成之一群組，此外第三金屬層 230亦可為一複合金屬層。因此，在第二導電型金屬閘極ι72 中，第二金屬層220係用以調節功函數’使第二導電型金屬 閘極172的功函數介於3·9 eV與4.3 eV之間。由於第二金 屬層220係用以滿足第二導電型金屬閘極Π2的功函數要 求，因此對第二導電变金屬閘極172來說’第三金屬層230 201135927 即作為其填充金屬層。 . 接下來請參閱第9圖至第10圖，第9圖至第10圖係為 本發明所提供之具有金屬閘極之半導體元件之製作方法之 々第一較佳實施例之示意圖。由於第二較佳實施例中，形成 第一導電型電晶體120與第二導電型電晶體122、形成第一 閘極溝渠160與第二閘極溝渠162、形成阻障層2〇〇與第一 φ金屬層210、以及形成圖案化光阻3〇2之步驟係與第一較佳 實她例相同’因此該等步驟及相同之元件係可參閱上述所揭 露以及第1圖至第4圖所繪示者，而不再贅述。 4參閱第4圖與第9圖。在第一閘極溝渠16〇與第二閘 極溝渠162形成圖案化光阻3〇2之後，係直接進行一蝕刻製 程，以移除第一閘極溝渠！ 6 〇與第二閘極溝 2 案化光阻層302覆蓋之第一金屬層210，而於第一 • 160與第二閘極溝渠162时別形成一如第9圖所示之〇型 金屬層212。由於阻障層200與第一金屬層21〇的蝕刻率差 異，上述蝕刻製程係可準確停止在阻障層2〇〇處，不致於傷 害到1〇)層152以及第一閘極溝渠16〇與第二閘極溝渠； 之側壁。 請參閱第10圖。接下來，係於第一主動區域11()，即第 一導電型電晶體120上形成一圖案化光阻層332。如第 15 201135927 圖所示，圖案化光阻層332係暴露出第二主動區域112。隨 後係進行一蝕刻製程，移除第二主動區域112内，尤其是第 二閘極溝渠162内之U型金屬層212。如前所述，由於阻障 層200的存在，因此在移除U型金屬層212的蝕刻製程中， 第二閘極溝渠162底部的閘極介電層104係受到阻障層200 的保護而不致受到損害。同樣地，可使用兩種蝕刻率不同的 光阻材料分別形成圖案化光阻302與圖案化光阻332，或控 制圖案化光阻332與圖案化光阻302的厚度比例，俾使蝕刻 第二主動區域112，尤其是移除第二閘極溝渠162内之圖案 化光阻302與U型金屬層212時，不影響第一主動區域110 内的所有元件（element)。 進行上述蝕刻製程之後，係依序進行移除圖案化光阻322 與第一閘極溝渠160内的圖案化光阻層302、形成第二金屬 層220與第三金屬層230、以及平坦化製程，而完成第一導 電型金屬閘極Π0與第二導電型金屬閘極172之製作。由於 上述步驟亦與第一較佳實施例相同，因此該等步驟及相同之 元件係可參閱第一較佳實施例所揭露以及第7圖至第8圖所 繪示者，而不再贅述。 本第二較佳實施例與第一較佳實施例之差異係在於利用 阻障層200與第一金屬層210之蝕刻率差異，可於形成圖案 化光阻層302後直接進行蝕刻製程，而於第一閘極溝渠160 16 201135927 内形成所欲獲得的U型金屬層212,故可更省去形成光阻與 微影製程等步驟之實施’更收節省成本之效。 此外’雖然第一較佳實施例與第二較佳實施例中閘極導 電層106係同時移除，但熟習該項技藝之人士應知本發明所 提供之方法亦不限於先後移除第一導電型電晶體12〇或第二 導電型電晶體122之閘極導電層1〇6。 綜上所述，根據本發明所提供之具有金屬閘極之半導體 元件之製作方法’各導電型電晶體皆是利用後閘極方法製作 而成，故此時需要較高熱預算的製程皆已完成。且由於卩型 金屬層之設置，除可提供所需的功函數金屬外，更可使後續 填入閘極溝渠内的填充金屬層享有較佳的填補結果，確保半 導體元件的可靠度。 # 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第8圖為本發明所提供之具有金屬閘極之半導 體兀件之製作方法之-第—較佳實施例之示意圖。 第9圖至第10圖為本發明所提供之具有金屬閘極之半導 201135927 體元件之製作方法之一第二較佳實施例之示意圖。 【主要元件符號說明】 100 半導體基底 102 淺溝絕緣 104 閘極介電層 106 閘極導電層 108 圖案化硬遮罩 110 第一主動區域 112 第二主動區域 120 第一導電型電晶體 122 第二導電型電晶體 130 第一輕摻雜汲極 132 第二輕摻雜汲極 134 側壁子 140 第一源極/汲極 142 第二源極/汲極 144 金屬石夕化物 150 接觸洞餘刻停止層 152 内層介電層 160 第一閘極溝渠 162 第二閘極溝渠 170 第一導電型金屬閘極 172 第二導電型金屬閘極 200 阻障層 210 第一金屬層 212 U型金屬層 220 第二金屬層 230 第三金屬層 300 302 ' 光阻 312 ' 322 > 332 圖案化光阻201135927 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device having a metal gate and a method of fabricating the same, and more particularly to a metal having a gate last process Gate semiconductor device and method of fabricating the same. [Prior Art] In the conventional semiconductor industry, polycrystalline germanium is widely used in semiconductor elements such as metal-oxide-semiconductor (MOS) transistors as a standard gate material. However, as the size of the MOS transistor continues to shrink, the conventional polycrystalline slab gate causes a decrease in component efficiency due to a boron penetration effect, and an unavoidable depletion effect, etc., making the equivalent The thickness of the gate dielectric layer increases, and the value of the gate capacitance decreases, which leads to the dilemma of the component driving capability. Therefore, the semiconductor industry has adopted a new gate material, such as the use of work function metal to replace the traditional polysilicon gate for control of high dielectric constant (High-K) gate dielectric layer. electrode. In a complementary metal-oxide semiconductor (CMOS) device, the dual-function metal gate must be paired with the 201135927 NMOS device, and the other must be paired with the pM〇s device, thus enabling the integration of the related components and Process control is more complex, and the thickness of each material and the control requirements are more stringent. The manufacturing method of the double work function metal gate can be roughly divided into two categories: a gate first process and a gate last process. Among them, the front gate process will start the metal/gate bungee ultra-shallow junction activation and tempering and form a high-heat budget process such as metal lithium, which makes the selection and adjustment of materials face more challenges. . In order to avoid the above-mentioned high-heat pre-calculation environment and obtain a wider material selection, the industry has proposed a method of replacing the front gate process by the gate process. In the latter post gate process, a dummy gate or a replacement gate is formed first, and after the fabrication of the general M〇s transistor is completed, the dummy gate is replaced/replaced. Removed to form a gate trench, and then filled with different metals in the gate recess according to electrical requirements. It can be seen that although the post-gate process can avoid the high-heat budget process of source/drain ultra-shallow junction activation and tempering, and it has a wide material selection, it still faces the integration of complex processes. Reliability and reliability requirements such as gate groove filling ability. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor device having a metal gate for performing a gate process. 201135927 According to the application of the present invention, there is provided a semiconductor device having a metal gate, the semiconductor device comprising a semiconductor substrate, a gate dielectric layer formed on the semiconductor substrate, and At least - a first conductive metal gate formed on the gate dielectric layer. The first conductive metal gate further comprises a -fill metal layer, and a (four) metal layer disposed between the gate layer and the true metal fill layer, and the southernmost portion of the one of the u-type metal layers is low The metal layer is filled. In accordance with the present invention, a semiconductor material-like green is produced which is all gate-type. First, a substrate is provided, and a surface of the substrate is formed with a -first conductivity type transistor, a second conductivity type transistor, and a dielectric layer surrounding the first conductivity type transistor and the second conductivity type transistor . Subsequently, the first conductive type transistor and the gate conductive layer of the second conductive type transistor are removed, and the first gate is formed in the first conductive type transistor and the second conductive type transistor respectively Gate treneh and - second gate ditch. Forming a barrier layer in the first gate trench and the second gate trench; forming a -U-shaped metal layer in the first gate trench, and the U-metal layer is lower than the first- Gate ditches. Finally, a second metal layer is formed in the first interpole trench and the second gate trench. According to the method for fabricating a semiconductor device having a metal gate provided by the present invention, each of the conductive 33 transistors is fabricated by a post-gate method, so that a process requiring a higher thermal budget at 201135927 has been completed. Moreover, since the U-type metal layer is provided to provide the desired work function metal, the filling metal layer which is subsequently filled into the gate trench can better fill the result and ensure the reliability of the semiconductor component. [Embodiment] Please refer to Figs. 1 to 8 and Fig. 1 to Fig. 8 are schematic views showing a first preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. As shown in FIG. 1, first, a semiconductor substrate 100 such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate is provided. The surface of the semiconductor substrate 100 defines a first active region 110 and A second active region 112 is formed, and a plurality of shallow trench isolation (STI) 102 for electrically isolating the first active region 110 and the second active region 112 are formed in the semiconductor substrate 100. Next, a first conductive type transistor 120 and a second conductive type transistor 122 are respectively formed on the semiconductor substrate 100 in the first active region 110 and the second active region 112. In the preferred embodiment, the first conductive type transistor 120 is a P-type transistor; and the second conductive type transistor 122 is an N-type transistor, but those skilled in the art should know the opposite. can. As shown in FIG. 1, the first conductive type transistor 120 and the second conductive type transistor 122 each include a gate dielectric layer 104, a gate conductive layer 106 such as a 201135927 polycrystalline layer, and a patterning The hard mask 1 〇 8; wherein the gate conductive layer 1 () 6 acts as a dummy gate or replaces the gate. In the preferred embodiment, the gate dielectric layer 104 can be a conventional germanium dioxide layer or a high-k gate dielectric layer, and the high_K gate dielectric The layer is selected from the group consisting of cerium nitride (SiN), cerium oxynitride (Si〇N) and metal oxides, wherein the metal oxide comprises hafniuin oxide (HfO) and oxygenated oxygen. Compound (hafnium silicon oxide, HfSiO), hafnium silicon oxynitride (HfSiON), oxidation! Aluminum oxide (A10), lanthanum oxide (LaO), lanthanum aluminum oxide 'LaAlO', tantalum oxide (TaO), zirconium oxide 'ZrO', ashixi acid Oxygen compound (zirconjum siiic〇n 〇xjde, ZrSiO), or hafnium zirconium oxide (HfZrO). Please continue to see Figure 1. The first conductive type transistor 12A and the second conductive type transistor 122 respectively include a first light doped drain (LDD) 130 and a second LDD 132, a sidewall 134, and a first Source/drain 140 and a second source/drain 142. The sidewall 134 may be a composite film layer structure, which may include a south temperature oxidized smectite layer, SiN, SiO or tantalum nitride formed using hexachlorodisilane (Si2Cl6). HCD-SiN). In addition, in the preferred embodiment, the first source/drain 140 and the second source/drain 142 may also be fabricated by a selective epitaxial growth (SEG) method, for example, when A conductive type transistor 120 is a P-type electromorphic 201135927 body, and when the second conductive type transistor 122 is an N-type transistor, an epitaxial layer containing a germanium telluride (SiGe) and containing tantalum carbide can be utilized ( The first source/drain 140 and the second source/drain 142 are respectively fabricated by using the epitaxial-layer layer to improve the electrical performance by utilizing the stress between the epitaxial layer and the gate channel. The first source/dipole 140 and the second source/drain 142 surface system respectively comprise a metal lithium 144. After the first conductive type transistor 12 〇 and the second conductive type transistor 122 are formed, A contact etch stop layer (CESL) 150 and an inter-layer dielectric (ILD) layer 152 are sequentially formed on the semiconductor substrate 1 。. Please refer to FIG. Next, a planarization process, such as a CMP process, is used to planarize the ILD layer 152. The CESL 150 removes the patterned hard mask 108 until the gate conductive layer 106 is exposed. After the planarization process, the first conductive type transistor 120 and the second conductive type transistor 122 are removed by an etching process. The gate conductive layer 106 forms a first gate trench 160 and a second gate trench 162 in the first conductive transistor 120 and the second conductive transistor 122. The openings of the first gate trench 160 and the second gate trench 162 are coplanar with the surface of the ILD layer 152. In the preferred embodiment, the gate dielectric layer 104 is exposed to the first gate trench 160, respectively. The bottom of the second gate trench 162, but those skilled in the art should understand that the method provided by the first preferred embodiment is not limited to the removal of the gate conductive layer 106, but also by an etching process. In addition to the gate dielectric layer 201135927 104. Thereafter, a high-K gate dielectric layer is formed at the bottom of the first gate trench ι6〇 and the second gate trench ία to replace the conventional ruthenium dioxide layer or The yttria layer acts as a gate dielectric layer, effectively reducing the low physical limit In the same EOT, the leakage current is effectively reduced and the equivalent capacitance is reached to control the channel switch. Please refer to Figure 3. Next, sequentially in the first gate trench 160 and the second gate trench 162. Forming a barrier layer 200 and a first metal layer 210. The first metal layer 210 may be a metal that satisfies the required work function of the P-type transistor, such as titanium nitride (TiN) or Tantalum carbide (TaC). However, it is worth noting that since the first conductive type transistor 120 is a P-type transistor and the metal gate has a work function of between 4.8 eV and 5.2 eV, the first embodiment provides A metal layer 210 is also not limited to any suitable metal material. The barrier layer 200 is a film layer having a different rate than the first metal layer 210, such as tantalum nitride (TaN). After the formation of the above film layer, a sacrificial layer having a good hole filling ability, such as a bottom anti-reflective coating (BARC layer) or a spin-on glass, is formed on the semiconductor substrate 1〇0. , SOG), or photoresist 300, and the photoresist 300 fills the first gate trench 160 and the second gate trench 162 as shown in FIG. Please refer to Figure 4. Next, the sacrificial layer of the photoresist 3 〇〇 is etched back to form a patterned photoresist 302. The etched patterned photoresist 302 does not fill the 201135527 full first gate trench 160 and the second gate trench 162, but must be completely covered and protected by the first and second gate trenches 16 and 162. The bottom; that is, the 4' dimension does not exceed the opening of the first gate trench 16〇 and the second gate trench 162. It should be noted that the patterned photoresist 302 provided in the preferred embodiment is as shown in FIG. 4 to define the position and height of a U-shaped metal layer to be obtained. φ is referred to Figure 5. After forming the patterned photoresist 302, another photoresist (not shown) is formed on the semiconductor substrate 100, and the photoresist is patterned by a lithography process, and formed in the second active region 112. Figure 5 shows the patterned photoresist 312. In other words, the patterned photoresist 312 is formed on the second conductive type transistor 122 and exposes the first gate trench 160 in the first active region 11''. In addition, those skilled in the art should know that before forming the patterned photoresist 312, a patterned bake step can be performed on the patterned photoresist 3 〇 2; or even two photoresist materials having different correlation rates can be used. The patterned photoresist 302 and the patterned photoresist 312 are respectively formed, so that the lithography process for forming the patterned photoresist 312 does not affect the patterned photoresist 3〇2. Continue to see Figure 5. Subsequently, an etching process is performed to remove the first active region 110, that is, a portion of the first metal layer 21A on the first conductive type transistor 12G. It should be noted that the first metal 0 layer 210 in the inner portion of the first gate trench 16 is protected by the patterned photoresist 302, so that after the process is completed, a U is formed in the first gate trench 160. Type metal layer 212. And, as shown in Fig. 201135927, the highest portion of any of the U-shaped metal layers 212 is lower than the opening of the first gate trench 160. In addition, since the surface of the ILD layer 152 is coplanar with the openings of the first and second gate trenches 160 and 162, the highest U-shaped portion of the lip-shaped metal layer 212 can also be considered to be lower than the ILD layer 152. Please refer to Figure 6. Next, after sequentially removing the patterned photoresist 312 and the patterned photoresists 302 in the first-gate trenches 160 and the second gate trenches 162, the first active regions 11 are connected to the first conductive region. A patterned photoresist 322 is further formed on the transistor 120. As shown in FIG. 6, the patterned photoresist 322 exposes the second active region 112. Subsequently, the first active region 112 is privately removed, and in detail, the first metal layer 21 on the second conductive type electric body body 122 and the second gate trench 162 is removed. It is also worth noting that the gate dielectric layer 104 at the bottom of the second gate trench 162 is exposed by the barrier layer 2 in the silver engraving process of removing the first metal layer 210 due to the thinness of the barrier layer. Protection without being damaged. Please refer to Figure 7. Next, the patterned photoresist 322 is removed, and then a second metal 122 and a third metal layer 230' are sequentially formed on the semiconductor substrate 1 and the third metal layer 23 is filled with the first interlayer. Ditch (10) and second gate ditch 162. In addition, the barrier layer may be removed prior to forming the first metal layer 22 and the third metal layer 230, depending on product characteristics and process requirements. Please refer to Figure 8. After the second metal layer 22 and a third metal layer 12 201135927 230 are formed to fill the first pole trench 16G and the second gate trench 162, the second planarization process can be performed to remove the excess The third metal layer 23, the second metal layer 22, and the barrier layer are thin to obtain an approximately flat surface, and the fabrication of the first conductive type metal gate 17G and the second conductive type metal gate is completed. After the planarization process, the surface of the plurality (four) 152 is coplanar with the top surface of the first conductive type metal gate 170 and the second conductive type metal open electrode 172. The above flattening process is known to those skilled in the art and will not be described again. Please still refer to Figure 8. As previously mentioned, the preferred embodiment is a - Ν type transistor. Therefore, in the first conductivity type metal interrogation port 72, the (four) metal layer 212 is used to adjust the work function such that the first conductivity type metal gate has a force function between 4.8 eV (eV) #52 eV. Since the lip-type gold layer 212 is used to satisfy the work function of the first-conductivity-type metal gate 17〇, the second metal layer 22 is formed as a layer. A composite type of filled metal layer. It is worth noting that the shape characteristic of the metal layer 212 'the first half opening of the first open drain ditch can maintain the original size' and effectively reduce the aspect ratio of the first interpole trench 160, so the second metal layer The third gold=30 can be filled in smoothly, so as to avoid filling the gap between the first pole trench (fine) and ensuring the reliable production of the first conductive metal gate 17〇 13 201135927 In addition, due to covering the first gate trench The portion of the U-shaped metal layer 212 at the bottom of the 160 has a greater influence on the work function than the portion of the U-shaped metal layer 212 covering the sidewall of the first gate trench 160. Therefore, the patterned photoresist 302 can be selected from the first rate and the first Metal layer 210 is approximately the same photoresist material, or even other suitable sacrificial materials. Accordingly, the patterned photoresist 302 and a portion of the first metal layer 210 covering the sidewalls of the first gate trench 160 may be consumed in the etching process and may not damage the first metal layer covering the bottom of the first gate trench 160. 210 is an etching process control consideration, which reduces the difference between the highest point and the lowest point of the U-shaped metal layer 212. Thus, a flatter U-shaped metal layer 212 can be obtained, so that the subsequently formed second metal layer 220 and third metal layer 230 are formed. It is easier to fill the first gate trench 160. Please continue to see Figure 8. The second metal layer 220 is selected from the group consisting of titanium aluminide (TiAl), aluminum amalgamation (ZrAl), tungsten aluminide (WA1), aluminum aluminide (TaAl), or hafnium aluminide (HfAl). The third metal layer 230 is selected from the group consisting of aluminum (Ai), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), Titanium carbide (TiC), nitride button (TaN), titanium tungsten (Ti/W) ' or a combination of titanium and titanium nitride (Ti/TiN), and the third metal layer 230 It is a composite metal layer. Therefore, in the second conductive type metal gate 110, the second metal layer 220 is used to adjust the work function ', so that the work function of the second conductive type metal gate 172 is between 3·9 eV and 4.3 eV. Since the second metal layer 220 is used to satisfy the work function requirement of the second conductivity type metal gate Π2, the third metal layer 230 201135927 is used as the filling metal layer for the second conductive metal gate 172. Next, please refer to FIG. 9 to FIG. 10, which are schematic diagrams showing a first preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. In the second preferred embodiment, the first conductive type transistor 120 and the second conductive type transistor 122 are formed, the first gate trench 160 and the second gate trench 162 are formed, and the barrier layer 2 and the barrier layer are formed. The steps of forming a φ metal layer 210 and forming the patterned photoresist 3 〇 2 are the same as those of the first preferred embodiment. Therefore, the steps and the same components can be referred to the above disclosure and FIGS. 1 to 4 . The person depicted is not described again. 4 See Figures 4 and 9. After the patterned photoresist 3 〇 2 is formed in the first gate trench 16 〇 and the second gate trench 162 , an etching process is directly performed to remove the first gate trench! 6 〇 and the second gate trench 2 form the first metal layer 210 covered by the photoresist layer 302, and in the first 160 and the second gate trench 162, a germanium metal as shown in FIG. 9 is formed. Layer 212. Due to the difference in etching rate between the barrier layer 200 and the first metal layer 21, the etching process can be accurately stopped at the barrier layer 2, without damaging the layer 152 and the first gate trench 16 And the second gate trench; the side wall. Please refer to Figure 10. Next, a patterned photoresist layer 332 is formed on the first active region 11 (i.e., the first conductive type transistor 120). As shown in FIG. 15 201135927, the patterned photoresist layer 332 exposes the second active region 112. An etch process is then performed to remove the U-shaped metal layer 212 in the second active region 112, particularly in the second gate trench 162. As described above, due to the existence of the barrier layer 200, in the etching process for removing the U-shaped metal layer 212, the gate dielectric layer 104 at the bottom of the second gate trench 162 is protected by the barrier layer 200. Not to be harmed. Similarly, the photoresist material 302 and the patterned photoresist 332 may be respectively formed by using two photoresist materials having different etching rates, or the thickness ratio of the patterned photoresist 332 and the patterned photoresist 302 may be controlled to make the etching second. The active region 112, particularly the patterned photoresist 302 and the U-shaped metal layer 212 in the second gate trench 162, does not affect all of the elements within the first active region 110. After performing the etching process, the patterned photoresist 322 and the patterned photoresist layer 302 in the first gate trench 160, the second metal layer 220 and the third metal layer 230, and the planarization process are sequentially performed. The fabrication of the first conductive type metal gate Π0 and the second conductive type metal gate 172 is completed. The above steps are also the same as those of the first preferred embodiment. Therefore, the steps and the same components can be referred to the first preferred embodiment and the seventh to eighth embodiments, and will not be described again. The difference between the second preferred embodiment and the first preferred embodiment is that the etching rate difference between the barrier layer 200 and the first metal layer 210 can be directly performed after the patterned photoresist layer 302 is formed. The U-shaped metal layer 212 is formed in the first gate trench 160 16 201135927, so that the implementation of the steps of forming the photoresist and the lithography process can be omitted. In addition, although the first preferred embodiment and the second preferred embodiment of the gate conductive layer 106 are simultaneously removed, those skilled in the art will appreciate that the method provided by the present invention is not limited to the first removal. The conductive transistor 12A or the gate conductive layer 1〇6 of the second conductivity type transistor 122. In summary, the method for fabricating a semiconductor device having a metal gate according to the present invention's each of the conductive type transistors is fabricated by a post-gate method, and thus a process requiring a higher thermal budget has been completed. Moreover, due to the arrangement of the bismuth metal layer, in addition to providing the required work function metal, the filling metal layer which is subsequently filled into the gate trench can enjoy better filling results and ensure the reliability of the semiconductor component. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the patent range of the present invention should be covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 8 are schematic views of a preferred embodiment of a method for fabricating a semiconductor gate having a metal gate according to the present invention. 9 to 10 are schematic views showing a second preferred embodiment of a method for fabricating a semiconductor element having a metal gate of the present invention. [Main component symbol description] 100 semiconductor substrate 102 shallow trench insulation 104 gate dielectric layer 106 gate conductive layer 108 patterned hard mask 110 first active region 112 second active region 120 first conductive type transistor 122 second Conductive transistor 130 first lightly doped drain 132 second lightly doped drain 134 sidewall spacer 140 first source/drain 142 second source/drain 144 metal lithium 150 contact hole residual stop Layer 152 inner dielectric layer 160 first gate trench 162 second gate trench 170 first conductive metal gate 172 second conductive metal gate 200 barrier layer 210 first metal layer 212 U-shaped metal layer 220 Two metal layer 230 third metal layer 300 302 'resistance 312 ' 322 > 332 patterned photoresist