201010008 九、發明說明： 【發明所屬之技術領域】 本發明是關於一種製 有金屬閘極之電方法4^法，尤指-種製作具 【先前技術】 在半導體產業中，由 曰 ❹ 〇 在製作典型金屬氧化物半夕#料具有抗熱性質，因此 多晶石夕材料來製作 體(Mos)電晶體時通常會使用 阻 圖 域得以在高溫下的間極電極，使其源極與沒極區 檔以離子佈植所摻雜之I退火。其次，由於多晶石夕能夠 案化之後能料地:、子進人通道區域，因此在閘極 ^成自行對準的源極與汲極區域。 然而，多晶矽閘極仍 材料相比，多晶石夕間極是以：雷點。首先，與大多數金屬 成。這造❹阻㈣半導體材料所形 ::s為了彌補南電阻與其相應之較低操作速率，”石夕 材料通常需要大量靼昂主从 郷腳迷+多阳矽 可提升至可接受的範圍糊處理，使其操作迷率 «二人夕日日石夕間極容易產生空乏效應（depletion effect)。 =說’目前多晶石夕的摻雜濃度只能達到約2x2〇2〇/cm3 到約 3xl〇2〇/cm3 & 々 、乾圍。在閘極材料中的摻雜濃度需要至 7 201010008 少達到5X102W的條件下，由於換雜濃度上的限制，因 此當多晶石夕閑極受到偏壓時，便會發生缺乏載子的現象， 使得靠近多晶㈣極與閘極介電層的介面上就容易產生空 乏區。而此空乏效應除了會使等效的間極介電層厚度增 又同時造賴極電容值下降，進而導致元件驅動能力 哀退等困境。 〇 故目前便有新的閘極材料被研製生產，例如利用具特定 功函數(work function)之金屬閘極來取代傳統的多晶矽閘 極。然而，製做金屬閘極時，一方面需要與NM〇s元件搭 配，另一方面則又需與PMOS元件相匹配，因此使得相關 元件的整合技術以及製程控制更形複雜，且各材料的厚度 與成分控制要求亦更形嚴苛。在這個嚴苛的製程環境下， 如何在製作金屬閘極時又能同時達到降低成本與完成具有 競爭力產品的作法即為現今一重要課題。 ❹ 【發明内容】 本發明之主要目的是提供一種製作具有金屬閘極之電 晶體的方法。 根據本發明之較佳實施例，本發明方法主要是先提供一 基底，且基底上定義有一第一電晶體區與一第二電晶體 區。然後形成一虛置閘極於第一電晶體區與第二電晶體區 8 201010008 的基底上，於各虛置閘極兩側形成一源極/汲極區域，並形 成一介電層並覆蓋虛置閘極。接著去除虛置閘極，以分別 於第一電晶體區與第二電晶體區之介電層中形成一開口。 隨後形成一高介電常數介電層並覆蓋介電層及各開口表 面，再覆蓋一第一遮蓋層於高介電常數介電層上。然後去 除第二電晶體區的第一遮蓋層，並形成一金屬層於第一電 晶體區的第一遮蓋層與第二電晶體區的高介電常數介電層 @ 表面。最後再形成一導電層並填滿第一電晶體區與第二電 晶體區的開口。 本發明另一實施例是揭露一種具有金屬閘極之電晶 體，包含有一基底、一金屬閘極設於基底上以及一源極/汲 極區域設於金屬閘極兩侧的基底中。其中金屬閘極另包含 有一 U型高介電常數介電層，一 U型遮蓋層設於U型高介 電常數介電層表面，以及一 U型金屬層設於該U型遮蓋層 ©上。 【實施方式】 請參照第1圖至第8圖，第1圖至第8圖為本發明較佳 實施例製作一具有金屬閘極之電晶體示意圖。如第1圖所 示，首先提供一基底12，例如一梦基底或一絕緣層上覆石夕 (silicon-on-insulator; SOI)基底等。然後在基底12中定義 至少一 NMOS電晶體區14以及一 PMOS電晶體區16，並 201010008 形成複數個隔離兩個電晶體區 構18。 14、16的淺溝隔離(STi)結 ❹201010008 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an electrical method for manufacturing a metal gate, in particular, a method for producing a device. [Prior Art] In the semiconductor industry, The production of a typical metal oxide is a heat-resistant property. Therefore, when a polycrystalline stone material is used to fabricate a body (Mos) transistor, a resistive field is usually used to make the electrode at a high temperature, so that the source is not The polar zone is annealed with I doped by ion implantation. Secondly, since the polycrystalline stone can be materialized afterwards, the sub-into the channel area, so the gate is self-aligned source and bungee regions. However, the polycrystalline germanium gate is still compared to the material, and the polycrystalline litter is at the same time: the lightning point. First, with most metals. This ❹ ❹ 四 (4) semiconductor material shape:: s in order to make up for the south resistance and its corresponding lower operating rate, "Shi Xi material usually requires a large number of 主 主 主 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Processing, making it operate at a rate of «There is a depletion effect in the evening of the two days.] =The current doping concentration of polycrystalline stone can only reach about 2x2〇2〇/cm3 to about 3xl. 〇2〇/cm3 & 々, dry circumference. The doping concentration in the gate material needs to be 7 201010008 and less than 5X102W, due to the limitation of the impurity concentration, when the polycrystalline stone is extremely biased When pressed, a lack of carriers occurs, which makes it easy to create a depletion zone near the interface between the poly(4-) and the gate dielectric layer. This depletion effect increases the thickness of the equivalent inter-electrode layer. At the same time, the value of the capacitor is decreased, which leads to the dilemma of the component drive capability. Therefore, new gate materials have been developed and produced, for example, by using metal gates with specific work functions instead of the conventional ones. Polycrystalline gate However, when manufacturing a metal gate, on the one hand, it needs to be matched with NM〇s components, and on the other hand, it needs to be matched with the PMOS components, thus making the integration technology and process control of the related components more complicated, and the thickness of each material. The composition control requirements are also more stringent. In this demanding process environment, how to reduce the cost and complete competitive products in the production of metal gates is an important issue today. The main object of the present invention is to provide a method for fabricating a transistor having a metal gate. According to a preferred embodiment of the present invention, the method of the present invention mainly provides a substrate, and a first transistor region is defined on the substrate. And a second transistor region, and then a dummy gate is formed on the substrate of the first transistor region and the second transistor region 8 201010008, and a source/drain region is formed on each side of each dummy gate. And forming a dielectric layer and covering the dummy gate. Then removing the dummy gate to form an opening in the dielectric layer of the first transistor region and the second transistor region, respectively. Forming a high-k dielectric layer and covering the dielectric layer and the surface of each opening, and then covering a first capping layer on the high-k dielectric layer, and then removing the first capping layer of the second transistor region, Forming a metal layer on the first cap layer of the first transistor region and the high-k dielectric layer @ surface of the second transistor region. Finally, forming a conductive layer and filling the first transistor region and the second layer An opening of a transistor region. Another embodiment of the invention discloses a transistor having a metal gate, comprising a substrate, a metal gate disposed on the substrate, and a source/drain region disposed on both sides of the metal gate The metal gate further includes a U-type high-k dielectric layer, a U-shaped mask layer is disposed on the surface of the U-type high-k dielectric layer, and a U-shaped metal layer is disposed on the U-type Cover layer ©. [Embodiment] Please refer to Figs. 1 to 8. Figs. 1 to 8 are schematic views showing a transistor having a metal gate according to a preferred embodiment of the present invention. As shown in Fig. 1, a substrate 12 is first provided, such as a dream substrate or a silicon-on-insulator (SOI) substrate. At least one NMOS transistor region 14 and a PMOS transistor region 16 are then defined in the substrate 12, and 201010008 forms a plurality of isolated two transistor regions 18. Shallow trench isolation (STi) junctions of 14, 16
然後形成-由氧化物、氮化物等之介電材料所構 極絕緣層2G在基底丨2表面，閘極絕緣層2()也可以是由閉 氧化層與具有高介電常數之介電材料層所構成，高=電， 數之介電材料例如是㈣給氧化合物(HfSi〇)、錢給氮= 化合物（HfSiON)、氧化給（Hfo)、氧化鋼（La〇)、紹酸綱 (LaAlO)、氧化錯(Zr〇)、矽酸錯氧化合物(ZrSi〇)或錯酸給 (HfZrO)等材料。在閘極絕緣層2()上依序形成—厚度約 1 〇〇〇埃(angstrom)的虛置閘極(du_y科⑹層，例如多2矽 層22,在閘極絕緣層20上以及一遮罩層24在多晶矽層22 上。在本較佳實施例中，遮罩層24可由二氧化矽（Si〇2)、 氮化矽或氮氧化矽(SiON)等材料所構成’而多晶矽層22可 由不具有任何摻質(undoped)的多晶矽材料或由具有N+摻 質的多晶矽材料所構成，此皆屬本發明所涵蓋的範圍。 接著如第2圖所示，形成一圖案化光阻層（圖未示）在多 晶矽層22上，並利用圖案化光阻層當作遮罩進行一圖案轉 移製程，以單次蝕刻或逐次蝕刻步驟，去除部分的遮罩層 24、多晶矽層22及閘極絕緣層20，並剝除此圖案化光阻 層，以於NMOS電晶體區14以及pM〇s電晶體16區各形 成一虛置閘極，例如本實施例中之多晶石夕閑極26。 201010008 如第3圖所示，然後在NMOS電晶體區14&pM〇s電 晶體區16各進行一淺摻雜製程，以形成所需的輕推雜沒 極。舉例來說，本發明可先覆蓋一圖案化光阻層（圖未示) 在丽OS電晶體區14以外的區域，然後利用該圖案化光 阻層當作遮罩進行-離子佈植，將N型推質植入聰仍電 晶體區14之多晶矽閘極26兩側的基底12中，以於NM〇s 電晶體區14形成-輕摻雜没極28。接著去除上述的圖案 〇化光阻層’再覆蓋另一圖案化光阻層在PMOS電晶體區16 以外的區域’並利用該圖案化光阻層當作遮罩進行另一離 子佈植，將P型摻質植入P M 〇 s電晶體區i 6之多晶石夕閑極 26兩侧的基底12中’以於PM〇s電晶體區16形成一輕摻 雜汲極30» / 隨後進行第^段的側壁子製程，例如純化多晶石夕問 極26的侧壁表面形成一氧化石夕層32，接著再以沈積、回 ❹餘刻的方式形成-例如是氮化石夕層所構成的側壁子％在 丽osf晶舰14#PM0S電晶體區16之多晶石夕問極％ 的周圍側壁。 如第4圖所不’先在覆蓋一由氮化矽所構成的保護層36 於側壁子34表面，然後進行一選擇性磊晶成長（selective ,epitaxial growth，SEG)製程，以於 NM〇s 電晶體區 14 或 PMOS電晶體區16的基底12中形成應變矽（strained 。 201010008 例如可先於PMOS電晶體區16之多晶矽閘極26兩側的基 底12中形成二凹槽，再利用選擇性磊晶成長製程實質上 (substantially)填滿這兩個凹槽而形成矽鍺層38。此矽鍺層 38可對PMOS電晶體區16的通道區域施加一壓縮應力 (compressive strain)’進而提升pm〇S電晶體的電洞遷移 率。 _ 接著進行第二階段的側壁子製程，例如可在NMOS電晶 體區14與PMOS電晶體區16的保護層36侧壁再形成一由 氧化矽所形成的侧壁子40。 隨後在NMOS電晶體區14進行一重摻雜離子佈植製 程’以形成所需的源極/’;及極區域。如同上述形成輕摻雜汲 極的作法，本發明可先覆蓋一圖案化光阻層（圖未示）在 NMOS電晶體區14以外的區域，然後利用該圖案化光阻層 © 當作遮罩進行一離子佈植製程，將N型摻質植入側壁子4〇 兩侧的基底12中，以於NMOS電晶體區14形成一源極/ 沒極區域42,接著去除上述的圖案化光阻層。而PM〇s電 晶體區16的源極/汲極44亦可用與NMOS電晶體區14相 同方式來進行一重摻雜離子佈植製程形成，較佳是於選擇 性蟲晶成長以同位摻雜（in-situ dope)所同時形成的，最佳是 如第4圖所示’選擇性蟲晶成長最初先不摻雜之後才推雜 的分階段同位摻雜方式形成源極/汲極44。 12 201010008 然後於形成源極/汲極區域42、44後，進行一個自行對 準矽化金屬（self-aligned siUcide，Salicide)製程。例如先形 成一由鈷、鈦、鎳、鉑、鈀或鉬等所構成的金屬層（圖未示） 在基底12表面覆蓋側壁子4〇，並搭配一快速升溫退火製 程，利用高溫使金屬層在側壁子4〇兩側的基底12表面反 應為一矽化金屬層46。最後再去除未反應的金屬層。 ◎ 接著形成一氮化矽層48在各多晶矽閘極26、各側壁子 40與基底12表面。在本較佳實施例中，氮化矽層48的厚 度約為100埃，其主要做為後續進行平坦化時之一蝕刻停 止層。然後形成一由氧化物所構成的層間介電層（interlayer dielectdC)50並覆蓋NMOS電晶體區14與PM0S電晶體區 16的氮化矽層48。 如第5圖所示，進行一化學機械研磨（chemical ❹ mechanical polishing，CMP)製程或一乾蝕刻製程，去除部分 的層間介電層50、氮化矽層48及遮罩層24直至多晶發閑 極26表面’並使多晶梦閘極26的頂部約略切齊於層間介 電層50表面。 如第6圖所示’進行一選擇性蝕刻製程，例如利用氨水 (ammonium hydroxide，NH4〇H)或氫氧化四甲錢 (Tetramethylammonium Hydroxide, TMAH)等姓刻溶液來去 13 201010008 除NMOS電晶體區14及pM〇s電晶體區16中的多晶石夕問 極26但不餘刻層間介電層5〇。在本實施例中此姓刻製 程會去除各電晶體區14、16的多晶矽閘極26以形成一開 口 52，並同時暴露出下方的閘極絕緣層20。 畠閘極絕緣層20是一般介電材料層時，需再去除閘極 絕緣層20而暴露出下方的基底12。然後依序沈積一襯氧 ❹ 化層68、一高介電常數介電層54以及一遮蓋層56knm〇S 電晶體區14以及PMOS電晶體區16的層間介電層5〇與開 口 52侧壁及底部。在本實施例中，高介電常數介電層54 可由梦酸铪氧化合物（HfSiO)、石夕酸铪氮氧化合物 (HfSiON)、氧化铪(HfO)、氧化鑭(LaO)、鋁酸鑭(LaA丨〇)、 氧化錯(ZrO)、石夕酸錄氧化合物(ZrSiO)或錯酸給(jjfZrO)等 材料所構成，而遮蓋層56則是由氧化鋼(LaO)、氧化鎮 (MgO)、氧化鏑(Dy203)或其他鑭系氧化物所構成。 〇 然而當閘極絕緣層20是高介電常數之介電材料時，則 直接進行沈積遮蓋層56於NMOS電晶體區14以及pm〇s 電晶體區16的層間介電層50與開口 52侧壁及底部。 接著形成一圖案化光阻層58覆蓋NMOS電晶體區14， 並利用圖案化光阻層58當做遮罩來進行一蝕刻製程，以去 除PMOS電晶體區16内的遮蓋層56。 201010008 如第7圖所示，在去除圖案化光阻層58之後，先沈積 一金屬層60在NMOS電晶體區14的遮蓋層56上以及 PMOS電晶體區16的高介電常數介電層54上。在本實施 例中’金屬層60可由氮化鈦(TiN)、碳化鈕(TaC)、氮化鈕 (TaN)、1化石夕鈕(TaSiN)、紹、或氮化紹鈦(TiA1N)等材料 所構成。 值得注意的是’本發明主要是藉由金屬層6〇下的遮蓋 層56來定義調整金屬層60的功函數(work functi〇n)，便可 對NMOS電晶體與PMOS電晶體的需求，而分別形成功函 數的費米能階(Fermi level)接近N型矽(N_type Si)與p型矽 (P-typeSi)的準費米能階（Quasi Fermi level)的金屬，使 CMOS電晶體可達到更佳的效能。以上述在NM〇s電晶體 區14所覆蓋的遮蓋層56為例，本發明是在金屬層6〇形成 前先覆蓋一層由氧化鑭所構成的遮蓋層56在金屬層6〇下 方，然後藉由此遮蓋層50定義出N型金屬的功函數。 但不侷限於此作法，本發明亦可同時在pM〇s電晶體區 16也覆蓋一遮蓋層（圖未示）在高介電常數介電層54及金屬 層60之間，並藉由此遮蓋層來定義p型金屬的功函數。舉 例來說，本發明可在去除完PMOS電晶體區16的遮蓋層 56後’先形成另一由氧化鋁(a12〇3)、氮化鋁(ΑΐΝ〇或氧氮 化銘(ΑΙΟΝ)等材料所構成的遮蓋層在pM〇s電晶體區w 15 201010008 的高介電常數介電層54上，然後再全面覆蓋金屬層60， 此都屬本發明所涵蓋的範圍。 隨後如第8圖所示’當開口 52仍未填滿時，可選擇性 地填入一低電阻材料所構成的導電層62在NMOS電晶體 區14與PMOS電晶體區16的金屬層60上並填滿開口 52。 在本實施例中，導電層62可由鋁、鎢、鈦鋁合金(TiAl)或 ❿鈷鎢磷化物（cobalt tungsten phosphide，CoWP)等低電阻材 料所構成。最後再進行另一化學機械研磨製程，去除部分 的導電層62及金屬層60’以於NMOS電晶體區14及PMOS 電晶體區16分別形成一具有金屬閘極64、66的電晶體。 再如第8圖所示，本發明依據上述製程另揭露一種具有 金屬閘極64、66的CMOS電晶體結構，其主要包含有一 基底12、兩個金屬閘極64、66分別設置於基底12上的 ❹ NM0S電晶體區14及PMOS電晶體區16以及兩個源極/ 汲極區域42、44分別設於金屬閘極64、66兩側的基底12 中。其中’ NMOS電晶體區14的金屬閘極64包含有一襯 氧化層68設於金屬閘極64的底部、一 u型高介電常數介 電層54設於襯氧化層68上並覆蓋金屬閘極64的側壁、一 U型遮蓋層56設於U型高介電常數介電層54上、一 u型 金屬層60設於U型遮蓋層56上以及一導電層62填滿金屬 閘極64内的剩餘開口。 201010008 PMOS電晶體區16的金屬閘極66則包含有一襯氧化層 68設於金屬閘極66的底部、一 U型高介電常數介電層54 設於襯氧化層68上並覆蓋金屬閘極66的側壁、一 U型金 屬層60設於U型高介電常數介電層54上以及一導電層62 設於U型金屬層60上並填滿金屬閘極66内的剩餘開口。 第8圖所示的實施例中的PMOS電晶體區16並未設置任何 的遮蓋層，但如上所述，本發明又可依據製程的需求同樣 ^ 在PMOS電晶體區16設置一 U型遮蓋層於U型高介電常 數介電層54及U型金屬層60之間，以調整P型金屬的功 函數。 此外，依據本發明另一實施例，當閘極絕緣層20是由 高介電常數的介電材料所構成時，可直接沈積遮蓋層56於 NMOS電晶體區14及PMOS電晶體區16的層間介電層50 與開口 52侧壁及底部，而完成如第9圖所示的電晶體結 ❹ 構。如第9圖所示，本實施例的CMOS電晶體主要包含有 一基底12、兩個金屬閘極64、66分別設置於基底12上的 NMOS電晶體區14及PMOS電晶體區16以及兩個源極/ 汲極區域42、44分別設於金屬閘極64、66兩側的基底12 中。其中，NMOS電晶體區14的金屬閘極64包含有一閘 極絕緣層20設於金屬閘極64的底部、一 U型遮蓋層56 設於閘極絕緣層20上並覆蓋金屬閘極64的侧壁、一 U型 金屬層60設於U型遮蓋層56上以及一導電層62填滿金屬 17 201010008 閘極64内的剩餘開口。 PMOS電晶體區16的金屬閘極66則包含有一閘極絕緣 層20設於金屬閘極66的底部、一 U型金屬層60設於閘極 絕緣層20上並覆蓋金屬閘極66的側壁以及一導電層62設 於U型金屬層60上並填滿金屬閘極66内的剩餘開口。如 同第8圖之電晶體結構，第9圖所示的PMOS電晶體區16 @ 並未設置任何的遮蓋層，但本發明又可依據製程的需求同 樣在PMOS電晶體區16設置一 U型遮蓋層於閘極絕緣層 20及U型金屬層60之間，以調整P型金屬的功函數。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 © 【圖式簡單說明】 第1圖至第8圖為本發明較佳實施例製作一具有金屬閘極 之電晶體不意圖。 第9圖為本發明一實施例之CMOS電晶體結構示意圖。 【主要元件符號說明】 12 基底 14 NMOS電晶體區 16 PMOS電晶體區 18 淺溝隔離結構 18 201010008 20 閘極絕緣層 22 多晶矽層 24 遮罩層 26 多晶石夕閘極 28 輕摻雜汲極 30 輕摻雜;及極 32 氧化矽層 34 側壁子 36 保護層 38 矽鍺層 40 側壁子 42 源極/、/及極區域 44 源極/;及極區域 46 石夕化金屬層 氣 48 氮化矽層 50 層間介電層 52 開口 54 高介電常數介電層 56 遮蓋層 58 圖案化光阻層 60 金屬層 62 導電層 64 金屬閘極 66 金屬閘極 ❹ 19Then, a gate insulating layer 2G is formed on the surface of the substrate 2 by a dielectric material such as an oxide or a nitride, and the gate insulating layer 2 can also be a closed oxide layer and a dielectric material having a high dielectric constant. The layer is composed of high=electric, and the dielectric materials are, for example, (iv) oxygen compound (HfSi〇), money supply nitrogen = compound (HfSiON), oxidation (Hfo), oxidized steel (La〇), sauerite ( LaAlO), oxidized (Zr〇), decanoic acid (ZrSi〇) or acid (HfZrO). Formed on the gate insulating layer 2 () a dummy gate having a thickness of about 1 angstrom (du_y (6) layer, for example, 2 layers 22, on the gate insulating layer 20 and The mask layer 24 is on the polysilicon layer 22. In the preferred embodiment, the mask layer 24 may be composed of a material such as germanium dioxide (Si〇2), tantalum nitride or hafnium oxynitride (SiON), and the polysilicon layer is formed. 22 may be composed of a polycrystalline germanium material having no undoped or a polycrystalline germanium material having an N+ dopant, which is within the scope of the present invention. Next, as shown in FIG. 2, a patterned photoresist layer is formed. (not shown) on the polysilicon layer 22, and using a patterned photoresist layer as a mask for a pattern transfer process, a single etching or successive etching steps to remove portions of the mask layer 24, the polysilicon layer 22 and the gate The insulating layer 20 is stripped and the patterned photoresist layer is stripped to form a dummy gate in each of the NMOS transistor region 14 and the pM〇s transistor region 16, such as the polycrystalline spine in this embodiment. 26. 201010008 As shown in FIG. 3, then each of the NMOS transistor regions 14 & pM〇s transistor region 16 is shallow The doping process is performed to form a desired nugget. For example, the present invention may first cover a patterned photoresist layer (not shown) in a region other than the L-electrode region 14 and then utilize the pattern. The photoresist layer is ion-implanted as a mask, and the N-type phosphor is implanted into the substrate 12 on both sides of the polysilicon gate 26 of the Secant transistor region 14 to form the NM〇s transistor region 14 - Lightly doping the electrode 28. Then removing the pattern of the above-described patterned germanium photoresist layer 'overlying another patterned photoresist layer in the region other than the PMOS transistor region 16' and using the patterned photoresist layer as a mask Another ion implantation implants a P-type dopant into the substrate 12 on both sides of the polysilicon of the PM 〇s transistor region i 6 to form a light doping in the PM 〇s transistor region 16 The drain 30» / is subsequently subjected to the side wall process of the second stage, for example, the surface of the side wall of the purified polycrystalline stone pole 26 forms a layer of a oxidized stone layer 32, which is then formed by deposition, retracement - for example It is the side wall of the nitride layer which is composed of the outer side wall of the polycrystalline stone of the osf crystal ship 14#PM0S transistor region 16. As shown in Fig. 4, a protective layer 36 made of tantalum nitride is applied to the surface of the sidewall 34, and then a selective epitaxial growth (SEG) process is performed to NM〇s. A strain 矽 is formed in the substrate 12 of the transistor region 14 or the PMOS transistor region 16. (201010, for example, two grooves may be formed in the substrate 12 on both sides of the polysilicon gate 26 of the PMOS transistor region 16, and the selectivity is reused. The epitaxial growth process substantially fills the two grooves to form the tantalum layer 38. The germanium layer 38 can apply a compressive strain to the channel region of the PMOS transistor region 16 to increase the hole mobility of the PM〇S transistor. Then, the second stage sidewall process is performed. For example, a sidewall 40 formed of yttrium oxide may be formed on the sidewalls of the protective layer 36 of the NMOS transistor region 14 and the PMOS transistor region 16. A heavily doped ion implantation process is then performed in the NMOS transistor region 14 to form the desired source/'; and polar regions. As described above for forming a lightly doped drain, the present invention may first cover a patterned photoresist layer (not shown) in a region other than the NMOS transistor region 14, and then use the patterned photoresist layer as a mask. An ion implantation process is performed, and an N-type dopant is implanted into the substrate 12 on both sides of the sidewall 4 to form a source/no-polar region 42 in the NMOS transistor region 14, and then the patterned photoresist is removed. Floor. The source/drain 44 of the PM〇s transistor region 16 can also be formed by a heavily doped ion implantation process in the same manner as the NMOS transistor region 14, preferably in selective doped crystal growth with doping ( In-situ dope) is formed at the same time, and as shown in Fig. 4, the source/drain 44 is formed by a phased co-doping method in which the selective insect crystal growth is initially doped without being doped. 12 201010008 Then, after forming the source/drain regions 42, 44, a self-aligned siUcide (Salicide) process is performed. For example, a metal layer composed of cobalt, titanium, nickel, platinum, palladium or molybdenum (not shown) is first formed on the surface of the substrate 12, and is combined with a rapid temperature annealing process to form a metal layer by using a high temperature. The surface of the substrate 12 on both sides of the side wall 4 turns into a deuterated metal layer 46. Finally, the unreacted metal layer is removed. ◎ Next, a tantalum nitride layer 48 is formed on each of the polysilicon gates 26, the sidewalls 40, and the surface of the substrate 12. In the preferred embodiment, the tantalum nitride layer 48 has a thickness of about 100 angstroms, which is primarily used as one of the etch stop layers for subsequent planarization. Then, an interlayer dielectric layer 50 composed of an oxide is formed and covers the NMOS transistor region 14 and the tantalum nitride layer 48 of the PMOS transistor region 16. As shown in FIG. 5, a chemical ❹ mechanical polishing (CMP) process or a dry etching process is performed to remove portions of the interlayer dielectric layer 50, the tantalum nitride layer 48, and the mask layer 24 until the polycrystalline free The surface of the pole 26 is 'and the top of the polycrystalline dream gate 26 is approximately flush with the surface of the interlayer dielectric layer 50. As shown in Fig. 6, a selective etching process is performed, for example, using ammonium hydroxide (NH4〇H) or Tetramethylammonium Hydroxide (TMAH) to remove the NMOS transistor region 14 201010008. And the polycrystalline spine in the pM〇s transistor region 16 but not the interlayer dielectric layer 5〇. In this embodiment, the etch process removes the polysilicon gate 26 of each of the transistor regions 14, 16 to form an opening 52 while exposing the underlying gate insulating layer 20. When the gate insulating layer 20 is a general dielectric material layer, the gate insulating layer 20 is removed to expose the underlying substrate 12. Then, an etchant layer 68, a high-k dielectric layer 54 and a capping layer 56knm〇S transistor region 14 and an interlayer dielectric layer 5〇 and an opening 52 sidewall of the PMOS transistor region 16 are sequentially deposited. And the bottom. In the present embodiment, the high-k dielectric layer 54 may be composed of a beryllic acid oxy-compound (HfSiO), an anthraquinone oxynitride (HfSiON), hafnium oxide (HfO), lanthanum oxide (LaO), or lanthanum aluminate. (LaA丨〇), oxidized (ZrO), Oxalic acid (ZrSiO) or wrong acid (jjfZrO) and other materials, while the cover layer 56 is made of oxidized steel (LaO), oxidized town (MgO ), yttrium oxide (Dy203) or other lanthanide oxide. However, when the gate insulating layer 20 is a high dielectric constant dielectric material, the deposition mask layer 56 is directly deposited on the NMOS transistor region 14 and the interlayer dielectric layer 50 and the opening 52 side of the pm〇s transistor region 16. Wall and bottom. A patterned photoresist layer 58 is then formed overlying the NMOS transistor region 14, and an etch process is performed using the patterned photoresist layer 58 as a mask to remove the capping layer 56 in the PMOS transistor region 16. 201010008 As shown in FIG. 7, after removing the patterned photoresist layer 58, a metal layer 60 is deposited on the capping layer 56 of the NMOS transistor region 14 and the high-k dielectric layer 54 of the PMOS transistor region 16. on. In the present embodiment, the metal layer 60 may be made of a material such as titanium nitride (TiN), carbonized button (TaC), nitride button (TaN), 1 fossil button (TaSiN), or nitriding titanium (TiA1N). Composition. It should be noted that the present invention mainly requires the work function of the adjustment metal layer 60 by the cover layer 56 of the metal layer 6 to define the work function of the NMOS transistor and the PMOS transistor. The Fermi level of the success function is close to the N-type Si (N_type Si) and the p-type 矽 (P-typeSi) Quasi Fermi level metal, making the CMOS transistor reachable. Better performance. Taking the above-mentioned cover layer 56 covered by the NM〇s transistor region 14 as an example, the present invention covers a cover layer 56 made of yttrium oxide under the metal layer 6〇 before the formation of the metal layer 6〇, and then borrows The masking layer 50 thus defines the work function of the N-type metal. However, the present invention is not limited to this. The present invention can also cover a pM 〇s transistor region 16 with a capping layer (not shown) between the high-k dielectric layer 54 and the metal layer 60. The cover layer defines the work function of the p-type metal. For example, the present invention can form another material such as alumina (a12〇3), aluminum nitride (ΑΐΝ〇 or oxynitride) after removing the mask layer 56 of the PMOS transistor region 16. The mask layer is formed on the high-k dielectric layer 54 of the pM〇s transistor region w 15 201010008, and then the metal layer 60 is completely covered, which is within the scope of the present invention. When the opening 52 is still not filled, a conductive layer 62 of a low-resistance material is selectively filled in the NMOS transistor region 14 and the metal layer 60 of the PMOS transistor region 16 and fills the opening 52. In this embodiment, the conductive layer 62 may be made of a low-resistance material such as aluminum, tungsten, titanium aluminum alloy (TiAl) or cobalt tungsten phosphide (CoWP). Finally, another chemical mechanical polishing process is performed. A portion of the conductive layer 62 and the metal layer 60' are removed to form a transistor having metal gates 64, 66, respectively, in the NMOS transistor region 14 and the PMOS transistor region 16. Further, as shown in FIG. 8, the present invention is based on the above The process further discloses a CMOS transistor junction having metal gates 64 and 66. The structure comprises a substrate 12, two metal gates 64, 66 respectively disposed on the substrate 12, a NMOS transistor region 14 and a PMOS transistor region 16, and two source/drain regions 42, 44 respectively. The metal gate 64 of the NMOS transistor region 14 includes a liner oxide layer 68 disposed at the bottom of the metal gate 64, and a U-type high dielectric constant dielectric. The layer 54 is disposed on the liner oxide layer 68 and covers the sidewall of the metal gate 64. A U-shaped mask layer 56 is disposed on the U-type high-k dielectric layer 54 and a U-shaped metal layer 60 is disposed on the U-type mask layer. 56 and a conductive layer 62 fill the remaining openings in the metal gate 64. 201010008 The metal gate 66 of the PMOS transistor region 16 includes a liner oxide layer 68 disposed at the bottom of the metal gate 66, a U-type high dielectric The electrically constant dielectric layer 54 is disposed on the liner oxide layer 68 and covers the sidewall of the metal gate 66. A U-shaped metal layer 60 is disposed on the U-type high-k dielectric layer 54 and a conductive layer 62 is disposed on the U-type. The metal layer 60 fills the remaining openings in the metal gate 66. The PMOS transistor region 16 in the embodiment shown in Fig. 8 does not. Any cover layer is provided, but as described above, the present invention can also provide a U-shaped mask layer on the U-type high-k dielectric layer 54 and the U-type metal layer 60 in the PMOS transistor region 16 according to the requirements of the process. In addition, in accordance with another embodiment of the present invention, when the gate insulating layer 20 is composed of a dielectric material having a high dielectric constant, the capping layer 56 may be directly deposited on the NMOS. The interlayer dielectric layer 50 of the transistor region 14 and the PMOS transistor region 16 and the sidewalls and the bottom of the opening 52 complete the transistor junction structure as shown in Fig. 9. As shown in FIG. 9, the CMOS transistor of the present embodiment mainly includes a substrate 12, two metal gates 64, 66, and an NMOS transistor region 14 and a PMOS transistor region 16 respectively disposed on the substrate 12, and two sources. The pole/drain regions 42, 44 are disposed in the substrate 12 on either side of the metal gates 64, 66, respectively. The metal gate 64 of the NMOS transistor region 14 includes a gate insulating layer 20 disposed on the bottom of the metal gate 64, and a U-shaped mask layer 56 disposed on the gate insulating layer 20 and covering the side of the metal gate 64. A wall, a U-shaped metal layer 60 is disposed on the U-shaped cover layer 56 and a conductive layer 62 fills the remaining openings in the gates 61 of the metal 17 201010008. The metal gate 66 of the PMOS transistor region 16 includes a gate insulating layer 20 disposed on the bottom of the metal gate 66, a U-shaped metal layer 60 disposed on the gate insulating layer 20 and covering the sidewall of the metal gate 66 and A conductive layer 62 is disposed over the U-shaped metal layer 60 and fills the remaining openings in the metal gate 66. As in the transistor structure of FIG. 8, the PMOS transistor region 16 @ shown in FIG. 9 does not have any mask layer, but the present invention can also provide a U-shaped mask in the PMOS transistor region 16 according to the requirements of the process. The layer is between the gate insulating layer 20 and the U-shaped metal layer 60 to adjust the work function of the P-type metal. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the invention are intended to be included in the scope of the present invention. [Embodiment of the drawings] Figs. 1 to 8 are diagrams for fabricating a transistor having a metal gate according to a preferred embodiment of the present invention. FIG. 9 is a schematic structural view of a CMOS transistor according to an embodiment of the present invention. [Main component symbol description] 12 Substrate 14 NMOS transistor region 16 PMOS transistor region 18 Shallow trench isolation structure 18 201010008 20 Gate insulating layer 22 Polysilicon layer 24 Mask layer 26 Polycrystalline etch gate 28 Lightly doped bungee 30 lightly doped; and 32 yttrium oxide layer 34 sidewall spacer 36 protective layer 38 germanium layer 40 sidewall spacer 42 source /, / and polar region 44 source /; and polar region 46 Shi Xihua metal layer gas 48 nitrogen矽 50 layer 50 interlayer dielectric layer 52 opening 54 high-k dielectric layer 56 mask layer 58 patterned photoresist layer 60 metal layer 62 conductive layer 64 metal gate 66 metal gate ❹ 19