JP4453960B2 - ダブル・ゲート・トランジスタおよび製法 - Google Patents
ダブル・ゲート・トランジスタおよび製法 Download PDFInfo
- Publication number
- JP4453960B2 JP4453960B2 JP2003507897A JP2003507897A JP4453960B2 JP 4453960 B2 JP4453960 B2 JP 4453960B2 JP 2003507897 A JP2003507897 A JP 2003507897A JP 2003507897 A JP2003507897 A JP 2003507897A JP 4453960 B2 JP4453960 B2 JP 4453960B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- silicon layer
- gate
- conductivity type
- polysilicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 65
- 229920005591 polysilicon Polymers 0.000 claims description 65
- 238000000034 method Methods 0.000 claims description 54
- 125000006850 spacer group Chemical group 0.000 claims description 47
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 44
- 229910052710 silicon Inorganic materials 0.000 claims description 44
- 239000010703 silicon Substances 0.000 claims description 44
- 150000004767 nitrides Chemical class 0.000 claims description 22
- 238000000151 deposition Methods 0.000 claims description 15
- 239000002019 doping agent Substances 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 12
- 230000005669 field effect Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 239000012212 insulator Substances 0.000 claims description 6
- 230000007261 regionalization Effects 0.000 claims description 5
- 238000002513 implantation Methods 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- GNFTZDOKVXKIBK-UHFFFAOYSA-N 3-(2-methoxyethoxy)benzohydrazide Chemical compound COCCOC1=CC=CC(C(=O)NN)=C1 GNFTZDOKVXKIBK-UHFFFAOYSA-N 0.000 claims 1
- FGUUSXIOTUKUDN-IBGZPJMESA-N C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 Chemical compound C1(=CC=CC=C1)N1C2=C(NC([C@H](C1)NC=1OC(=NN=1)C1=CC=CC=C1)=O)C=CC=C2 FGUUSXIOTUKUDN-IBGZPJMESA-N 0.000 claims 1
- 125000001475 halogen functional group Chemical group 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 37
- 239000007943 implant Substances 0.000 description 28
- 239000000463 material Substances 0.000 description 24
- 230000015572 biosynthetic process Effects 0.000 description 12
- 125000005843 halogen group Chemical group 0.000 description 8
- 230000008021 deposition Effects 0.000 description 6
- 238000001020 plasma etching Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 5
- 230000003647 oxidation Effects 0.000 description 5
- 238000007254 oxidation reaction Methods 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- 238000005516 engineering process Methods 0.000 description 4
- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 125000004429 atom Chemical group 0.000 description 2
- 230000003628 erosive effect Effects 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 1
- 230000001154 acute effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 210000000746 body region Anatomy 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000015654 memory Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000010405 reoxidation reaction Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000009827 uniform distribution Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
- H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Description
Claims (10)
- フィン型ダブル・ゲート電界効果トランジスタを形成する方法であって、
a)埋め込まれた誘電体層の上にシリコン層を備えるシリコン・オン・インシュレータ基板を用意する(101)ステップ、
b)前記シリコン層の上側にマンドレル層(212)を形成し、該マンドレル層をパターン形成し、該マンドレル層の前記パターン形成により露出された側の端部に側壁スペーサを設ける(102)ステップと、
c)残っているマンドレル層及び前記側壁スペーサをマスクとして用いて前記シリコン層をパターン形成して(104)、ダブル・ゲートの一方が形成される領域を画定するステップと、
d)前記シリコン層の、前記パターン形成により露出された側面にゲート酸化膜を形成する(104)ステップと、
e)前記ダブル・ゲートの一方が形成される領域に、第1導電型のポリシリコンを堆積させた後に平坦化するステップと、
f)前記残っているマンドレル層を選択的に除去して、前記側壁スペーサの、前記マンドレル層側の側面を露出させるステップと、
g)除去された前記残っているマンドレル層の下側のシリコン層を除去して、前記ダブル・ゲートの他方が形成される領域を画定するステップと、
h)前記側壁スペーサの下に位置するシリコン層の、ステップg)における前記除去により露出された側面にゲート酸化膜(221)を形成するステップと、
i)前記ダブル・ゲートの他方が形成される領域に第2導電型のポリシリコンを堆積させた後に平坦化する(112)ステップと、
j)前記側壁スペーサを除去し、該除去により形成された穴に真性ポリシリコンを充填するステップと、
k)前記第1導電型のポリシリコンと第2導電型のポリシリコンの上に延びる窒化物層を形成し、該窒化物層をマスクとして用いて、該第1導電型のポリシリコンと第2導電型のポリシリコンの、前記トランジスタのソース及びドレイン領域に近接する部分を選択的に除去するステップと、
を備える方法。 - フィン型ダブル・ゲート電界効果トランジスタを形成する方法であって、
a)埋め込まれた誘電体層の上にシリコン層を備えるシリコン・オン・インシュレータ基板を用意する(101)ステップ、
b)前記シリコン層の上側にマンドレル層(212)を形成し、前記マンドレル層をパターン形成するステップと、
c)残っているマンドレル層をマスクとして用いて前記シリコン層をパターン形成してダブル・ゲートの一方が形成される領域を画定する(104)ステップと、
d)前記シリコン層の前記パターン形成により露出された側面にゲート酸化膜を形成する(104)ステップと、
e)前記ダブル・ゲートの一方が形成される領域に、第1導電型のポリシリコンを堆積させた後に平坦化するステップと、
f)残っている前記マンドレル層を選択的に除去するステップと、
g)前記第1導電型のポリシリコンの、ステップf)における前記除去により露出された側の端部に側壁スペーサを設けるステップと、
h)前記除去されたマンドレル層の下側のシリコン層であって前記側壁スペーサで覆われていない部分のシリコン層を除去して、前記ダブル・ゲートの他方が形成される領域を画定するステップと、
i)前記側壁スペーサの下に位置するシリコン層の、ステップh)における前記除去により露出された側面にゲート酸化膜(221)を形成するステップと、
j)前記ダブル・ゲートの他方が形成される領域に第2導電型のポリシリコンを堆積させた後に平坦化する(112)ステップと、
k)前記側壁スペーサを除去し、それにより形成された穴に真性ポリシリコンを充填するステップと、
l)前記第1導電型のポリシリコンと第2導電型のポリシリコンの上に延びる窒化物層を形成し、該窒化物層をマスクとして用いて、該第1導電型のポリシリコンと第2導電型のポリシリコンの、前記トランジスタのソース及びドレイン領域に近接する部分を選択的に除去するステップと、
を備える方法。 - 前記シリコン層のソース及びドレイン領域にドーパントを打込むステップをさらに備える請求項1または2記載の方法。
- ステップd)において、ゲート酸化膜を形成する前に、シリコン層の露出された側から前記シリコン層にドーパントを打込み、及び、ステップh)において、ゲート酸化膜を形成する前に、シリコン層の露出された側から前記シリコン層にドーパントを打込むステップをさらに含む、請求項1記載の方法。
- ステップd)において、ゲート酸化膜を形成する前に、シリコン層の露出された側から前記シリコン層にドーパントを打込み、及び、ステップi)において、ゲート酸化膜を形成する前に、シリコン層の露出された側から前記シリコン層にドーパントを打込むステップをさらに含む、請求項2記載の方法。
- 前記シリコン層のソース及びドレイン領域にドーパントを打込むステップが、ハロー打込みにより行なわれる、請求項3に記載の方法。
- 前記第1導電型のポリシリコンがn型ポリシリコンであり、前記第2導電型のポリシリコンがp型ポリシリコンである、請求項1〜6のいずれか1項に記載の方法。
- ステップb)において、前記シリコン層の上に第1酸化物層、窒化物層、及び第2酸化物層を順次形成し、該第2酸化物層の上に前記マンドレル層が形成される、請求項1または2に記載の方法。
- 前記側壁スペーサが窒化珪素を堆積した後、指向性エッチングを行なうことにより形成される、請求項1または2記載の方法。
- 請求項1〜9のいずれか1項に記載の方法を使用して製造されるフィン型ダブル・ゲート電界効果トランジスタ。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/886,823 US6960806B2 (en) | 2001-06-21 | 2001-06-21 | Double gated vertical transistor with different first and second gate materials |
PCT/EP2002/006202 WO2003001604A2 (en) | 2001-06-21 | 2002-06-06 | Double gated transistor and method of fabrication |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004531085A JP2004531085A (ja) | 2004-10-07 |
JP4453960B2 true JP4453960B2 (ja) | 2010-04-21 |
Family
ID=25389849
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003507897A Expired - Fee Related JP4453960B2 (ja) | 2001-06-21 | 2002-06-06 | ダブル・ゲート・トランジスタおよび製法 |
Country Status (9)
Country | Link |
---|---|
US (3) | US6960806B2 (ja) |
JP (1) | JP4453960B2 (ja) |
KR (1) | KR100518128B1 (ja) |
CN (1) | CN1272855C (ja) |
AU (1) | AU2002317778A1 (ja) |
DE (1) | DE10296953B4 (ja) |
IL (1) | IL159476A0 (ja) |
TW (1) | TW578295B (ja) |
WO (1) | WO2003001604A2 (ja) |
Families Citing this family (76)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6770516B2 (en) * | 2002-09-05 | 2004-08-03 | Taiwan Semiconductor Manufacturing Company | Method of forming an N channel and P channel FINFET device on the same semiconductor substrate |
US20060154423A1 (en) * | 2002-12-19 | 2006-07-13 | Fried David M | Methods of forming structure and spacer and related finfet |
JP2005086024A (ja) * | 2003-09-09 | 2005-03-31 | Toshiba Corp | 半導体装置及びその製造方法 |
KR100506460B1 (ko) * | 2003-10-31 | 2005-08-05 | 주식회사 하이닉스반도체 | 반도체소자의 트랜지스터 및 그 형성방법 |
US7091566B2 (en) * | 2003-11-20 | 2006-08-15 | International Business Machines Corp. | Dual gate FinFet |
US7176092B2 (en) * | 2004-04-16 | 2007-02-13 | Taiwan Semiconductor Manufacturing Company | Gate electrode for a semiconductor fin device |
KR100555569B1 (ko) | 2004-08-06 | 2006-03-03 | 삼성전자주식회사 | 절연막에 의해 제한된 채널영역을 갖는 반도체 소자 및 그제조방법 |
US6969659B1 (en) | 2004-08-12 | 2005-11-29 | International Business Machines Corporation | FinFETs (Fin Field Effect Transistors) |
US20060046392A1 (en) * | 2004-08-26 | 2006-03-02 | Manning H M | Methods of forming vertical transistor structures |
US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7115525B2 (en) | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
US7655387B2 (en) * | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
KR100679693B1 (ko) * | 2004-10-29 | 2007-02-09 | 한국과학기술원 | 비대칭적인 일함수를 갖는 이중 게이트 구조를 이용한2비트 비휘발성 메모리 소자 제조 방법 및 그 구조 |
US7193279B2 (en) * | 2005-01-18 | 2007-03-20 | Intel Corporation | Non-planar MOS structure with a strained channel region |
US7202117B2 (en) * | 2005-01-31 | 2007-04-10 | Freescale Semiconductor, Inc. | Method of making a planar double-gated transistor |
US7518196B2 (en) | 2005-02-23 | 2009-04-14 | Intel Corporation | Field effect transistor with narrow bandgap source and drain regions and method of fabrication |
US7390746B2 (en) | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7253118B2 (en) | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
US7429536B2 (en) | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US7396781B2 (en) | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US7413981B2 (en) | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
US8123968B2 (en) | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
US7816262B2 (en) | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
US7829262B2 (en) * | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7572572B2 (en) | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
US7759197B2 (en) | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7776744B2 (en) | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7842558B2 (en) | 2006-03-02 | 2010-11-30 | Micron Technology, Inc. | Masking process for simultaneously patterning separate regions |
US7476933B2 (en) | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US8003310B2 (en) | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7795149B2 (en) | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US7723009B2 (en) | 2006-06-02 | 2010-05-25 | Micron Technology, Inc. | Topography based patterning |
KR101146588B1 (ko) | 2006-08-11 | 2012-05-16 | 삼성전자주식회사 | Fin 구조체 및 이를 이용한 핀 트랜지스터의 제조방법 |
US7611980B2 (en) | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
US7659579B2 (en) * | 2006-10-06 | 2010-02-09 | International Business Machines Corporation | FETS with self-aligned bodies and backgate holes |
JP2008098553A (ja) | 2006-10-16 | 2008-04-24 | Elpida Memory Inc | 半導体装置及びその製造方法 |
US7960760B2 (en) * | 2006-12-28 | 2011-06-14 | Texas Instruments Incorporated | Electrically programmable fuse |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US8563229B2 (en) | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US7737039B2 (en) | 2007-11-01 | 2010-06-15 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
US7659208B2 (en) | 2007-12-06 | 2010-02-09 | Micron Technology, Inc | Method for forming high density patterns |
US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US8030218B2 (en) | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US7982269B2 (en) * | 2008-04-17 | 2011-07-19 | International Business Machines Corporation | Transistors having asymmetric strained source/drain portions |
US8076208B2 (en) | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
US8101497B2 (en) | 2008-09-11 | 2012-01-24 | Micron Technology, Inc. | Self-aligned trench formation |
US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
US7999332B2 (en) * | 2009-05-14 | 2011-08-16 | International Business Machines Corporation | Asymmetric semiconductor devices and method of fabricating |
US8617937B2 (en) | 2010-09-21 | 2013-12-31 | International Business Machines Corporation | Forming narrow fins for finFET devices using asymmetrically spaced mandrels |
EP2731109B1 (en) | 2010-12-14 | 2016-09-07 | SanDisk Technologies LLC | Architecture for three dimensional non-volatile storage with vertical bit lines |
CN102903750B (zh) * | 2011-07-27 | 2015-11-25 | 中国科学院微电子研究所 | 一种半导体场效应晶体管结构及其制备方法 |
US9171584B2 (en) | 2012-05-15 | 2015-10-27 | Sandisk 3D Llc | Three dimensional non-volatile storage with interleaved vertical select devices above and below vertical bit lines |
CN103426756B (zh) * | 2012-05-15 | 2016-02-10 | 中国科学院微电子研究所 | 半导体器件及其制造方法 |
KR101286707B1 (ko) * | 2012-05-17 | 2013-07-16 | 서강대학교산학협력단 | 독립된 듀얼 게이트의 핀펫 구조를 갖는 터널링 전계효과 트랜지스터 및 그 제조방법 |
KR101402697B1 (ko) * | 2012-12-11 | 2014-06-03 | 한국과학기술원 | 독립적 및 대칭적인 이중 게이트 구조를 이용한 전자-정공 이중층 터널 전계 효과 트랜지스터 및 그 제조 방법 |
US9202694B2 (en) | 2013-03-04 | 2015-12-01 | Sandisk 3D Llc | Vertical bit line non-volatile memory systems and methods of fabrication |
US9165933B2 (en) | 2013-03-07 | 2015-10-20 | Sandisk 3D Llc | Vertical bit line TFT decoder for high voltage operation |
CN104576386B (zh) * | 2013-10-14 | 2018-01-12 | 中国科学院微电子研究所 | 一种FinFET及其制造方法 |
KR102124063B1 (ko) | 2013-10-29 | 2020-06-18 | 삼성디스플레이 주식회사 | 표시 장치 및 이의 제조 방법 |
US9362338B2 (en) | 2014-03-03 | 2016-06-07 | Sandisk Technologies Inc. | Vertical thin film transistors in non-volatile storage systems |
US9379246B2 (en) | 2014-03-05 | 2016-06-28 | Sandisk Technologies Inc. | Vertical thin film transistor selection devices and methods of fabrication |
US9627009B2 (en) | 2014-07-25 | 2017-04-18 | Sandisk Technologies Llc | Interleaved grouped word lines for three dimensional non-volatile storage |
CN105990344B (zh) * | 2015-02-28 | 2018-10-30 | 北大方正集团有限公司 | 一种cmos集成电路 |
US9450023B1 (en) | 2015-04-08 | 2016-09-20 | Sandisk Technologies Llc | Vertical bit line non-volatile memory with recessed word lines |
US9793270B1 (en) | 2016-04-21 | 2017-10-17 | International Business Machines Corporation | Forming gates with varying length using sidewall image transfer |
US10381348B2 (en) | 2017-01-10 | 2019-08-13 | International Business Machines Corporation | Structure and method for equal substrate to channel height between N and P fin-FETs |
US10734479B1 (en) | 2019-01-23 | 2020-08-04 | International Business Machines Corporation | FinFET CMOS with asymmetric gate threshold voltage |
US10790357B2 (en) | 2019-02-06 | 2020-09-29 | International Business Machines Corporation | VFET with channel profile control using selective GE oxidation and drive-out |
US11158715B2 (en) | 2019-06-20 | 2021-10-26 | International Business Machines Corporation | Vertical FET with asymmetric threshold voltage and channel thicknesses |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3872491A (en) | 1973-03-08 | 1975-03-18 | Sprague Electric Co | Asymmetrical dual-gate FET |
US4041519A (en) * | 1975-02-10 | 1977-08-09 | Melen Roger D | Low transient effect switching device and method |
US5032529A (en) * | 1988-08-24 | 1991-07-16 | Harris Corporation | Trench gate VCMOS method of manufacture |
US4996575A (en) * | 1989-08-29 | 1991-02-26 | David Sarnoff Research Center, Inc. | Low leakage silicon-on-insulator CMOS structure and method of making same |
JP2994670B2 (ja) * | 1989-12-02 | 1999-12-27 | 忠弘 大見 | 半導体装置及びその製造方法 |
US5391506A (en) * | 1992-01-31 | 1995-02-21 | Kawasaki Steel Corporation | Manufacturing method for semiconductor devices with source/drain formed in substrate projection. |
US5563093A (en) | 1993-01-28 | 1996-10-08 | Kawasaki Steel Corporation | Method of manufacturing fet semiconductor devices with polysilicon gate having large grain sizes |
JP3252578B2 (ja) * | 1993-12-27 | 2002-02-04 | ソニー株式会社 | 平面型絶縁ゲート電界効果トランジスタの製法 |
JP3238820B2 (ja) | 1994-02-18 | 2001-12-17 | 富士通株式会社 | 半導体装置 |
JPH0832040A (ja) | 1994-07-14 | 1996-02-02 | Nec Corp | 半導体装置 |
US5576227A (en) * | 1994-11-02 | 1996-11-19 | United Microelectronics Corp. | Process for fabricating a recessed gate MOS device |
JPH08204191A (ja) | 1995-01-20 | 1996-08-09 | Sony Corp | 電界効果トランジスタ及びその製造方法 |
US5512517A (en) | 1995-04-25 | 1996-04-30 | International Business Machines Corporation | Self-aligned gate sidewall spacer in a corrugated FET and method of making same |
DE19535629C1 (de) | 1995-09-25 | 1996-09-12 | Siemens Ag | Verfahren zur Herstellung einer integrierten CMOS-Schaltung |
DE19548056C1 (de) * | 1995-12-21 | 1997-03-06 | Siemens Ag | Verfahren zur Herstellung einer Gateelektrode für eine MOS-Struktur |
JPH09205152A (ja) | 1996-01-25 | 1997-08-05 | Sony Corp | 2層ゲート電極構造を有するcmos半導体装置及びその製造方法 |
US5780330A (en) | 1996-06-28 | 1998-07-14 | Integrated Device Technology, Inc. | Selective diffusion process for forming both n-type and p-type gates with a single masking step |
US5670397A (en) | 1997-01-16 | 1997-09-23 | Powerchip Semiconductor Corp. | Dual poly-gate deep submicron CMOS with buried contact technology |
US6015991A (en) | 1997-03-12 | 2000-01-18 | International Business Machines Corporation | Asymmetrical field effect transistor |
US5933721A (en) | 1997-04-21 | 1999-08-03 | Advanced Micro Devices, Inc. | Method for fabricating differential threshold voltage transistor pair |
US5939937A (en) | 1997-09-29 | 1999-08-17 | Siemens Aktiengesellschaft | Constant current CMOS output driver circuit with dual gate transistor devices |
US6197672B1 (en) | 1998-12-08 | 2001-03-06 | United Microelectronics Corp. | Method for forming polycide dual gate |
US6265293B1 (en) * | 1999-08-27 | 2001-07-24 | Advanced Micro Devices, Inc. | CMOS transistors fabricated in optimized RTA scheme |
US6362057B1 (en) * | 1999-10-26 | 2002-03-26 | Motorola, Inc. | Method for forming a semiconductor device |
US6396108B1 (en) * | 2000-11-13 | 2002-05-28 | Advanced Micro Devices, Inc. | Self-aligned double gate silicon-on-insulator (SOI) device |
US6693009B1 (en) * | 2000-11-15 | 2004-02-17 | Advanced Micro Devices, Inc. | Flash memory cell with minimized floating gate to drain/source overlap for minimizing charge leakage |
US6458662B1 (en) * | 2001-04-04 | 2002-10-01 | Advanced Micro Devices, Inc. | Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed |
US6586296B1 (en) * | 2001-04-30 | 2003-07-01 | Cypress Semiconductor Corp. | Method of doping wells, channels, and gates of dual gate CMOS technology with reduced number of masks |
-
2001
- 2001-06-21 US US09/886,823 patent/US6960806B2/en not_active Expired - Fee Related
-
2002
- 2002-06-06 AU AU2002317778A patent/AU2002317778A1/en not_active Abandoned
- 2002-06-06 WO PCT/EP2002/006202 patent/WO2003001604A2/en active Application Filing
- 2002-06-06 KR KR10-2003-7015974A patent/KR100518128B1/ko not_active IP Right Cessation
- 2002-06-06 CN CNB028122984A patent/CN1272855C/zh not_active Expired - Fee Related
- 2002-06-06 JP JP2003507897A patent/JP4453960B2/ja not_active Expired - Fee Related
- 2002-06-06 DE DE10296953T patent/DE10296953B4/de not_active Expired - Lifetime
- 2002-06-06 IL IL15947602A patent/IL159476A0/xx unknown
- 2002-06-20 TW TW091113496A patent/TW578295B/zh not_active IP Right Cessation
-
2005
- 2005-05-09 US US11/125,063 patent/US7288445B2/en not_active Expired - Fee Related
-
2007
- 2007-07-09 US US11/774,663 patent/US7645650B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
WO2003001604A2 (en) | 2003-01-03 |
US20050221543A1 (en) | 2005-10-06 |
DE10296953B4 (de) | 2010-04-08 |
US7288445B2 (en) | 2007-10-30 |
WO2003001604A3 (en) | 2003-09-04 |
IL159476A0 (en) | 2004-06-01 |
JP2004531085A (ja) | 2004-10-07 |
CN1518772A (zh) | 2004-08-04 |
DE10296953T5 (de) | 2004-04-29 |
US7645650B2 (en) | 2010-01-12 |
AU2002317778A1 (en) | 2003-01-08 |
US20020197781A1 (en) | 2002-12-26 |
CN1272855C (zh) | 2006-08-30 |
KR20040012900A (ko) | 2004-02-11 |
KR100518128B1 (ko) | 2005-10-04 |
TW578295B (en) | 2004-03-01 |
US6960806B2 (en) | 2005-11-01 |
US20070254438A1 (en) | 2007-11-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4453960B2 (ja) | ダブル・ゲート・トランジスタおよび製法 | |
US11515418B2 (en) | Vertical tunneling FinFET | |
US6492212B1 (en) | Variable threshold voltage double gated transistors and method of fabrication | |
US7256458B2 (en) | Doubly asymmetric double gate transistor structure | |
TWI495018B (zh) | 藉由晚期鰭部蝕刻以在圖案化的淺溝槽隔離區域上形成鰭部電晶體 | |
US9722043B2 (en) | Self-aligned trench silicide process for preventing gate contact to silicide shorts | |
JP3378414B2 (ja) | 半導体装置 | |
US6762101B2 (en) | Damascene double-gate FET | |
US9425105B1 (en) | Semiconductor device including self-aligned gate structure and improved gate spacer topography | |
US7687365B2 (en) | CMOS structure for body ties in ultra-thin SOI (UTSOI) substrates | |
US9245975B2 (en) | Recessed channel insulated-gate field effect transistor with self-aligned gate and increased channel length | |
US20060175669A1 (en) | Semiconductor device including FinFET having metal gate electrode and fabricating method thereof | |
US20050124099A1 (en) | Selfaligned source/drain finfet process flow | |
US20070158743A1 (en) | Thin silicon single diffusion field effect transistor for enhanced drive performance with stress film liners | |
US7648880B2 (en) | Nitride-encapsulated FET (NNCFET) | |
CN106328537B (zh) | 半导体元件及制造方法 | |
TW202129964A (zh) | 先進邏輯操作的電荷捕捉tfet半導體元件製作方法 | |
US20230402520A1 (en) | Staircase stacked field effect transistor |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20070903 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20080108 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20080404 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20080404 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20080404 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20080404 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20090108 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20090115 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20090126 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7424 Effective date: 20090212 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090317 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090615 Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20090615 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20090728 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20090730 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20090728 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20090908 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20091016 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100119 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
RD14 | Notification of resignation of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7434 Effective date: 20100120 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100129 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130212 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130212 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140212 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |