TW202129964A - 先進邏輯操作的電荷捕捉tfet半導體元件製作方法 - Google Patents

先進邏輯操作的電荷捕捉tfet半導體元件製作方法 Download PDF

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TW202129964A
TW202129964A TW109135329A TW109135329A TW202129964A TW 202129964 A TW202129964 A TW 202129964A TW 109135329 A TW109135329 A TW 109135329A TW 109135329 A TW109135329 A TW 109135329A TW 202129964 A TW202129964 A TW 202129964A
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tfet
source
nmos
pmos
charge trapping
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馬克 Ｉ 加德納
Ｈ 吉姆 富爾福德
安東 德維利耶
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日商東京威力科創股份有限公司
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Abstract

電荷捕捉穿隧場效電晶體(TFET)包括多層介電材料，其定義一電荷捕捉層。p摻雜之源極/汲極區域與n摻雜之源極區域透過奈米通道連接，該奈米通道形成於多層介電質之間，因而形成電荷捕捉TFET。

Description

先進邏輯操作的電荷捕捉TFET半導體元件製作方法
本發明係關於半導體元件之製造。更明確地，其係關於三維(3D)電晶體之製造，該三維電晶體包括在不同元件區域中使用多個選擇性奈米片用於製造之電荷捕捉穿隧場效電晶體(TFET)。 [相關申請案]
本申請案與2019年10月11日申請之美國非臨時專利申請案第16/656,911號有關並對其主張優先權，其整體內容皆併於此作為參考。
在半導體元件(尤其是在微小尺度上)之製造中，執行諸多製造製程，例如成膜沉積、蝕刻遮罩產生、圖案化、材料蝕刻及去除、以及摻雜處理。此些製程係重複執行，以在基板上形成所欲半導體元件單元。歷史上，利用微製造，已在一平面中產生電晶體，且佈線/金屬化形成於主動元件平面上方，因此已被表徵為二維(2D)電路或2D製造。微縮方面的努力已大幅增加2D電路中每單位面積電晶體的數量，但當微縮進入個位數奈米半導體元件製造時，微縮方面的努力正面臨更大的挑戰。半導體元件製造者已表達對三維(3D)半導體電路之需求，其中電晶體係堆疊於彼此上。
3D整合(即多個元件之垂直堆疊)旨在透過增加體積而非面積中之電晶體密度來克服平面元件中遭遇之微縮限制。雖然採用3D NAND元件之快閃記憶體產業已成功驗證並實施元件堆疊，但應用至邏輯設計實質上是更困難。正尋求邏輯晶片(例如，CPU(中央處理單元)、GPU(圖形處理單元)、FPGA(場可程式化閘陣列)、SoC(系統單晶片))之3D整合。
本文之技術包括3D電晶體之3D架構及其製造方法，3D電晶體在不同元件區域(即，N型金屬-氧化物-半導體(NMOS)、P型金屬-氧化物-半導體(PMOS)及新的元件類型)中使用多個選擇性奈米片用於製造。尤其，該等技術涉及製造電荷捕捉TFET(堆疊NMOS TFET與PMOS TFET兩者)之方法，以在多個電晶體平面上實現電晶體類型。TFET元件具有非常低的次臨界斜率(sub-threshold slope，SS)及低功率操作。透過添加固定量之受控電荷捕捉，每一電晶體可獲得改進之定制元件特性(即，穩健之電晶體參數、Vtcc、Idsat、Idoff)。此得以3D整合，因為電晶體Vt可透過電程式設計進行改變，以大幅擴展3D電路之邏輯選擇。
實施例包括使用堆疊奈米片之多個3D奈米平面上的電荷捕捉TFET，以製造具有3D元件佈局之TFET電荷捕捉電晶體。電荷捕捉TFET可用於設置NMOS與PMOS之閾值元件，以將邏輯設計最佳化。TFET電荷捕捉電晶體可由多層(例如，一層、兩層或三層)介電質堆疊所組成，以在奈米平面TFET中定義電荷捕捉層。
電荷捕捉特徵允許將Vt設為諸多值，以透過電荷捕捉之製程條件來調控Vt。此外，電荷捕捉TFET可依需求進行電程式設計及進一步再程式設計，以將Vt更改為多個值。此獨特特徵可作為3D開關。此特徵可使電路之某些部分能夠被修改以使用Vt來更改邏輯及電路功能，俾以調控電路(即，若電荷捕捉值的Vt高於電路Vt值，則電晶體(電荷捕捉TFET)將被關閉))。另外，3D電荷捕捉TFET亦可用作電路之某些區域中的記憶元件。
具電荷捕捉之穩健TFET對於使TFET具有最佳元件特性(Idsat、Idoff、Vtcc)是必要的。具3D電路邏輯之3D記憶電路需具有低功率及SS的TFET元件，對許多其他電路設計亦是如此。本申請描述在具有不同材料之多個奈米平面上製造此些元件的方法，以用於有效的電路佈局及設計。許多其他電路邏輯區塊需要本文所論及之關鍵元件(使用奈米片及3D元件架構)以變得可行。
由於電荷捕捉TFET可進行電程式設計以更改Vt，因此可製作獨特的邏輯元件(例如，靜態隨機存取記憶體(SRAM)、反相器、電晶體及其他3D形式之基本邏輯區塊)，但亦可更改以建立關鍵3D邏輯電路，其中邏輯及記憶元件可針對特定電路應用進行再程式化。
在一實施例中，形成在基板上之PMOS電荷捕捉TFET與NMOS電荷補捉TFET堆疊被使用作為反相器，其中對PMOS TFET與NMOS TFET之閘電極進行特定的分開控制，且亦分開控制源極與汲極區域兩者之邏輯連接。
本文所述之不同步驟的順序係以清楚目的來呈現。一般而言，此些步驟可依任何合適的順序來執行。另外，雖然本文中之每一不同特徵、技術、配置等可能是在本發明之不同地方來討論，但其用意為每一概念可彼此獨立地或相互組合地執行。據此，可以許多不同方式來具體實施並概觀本申請之特徵。
此「發明內容」段落並未指定本申請之每個實施例及/或新穎態樣。 相反地，此「發明內容」僅提供對不同實施例之初步討論以及相對於習知技術之新穎性的相應要點。所揭示之實施例的額外細節及/或可能觀點則描述於本發明之「實施方式」段落及對應圖式中，如下文進一步討論。
整篇本說明書中提及「一實施例」意指與實施例結合說明之特定特徵、結構、材料、或特性被包含在本申請之至少一實施例中，但不表示其存在於每一實施例中。因此，在整篇本說明書中之諸多地方所出現的「在一實施例中」詞語不一定指本申請之同一實施例。再者，該等特定特徵、結構、材料、或特性可在一或更多實施例中以任何適當方式結合。
本文所述之實施例包括電晶體基板平面之堆疊，以在多個電晶體平面上形成多維邏輯電路。本文之元件係使用奈米通道來具體實施。一般而言，術語「奈米通道」係指用於場效電晶體之奈米線或奈米片狀通道。奈米線係形成為具有大致圓形橫截面或圓化橫截面之相對小的細長結構。奈米線經常是從層來形成，層被圖案蝕刻以形成具有大致正方形橫截面之通道，接著此正方形橫截面結構的角例如透過蝕刻而被圓化，以形成圓柱結構。奈米片類似於奈米線，因為其具有相對小的橫截面(小於一微米，通常小於30奈米)，但具有矩形的橫截面。給定之奈米片可包括圓角。
迄今為止，尚未證明使用堆疊奈米片來製造具有3D元件佈局之TFET電荷捕捉電晶體的完整有效解決方式。由於TFET電晶體可具有受控數量的捕捉電荷，故可在電路之選擇區域/位置上，甚至在各個電晶體階層上控制臨界電壓(Vt)、飽和汲極電流(Idsat)、關閉時漏電流(Idoff)及其他關鍵元件特性。
現今互補FET(CFET)堆疊為2層堆疊(非捕捉堆疊)，其中層1為氧化物，而層2為HfO2 層。本文所述之電荷捕捉TFET與現有CFET相容。
在一實施例中，TFET電荷捕捉電晶體係由三層介電質之堆疊所組成，以在奈米平面TFET中定義電荷捕捉層。此示於圖1中。尤其，對於TFET元件，一源極/汲極區域為N摻雜，而相對側上之源極/汲極區域為P摻雜。該配置形成穿隧FET元件。該一源極/汲極區域透過奈米通道連接至另一源極/汲極區域，因而形成TFET。在圖1中，介電層1(例如，氧化物)為穿隧介電層。介電層2(例如，高k層，如HfO2 )是電荷捕捉層。介電層3(例如氧化物)為電荷滯留層。此些層可使用原子層沉積(ALD)來形成，但可使用其他方法，包括化學氣相沉積(CVD)。
圖2示出被包含有電荷捕捉層之複數介電層所圍繞之奈米通道的橫截面。該橫截面可為圓形、正方形或矩形。
圖3示出可用於形成圖1所示之電荷捕捉TFET電晶體之不同材料的示例。可修改層1、層2及層3的材料、厚度及特性，以調變並控制TFET中之電荷捕捉數量至電路應用所需之所欲特性。另外，可透過對電晶體施加偏壓來重新配置電荷捕捉TFET，以達到不同的補捉電荷狀態，從而將電路之諸多區域中的電晶體效能最佳化。
在另一實施例中，電荷捕捉層包括兩層介電質之堆疊。圖4示出可用於形成電荷捕捉TFET電晶體之不同材料的示例。對於2層堆疊系統，沉積介電層2之高k材料以形成可僅用2個介電沉積來控制之電荷捕捉。
在又另一實施例中，電荷捕捉層包括一層介電質。圖5示出可用於形成電荷捕捉TFET電晶體之不同材料的示例。對於1層堆疊系統，沉積高k材料以僅用一個介電沉積形成電荷捕捉。
2層介電沉積與1層介電沉積皆可導致透過原位處理所產生之3層系統(即氧化物界面/高k/氧化物)。另一選擇是，2層或1層系統可使用正確的閘電極與介電組合來保留2層或1層系統。形成每一介電質之後，亦可選擇原位退火以設置最佳數量的電荷捕捉。
典型3層系統示於圖6中，其使用HfO2 作為第二介電層。在此示例中，最小3層介電厚度為0.9 nm，最大3層介電厚度為3.5 nm。又，由於不同高k材料具有不同的k值，故物理厚度將根據所使用之材料而改變。
最大厚度及最小厚度皆可根據電路要求(Vt、Idoff及Idsat)而更高或更低。又，由於不同高k材料具有不同的k值，因此給定HfO2 厚度下之HfO2 等效氧化物厚度(EOT)相對於SiO2 更低。注意，在本文所述之方法中，較高k區域為電荷捕捉層。
層之EOT是透過以下得出：
EOT =高k層之厚度(SiO2 的k/高k層的k)
在一示例中，對於厚度為1.5 nm = 15 Å的HfO2 層，EOT為：
EOT ＝ 1.5nm (3.9 / 25)＝ 0.234nm ＝ 2.34 Å氧化物當量。即，15Å之HfO2 厚度等於氧化物的2.34 Å。透過使用較高k材料，電荷捕捉層可被製成更厚的物理厚度但小EOT。
使用三堆疊介質沉積，可在NMOS或PMOS元件中製造TFET電荷捕捉元件之3D堆疊。本文所述之方法具有改變電荷捕捉元件之Vt的能力，其透過改變製程條件或透過選擇性地對TFET進行程式設計以達最佳電路效能之所欲Vt窗。
尤其，電荷捕捉閘極介電堆疊本身可改變元件的Vt(材料類型、堆疊及厚度)。另外，金屬閘極材料類型功函數本身可改變Vt。電荷捕捉TFET可僅使用一種金屬，但亦可透過在電荷捕捉介電堆疊中添加或減去電荷捕捉而具有Vt調整的功能(例如，對於NMOS，通道中更多正電荷會提高NMOS的Vt，但降低PMOS的Vt，對於PMOS，通道中更多負電荷會增加PMOS的Vt，但降低NMOS的Vt)。
注意，以上三者之組合可用於改變Vt。
NMOS及PMOS可能有許多不同的金屬沉積，以達到特定電路應用之所欲Vt值。因此，電荷捕捉TFET允許對NMOS及PMOS元件有更加多且靈活的選擇。
本申請之特徵在於，一種金屬類型用於NMOS與PMOS電荷捕捉TFET元件兩者，其大幅降低製程複雜度。可使用之一些常見金屬為Ti、Ta、TiN、TaN、W、Ru、Pt、Co、NiSi、WSi、PtSi及CoSi。
NMOS TFET之經改變的Vt值範圍可例如從0.2V至1.5V，而PMOS TFET之經改變的Vt值範圍可例如從-0.2V至-1.5V(低壓(LV)邏輯電路之較佳範圍)。 然而，本申請之元件可涵蓋用於高壓(HV)邏輯電路之更高電壓範圍。一般而言，NMOS TFET元件具有正的Vt值，而PMOS TFET具有負的Vt值。以上討論之三個Vt設定過程中的任一者可對NMOS建立0.2V至1.5V的Vt值，以及對PMOS建立-0.2V至-1.5V的Vt值。
在三層PMOS電荷捕捉TFET之一實施例中，層的順序及其厚度如下所示。由於可對每一電晶體調變Vt，因此很多金屬閘電極材料選擇是可能的。
介電 1 : 0.3 nm至1.0 nm，界面氧化物層
介電層 2 : 0.3 nm至10.0 nm，HfO2 ， HfO2 之等效氧化物厚度(EOT)範圍為0.124 nm至1.56 nm SiO2 當量。
介電 3 : 0.3 nm至1.0 nm，氧化層
TiN : 0.9 nm
TaN : 0.9 nm
TiON : 2.7 nm
TiC : 2.7 nm
在三層NMOS電荷捕捉TFET之一實施例中，層的順序及其厚度如下所示。
介電 1 : 0.3 nm至1.0 nm，界面氧化物層
介電層 2 : 0.3 nm至10.0 nm，HfO2 ， HfO2 之等效氧化物厚度(EOT)範圍為0.124 nm至1.56 nm SiO2 當量。
介電 3 : 0.3 nm至1.0 nm，氧化層
TiC : 2.7 nm
在另一實施例中，TFET電荷捕捉電晶體係由形成於基板上之PMOS電荷捕捉TFET及NMOS電荷捕捉TFET的堆疊所組成。此示於圖7中。 尤其，在底部NMOS電荷捕捉TFET中，P摻雜之源極區域透過奈米通道連接至N摻雜之汲極區域，因而形成NMOS TFET。此外，介電層1(例如，氧化物)為穿隧介電層；介電層2(例如，高k層，如HfO2 )為電荷捕捉層；介電層3(例如氧化物)為電荷滯留層。此些層可使用ALD形成並定義電荷捕捉層。上部PMOS電荷捕捉TFET具有與下部NMOS電荷捕捉TFET類似的配置。
圖7的電荷捕捉TFET元件可分開控制NMOS TFET之閘電極與PMOS TFET之閘電極，以及分開邏輯控制兩個TFET之源極與汲極區域兩者。如圖7所示，鋰金屬帶可用於對兩個TFET之閘電極與源極/汲極區域提供六個連接。
圖7的電荷捕捉TFET元件可透過適當地配置源極與汲極區域及閘極的連接而被使用作為反相器，如圖8中所見。尤其，透過用Li帶連接兩閘極、連接PMOS TFET之汲極與NMOS TFET之源極以提供電壓輸出、並施加供應電壓Vdd(電源電壓)至PMOS TFET的源極，即可實施反相器元件。
在上述實施例之變化中，圖8的電荷捕捉TFET元件可透過實施不同於圖8元件之源極與汲極區域及閘極的連接而被使用作為反相器，如圖9中所見。與圖8中之連接不同的是，閘極透過ALD形成足夠厚度，使得其彼此接觸，因而刪除一金屬連接。
本申請之電荷捕捉TFET製造方法的描述提供於下。
現參考圖10，形成奈米片堆疊以用於環繞式閘極堆疊電晶體。此例如可用於CFET 3D元件。起始材料可為矽塊材、鍺塊材、絕緣層上覆矽(SOI)或其他晶圓或基板。多層材料可先形成為毯覆式沉積(blanket depositions)或磊晶生長。在此示例中，使用九層磊晶生長。例如，可生長諸多分子組合之矽、矽鍺及鍺層，Si(65)Ge(35)/Six Gey /Si/Six Gey /Si/Six Gey /Si/Six Gey /Si，典型範圍x從0.6至0.8，而y從0.4至0.2。接著，在膜堆上形成蝕刻遮罩。可對膜堆進行非等向性蝕刻以形成奈米片堆疊。自對準雙重圖案化或自對準四重圖案化可用於形成蝕刻遮罩。可形成埋入式電源導軌。額外微製造步驟可包括形成淺溝槽隔離(STI)、利用多晶矽建立偽閘極、選擇性SiGe釋放、沉積並蝕刻低k材料、以及形成犧牲性間隔物及內間隔物。圖10示出此處理之後的示例性基板部分。亦示出奈米片堆疊之間的填充材及/或頂層封膠。
從此奈米片堆疊繼續，在特定位置處打開溝槽以在水平或垂直位置處形成p-摻雜或n-摻雜的源極/汲極區域。
在基板上特定位置處形成一光罩，以遮擋或覆蓋NMOS區域，如圖11所示。
在NMOS區域被遮擋下，可將氧化物填充材(或其他填充材料)從顯露之奈米片堆疊之間去除。注意，可在通道之一或更多平面處去除氧化物填充材。注意，在此示例中，對於電晶體之兩平面，首先將氧化物填充材向下移除到上部電晶體平面與下部電晶體平面之間的斷開處。一示例示於圖12中。接著，可在奈米片堆疊之側壁上形成氮化矽間隔物。此可透過保形沉積且隨後進行間隔物開口蝕刻(定向蝕刻)來完成。因此，頂部P+未來源極/汲極區域被覆蓋，以防止後續步驟中的生長。
執行另一非等向性蝕刻以從下部電晶體平面去除氧化物填充材，因而顯露奈米片的矽。接著可去除光罩。圖13示出一示例結果。
P摻雜之SiGe或其他材料接著可生長於下部平面源極/汲極區域中。在完成磊晶生長之後，可用氧化物填充基板。任何超覆層(overburden)可使用化學\機械拋光(CMP)或其他平面化技術來去除。圖14示出基板部分之橫截面的示例結果。
接著，在此示例中，再次形成光罩以再次覆蓋NMOS區域。圖15示出一示例結果。
去除氧化物膜，以顯露上部電晶體平面。注意，可將氧化物填充材向下移除到下部電晶體平面之源極/汲極區域，接著添加間隔物。或者，可在下部電晶體平面之源極/汲極區域之前停止氧化物填充材移除，以在上部與下部源極/汲極區域之間留下間隔物。氧化物形成凹口之後，可去除覆蓋矽奈米片之氮化矽側壁。亦可去除光罩。示例結果示於圖16中。
亦可在底部源極/汲極區域顯露時形成局部互連。此可包括諸多沉積、形成遮罩、選擇性去除及選擇性沉積步驟，例如以形成釕觸點或其他所欲金屬。
P摻雜之源極/汲極區域可接著生長於上部電晶體平面之顯露部分中。接著可再次用氧化物填充基板並進行平面化。示例結果示於圖17中。
接下來可繼續進行處理以形成N摻雜源極/汲極。 添加第三光罩以覆蓋基板上P摻雜之源極汲極區域。使氧化物填充材充分地形成凹口，以顯露上部電晶體平面，而下部電晶體平面仍被覆蓋。示例結果示於圖18中。
在NMOS區域中顯露上部矽時，可添加氮化矽間隔物以覆蓋矽側壁。接著，可去除剩餘的氧化物填充材，使得下部電晶體平面中來自奈米片的矽顯露。亦可去除第三光罩。示例結果示於圖19中。
N摻雜材料可接著生長於下部平面源極/汲極區域中。在完成磊晶生長之後，可用氧化物填充基板。任何超覆層可使用CMP或其他平面化技術來去除。圖20示出基板部分之橫截面的示例結果。
上部P摻雜源極/汲極區域所述之類似處理可用於上部N摻雜源極汲極區域。氧化物填充材可添加至溝槽中。示例結果示於圖21中。
圖22示出透過上述方法形成之電荷捕捉TFET陣列。
從此點開始，可繼續進行額外處理。例如，可完成局部互連步驟以及進一步佈線。可去除偽多晶閘極材料。可完成所有電晶體之替換金屬閘極。此可包括去除氧化物、SiGe通道釋放、矽蝕刻修整、沉積界面SiO、沉積高k材料、沉積TiN、TaN、TiAl或其他所欲功函數金屬之任一者。PMOS元件之替換金屬閘極可包括沉積有機平坦化層並使平坦化層之選定部分形成凹口，以及去除TiAL。
注意，N摻雜與P摻雜源極/汲極區域可透過改變遮罩磊晶生長而在任何位準(垂直位準)互換。此外，N摻雜與P摻雜源極/汲極區域可在基板上之任何水平坐標位置處互換。以此方式，可實施電荷捕捉TFT陣列(例如，圖21(於一維延伸)所示之配置於二維延伸)。在其他實施例中，不同類型的材料以及不同的摻雜程度可執行於不同電晶體平面上之S/D磊晶。
據此，可用電路元件所需之任何數量的FET來建立並排的TFET。 對稱之源極/汲極CMOS元件可在同一製程內與不對稱之S/D TFET CMOS整合。 本文技術透過分開堆疊彼此緊鄰之NMOS與PMOS元件，使得NMOS與PMOS元件之靈活設置能夠被更有效地整合以用於電路設計佈局。本文方法提供靈活度，以根據電路要求或設計目標來製造一個奈米平面至十個以上奈米平面。
本文所述之電荷捕捉TFET的優點包括：1)透過使精確受控之電荷捕捉數量最佳化，可達成具有可預測電晶體特性之穩定電晶體(即，Ids vs Vt、Idoff vs Idsat)； 2)電荷捕捉TFET元件有更低的SS及更佳的效能(晶片佈局之每一區域均可獲得驅動電流)；3)用於低電壓之多個且穩定的Vt值；4)根據電路要求，新的電晶體架構將達到電晶體之N=1至N≥10基板平面；5)本申請之電荷捕捉TFET可透過些許額外的製程步驟與現有的CFET共整合。未來的微縮將需要新的電荷捕捉穿隧電晶體，以達成低功率及通道長度微縮。
已將諸多技術描述為多個各別操作，以輔助瞭解諸多實施例。不應將描述之順序視為暗指此些操作必須與依順序。當然，此些操作無需依呈現的順序來進行。所述操作可依不同於所述實施例之順序來進行。可實施諸多額外操作，及/或可在額外實施例中省略所述操作。
本文所使用之「基板」或「目標基板」總體上意指將根據本申請處理之一物件。該基板可包含一元件(尤其是半導體或其他電子元件)之任何材料部分或結構，且可例如為一基礎基板結構，例如半導體晶圓、光罩、或基礎基板結構上或覆蓋基礎基板結構之一層(例如薄膜)。因此，基板並不限於任何特定基礎結構、底層或上覆層、圖案化或未圖案化，反而可考慮包含任何此等層或基礎結構、以及層及/或基礎結構之任何組合。該描述可參考特定類型之基板，但此僅為了說明目的。
本領域中熟悉技藝者亦將瞭解，可對以上解說之技術的操作進行眾多變化，而仍將達成相同目的。此等變化意欲由本發明之範疇所涵蓋。如此，實施例之以上描述並非用於限制。反而，對實施例之任何限制將呈現於以下請求項中。
D:汲極 S:源極 GND:接地 Vdd:電源電壓 N+S/D:N+源極/汲極 P+S/D:P+源極/汲極 NMOS TFET:N型金屬-氧化物-半導體穿隧場效電晶體 PMOS TFET:P型金屬-氧化物-半導體穿隧場效電晶體 NFET:N型場效電晶體 PFET:P型場效電晶體 TFET:穿隧場效電晶體
鑒於非限定方式給出之描述並結合隨附圖式，將更好地理解本申請，其中：
圖1示出兩個電荷捕捉TFET堆疊之剖面示意圖。
圖2示出圖1之兩個電荷捕捉TFET堆疊在垂直於元件之方向上的剖面，其示出被包含有電荷捕捉層之複數介電層所圍繞之奈米通道。
圖3示出用於電荷捕捉之三層介電層堆疊中的介電質列表。
圖4示出用於電荷捕捉之兩層介電層堆疊中的介電質列表。
圖5示出用於電荷捕捉之單層介電層堆疊中的介電質列表。
圖6示出電荷捕捉TFET閘極氧化物區域之剖面示意圖，其示出通道及三個相鄰之介電區域。
圖7示出兩個電荷捕捉TFET堆疊之剖面示意圖。
圖8示出用作反相器之兩個電荷捕捉TFET堆疊之剖面示意圖。
圖9示出用作反相器之兩個電荷捕捉TFET堆疊之剖面示意圖，其中金屬閘極在處理期間一起沉積。
圖10-21示出製造TFET元件並排堆疊之不同步驟。
圖22示出電荷捕捉TFET陣列之示意圖。
D:汲極
S:源極
N+S/D:N+源極/汲極
P+S/D:P+源極/汲極
NMOS TFET:N型金屬-氧化物-半導體穿隧場效電晶體
PMOS TFET:P型金屬-氧化物-半導體穿隧場效電晶體

Claims (20)

  1. 一種半導體元件，包括： 一穿隧場效電晶體(TFET)堆疊，其形成於一基板上，該堆疊垂直於該基板之一表面延伸，該TFET堆疊中之每一TFET包括一奈米通道，其連接每一TFET之一第一側上的一源極/汲極區域與每一TFET之一相反側上的另一源極/汲極區域，其中至少一介電層形成於該奈米通道周圍，該至少一介電層形成一電荷捕捉層。
  2. 如請求項1所述之半導體元件，其中： 該至少一介電層包括形成於該奈米通道周圍之一第一氧化物層、形成於該第一氧化物層周圍之一高介電常數(k)介電層、以及形成於該高k介電層周圍之一第二氧化物層。
  3. 如請求項1所述之半導體元件，其中： 該至少一介電層包括形成於該奈米通道周圍之一第一氧化物層、以及形成於該第一氧化物層周圍之一高介電常數(k)介電層。
  4. 如請求項1所述之半導體元件，其中： 該至少一介電層包括形成於該奈米通道周圍之一高介電常數(k)介電層。
  5. 如請求項1所述之半導體元件，進一步包括： 一金屬閘電極堆疊，其於垂直該基板之該表面之一方向上形成於兩相鄰TFET之間，該金屬閘電極堆疊連接該TEFT之該一源極/汲極區域與該TFET之該相反側上的該另一源極/汲極區域。
  6. 如請求項5所述之半導體元件，其中： 該金屬閘電極堆疊包括TiN、TaN、TiON及TiC層。
  7. 如請求項1所述之半導體元件，其中： 該奈米通道包括Si或SiGe。
  8. 如請求項2所述之半導體元件，其中： 該至少一介電層之厚度具有0.9 nm的最小值及3.5 nm的最大值。
  9. 如請求項2所述之半導體元件，其中： 該高k介電層為HfO2 。
  10. 如請求項3所述之半導體元件，其中： 該高k介電層為HfO2 。
  11. 如請求項4所述之半導體元件，其中： 該高k介電層為HfO2 。
  12. 一種半導體電荷捕捉穿隧場效電晶體(TFET)元件，包括： 一n型金屬氧化物半導體TFET(NMOS TFET)元件，其形成於一基板上，該NMOS TFET元件包括一奈米通道，其連接該NMOS TFET元件之源極/汲極區域，其中至少一介電層形成於該奈米通道周圍，該至少一介電層形成一電荷捕捉層；以及 一p型金屬氧化物半導體TFET(PMOS TFET)元件，其形成於該基板上，並設置於該NMOS TFET元件正上方，至少一間隔物將該NMOS TFET元件與該PMOS TFET元件分隔開，該PMOS TFET元件包括一奈米通道，其連接該PMOS TFET元件之源極/汲極區域，其中至少一介電層形成於該奈米通道周圍，該至少一介電層形成一電荷捕捉層，其中： 該PMOS TFET之該汲極區域連接至該NMOS TFET之該源極區域，且對該NMOS TFET與該PMOS TFET之該等源極與汲極區域，以及對該NMOS TFET與該PMOS TFET之閘電極分開提供金屬連接。
  13. 如請求項12所述之半導體電荷捕捉穿隧場效電晶體半導體元件，其中： 該NMOS TFET與該PMOS TFET之該等閘電極係透過一金屬帶加以連接，該PMOS TFET之該汲極與該NMOS TFET之該源極加以連接以提供一輸出電壓，且該PMOS TFET之該源極係連接至一正供應電壓Vdd，因而構成一反相器元件。
  14. 如請求項12所述之半導體電荷捕捉穿隧場效電晶體半導體元件，其中： 該NMOS TFET與該PMOS TFET之該等閘電極在無金屬帶的情況下加以連接，該PMOS TFET之該汲極與該NMOS TFET之該源極加以連接以提供一輸出電壓，且該PMOS TFET之該源極係連接至一正供應電壓Vdd，因而構成一反相器元件。
  15. 如請求項12所述之半導體電荷捕捉穿隧場效電晶體半導體元件，其中： 該至少一介電層包括一高介電常數(k)介電層，其形成於該奈米通道周圍。
  16. 一種半導體元件，包括： 一第一FET(場效電晶體)元件，其形成於一基板上，該第一FET元件包括至少一奈米通道，其連接該第一FET元件之源極/汲極區域； 一第二FET元件，其形成於該基板上並鄰近於該第一FET元件，該第二FET元件包括至少一奈米通道，其連接該第二FET元件之源極/汲極區域，其中該第二FET元件之一源極/汲極區域與該第一FET元件之一源極/汲極區域共享； 一第三FET元件，其形成於該基板上並鄰近於該第二FET元件，該第三FET元件包括至少一奈米通道，其連接該第三FET元件之源極/汲極區域，其中該第三FET元件之一源極/汲極區域與該第二FET元件之一源極/汲極區域共享，其中： 該半導體元件被摻雜，使得該第一FET元件形成一p通道FET，該第二FET形成一穿隧FET，且該第三FET形成一n通道FET，以及 介電質之至少一電荷捕捉層形成於該第一FET、該第二FET及該第三FET中之該至少一奈米通道周圍。
  17. 一種半導體電荷捕捉穿隧場效電晶體(TFET)元件，包括： 一p型金屬氧化物半導體TFET(PMOS TFET)元件，其形成於一基板上，該PMOS TFET元件包括一奈米通道，其連接該PMOS TFET元件之源極/汲極區域，其中至少一介電層形成於該奈米通道周圍，該至少一介電層形成一電荷捕捉層；以及 一n型金屬氧化物半導體TFET(NMOS TFET)元件，其形成於該基板上，並設置於該PMOS TFET元件正上方，至少一間隔物分開該NMOS TFET元件與該PMOS TFET元件，該NMOS TFET元件包括一奈米通道，其連接該NMOS TFET元件之源極/汲極區域，其中至少一介電層形成於該奈米通道周圍，該至少一介電層形成一電荷捕捉層，且其中： 該NMOS TFET元件之該汲極區域係連接至該PMOS TFET元件之該源極區域，且對該PMOS TFET與該NMOS TFET元件之該等源極與汲極區域，以及對該PMOS TFET與該NMOS TFET元件之閘電極分開提供金屬連接。
  18. 如請求項17所述之半導體電荷捕捉穿隧場效電晶體元件，其中： 該PMOS TFET與該NMOS TFET元件之該等閘電極係透過一金屬帶加以連接，該NMOS TFET元件之汲極與該PMOS TFET元件之源極連接以提供一輸出電壓，且該NMOS TFET元件之該源極連接至一正供應電壓Vdd，因而構成一反相器元件。
  19. 如請求項17所述之半導體電荷捕捉穿隧場效電晶體元件，其中： 該PMOS TFET與該NMOS TFET元件之該等閘電極在無金屬帶的情況下加以連接，該NMOS TFET元件之汲極係與該PMOS TFET元件之源極連接以提供一輸出電壓，且該NMOS TFET元件之該源極係連接至一正供應電壓Vdd，因而構成一反相器元件。
  20. 如請求項17所述之半導體電荷捕捉穿隧場效電晶體元件，其中： 該至少一介電層包括一高介電常數(k)介電層，其形成於該奈米通道周圍。
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