JP4444995B2 - 基板配線用導電性組成物、回路基板及び電子デバイス - Google Patents

基板配線用導電性組成物、回路基板及び電子デバイス Download PDF

Info

Publication number
JP4444995B2
JP4444995B2 JP2007209696A JP2007209696A JP4444995B2 JP 4444995 B2 JP4444995 B2 JP 4444995B2 JP 2007209696 A JP2007209696 A JP 2007209696A JP 2007209696 A JP2007209696 A JP 2007209696A JP 4444995 B2 JP4444995 B2 JP 4444995B2
Authority
JP
Japan
Prior art keywords
circuit board
circuit
electrode
circuit pattern
conductive composition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2007209696A
Other languages
English (en)
Japanese (ja)
Other versions
JP2009044065A (ja
JP2009044065A5 (enExample
Inventor
重信 関根
由莉奈 関根
良治 桑名
Original Assignee
有限会社ナプラ
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 有限会社ナプラ filed Critical 有限会社ナプラ
Priority to JP2007209696A priority Critical patent/JP4444995B2/ja
Priority to US12/180,831 priority patent/US7910837B2/en
Publication of JP2009044065A publication Critical patent/JP2009044065A/ja
Publication of JP2009044065A5 publication Critical patent/JP2009044065A5/ja
Application granted granted Critical
Publication of JP4444995B2 publication Critical patent/JP4444995B2/ja
Priority to US13/017,544 priority patent/US8217280B2/en
Priority to US13/017,590 priority patent/US8609999B2/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Electric Cables (AREA)
JP2007209696A 2007-08-10 2007-08-10 基板配線用導電性組成物、回路基板及び電子デバイス Expired - Fee Related JP4444995B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP2007209696A JP4444995B2 (ja) 2007-08-10 2007-08-10 基板配線用導電性組成物、回路基板及び電子デバイス
US12/180,831 US7910837B2 (en) 2007-08-10 2008-07-28 Circuit board, electronic device and method for manufacturing the same
US13/017,544 US8217280B2 (en) 2007-08-10 2011-01-31 Circuit board, electronic device and method for manufacturing the same
US13/017,590 US8609999B2 (en) 2007-08-10 2011-01-31 Circuit board, electronic device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2007209696A JP4444995B2 (ja) 2007-08-10 2007-08-10 基板配線用導電性組成物、回路基板及び電子デバイス

Publications (3)

Publication Number Publication Date
JP2009044065A JP2009044065A (ja) 2009-02-26
JP2009044065A5 JP2009044065A5 (enExample) 2009-09-17
JP4444995B2 true JP4444995B2 (ja) 2010-03-31

Family

ID=40444454

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2007209696A Expired - Fee Related JP4444995B2 (ja) 2007-08-10 2007-08-10 基板配線用導電性組成物、回路基板及び電子デバイス

Country Status (1)

Country Link
JP (1) JP4444995B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102598879A (zh) * 2009-10-23 2012-07-18 株式会社藤仓 器件安装结构以及器件安装方法
EP2493273A4 (en) * 2009-10-23 2013-10-16 Fujikura Ltd MOUNTING SUPPORT AND ASSEMBLY PROCESS FOR ONE DEVICE
US20140254120A1 (en) * 2009-10-23 2014-09-11 Fujikura Ltd. Device packaging structure and device packaging method
JP4637966B1 (ja) * 2010-02-15 2011-02-23 有限会社ナプラ 電子デバイスの製造方法
US9704793B2 (en) 2011-01-04 2017-07-11 Napra Co., Ltd. Substrate for electronic device and electronic device
JP5667467B2 (ja) * 2011-02-18 2015-02-12 有限会社 ナプラ 合金材料、回路基板、電子デバイス及びその製造方法
CN104332447A (zh) * 2013-07-22 2015-02-04 赛方塊股份有限公司 电极的构造,构成材料及其制造方法
US20220395935A1 (en) * 2019-09-11 2022-12-15 Shinryo Corporation Sn-bi-in-based low melting-point joining member, production method therefor, semiconductor electronic circuit, and mounting method therefor

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW369451B (en) * 1996-05-10 1999-09-11 Ford Motor Co Solder composition and method of using to interconnect electronic components to circuits on thermoplastic substrates
JP3761678B2 (ja) * 1997-07-17 2006-03-29 松下電器産業株式会社 錫含有鉛フリーはんだ合金及びそのクリームはんだ並びにその製造方法
JP4468081B2 (ja) * 2004-06-10 2010-05-26 三菱樹脂株式会社 多層配線基板用導電性ペースト組成物
JP4936352B2 (ja) * 2005-09-02 2012-05-23 有限会社 ナプラ 多層回路基板又はウエハーに設けられた貫通孔又は非貫通孔に充填材を充填する方法

Also Published As

Publication number Publication date
JP2009044065A (ja) 2009-02-26

Similar Documents

Publication Publication Date Title
JP4444995B2 (ja) 基板配線用導電性組成物、回路基板及び電子デバイス
JP3849573B2 (ja) 電子装置
JP4800606B2 (ja) 素子内蔵基板の製造方法
US9049807B2 (en) Processes of making pad-less interconnect for electrical coreless substrate
US20080296056A1 (en) Printed circuit board, production method therefor, electronic-component carrier board using printed circuit board, and production method therefor
TW200904278A (en) Circuitized substrate assembly with internal stacked semiconductor chips, method of making same, electrical assembly utilizing same and information handling system utilizing same
JP2014131037A (ja) 回路基板及びその製造方法
WO2004006331A1 (ja) 多層配線回路モジュール及びその製造方法
JP2005045013A (ja) 回路モジュールとその製造方法
JP2003163323A (ja) 回路モジュール及びその製造方法
JP2005286112A (ja) プリント配線板及びその製造方法
US8058723B2 (en) Package structure in which coreless substrate has direct electrical connections to semiconductor chip and manufacturing method thereof
JP2008085089A (ja) 樹脂配線基板および半導体装置
JP3691995B2 (ja) 半導体パッケージ及びその製造方法並びに半導体装置
JP2016072433A (ja) 貫通電極基板及びその製造方法
JP4386458B2 (ja) 回路基板、電子デバイス及びそれらの製造方法
JP4608297B2 (ja) 積層配線基板の製造方法
CN118234121A (zh) 印刷电路板
KR20140114932A (ko) 복합기판을 이용한 패키지 및 그 제조방법
JP4580027B1 (ja) 回路基板及び電子デバイス
US8546186B2 (en) Planar interconnect structure for hybrid circuits
JP4443349B2 (ja) 多層配線基板の製造方法
JP4570051B2 (ja) 回路基板、電子デバイス及びその製造
TWI361483B (en) Aluminum oxide-based substrate and method for manufacturing the same
JPH0831976A (ja) シリコン両面実装基板及びその製造方法

Legal Events

Date Code Title Description
RD04 Notification of resignation of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7424

Effective date: 20090220

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090731

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20090731

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20090731

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20090904

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090909

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20091002

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20100106

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100114

R150 Certificate of patent or registration of utility model

Ref document number: 4444995

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130122

Year of fee payment: 3

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20100713

A072 Dismissal of procedure [no reply to invitation to correct request for examination]

Free format text: JAPANESE INTERMEDIATE CODE: A072

Effective date: 20101201

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees