JP4439935B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP4439935B2
JP4439935B2 JP2004025581A JP2004025581A JP4439935B2 JP 4439935 B2 JP4439935 B2 JP 4439935B2 JP 2004025581 A JP2004025581 A JP 2004025581A JP 2004025581 A JP2004025581 A JP 2004025581A JP 4439935 B2 JP4439935 B2 JP 4439935B2
Authority
JP
Japan
Prior art keywords
layer
semiconductor device
manufacturing
convex portion
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004025581A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005217365A (ja
JP2005217365A5 (https=
Inventor
泰宏 堂前
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Semiconductor Co Ltd filed Critical Oki Semiconductor Co Ltd
Priority to JP2004025581A priority Critical patent/JP4439935B2/ja
Priority to US10/942,828 priority patent/US7238592B2/en
Publication of JP2005217365A publication Critical patent/JP2005217365A/ja
Publication of JP2005217365A5 publication Critical patent/JP2005217365A5/ja
Application granted granted Critical
Publication of JP4439935B2 publication Critical patent/JP4439935B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H10W46/503—Located in scribe lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2004025581A 2004-02-02 2004-02-02 半導体装置の製造方法 Expired - Fee Related JP4439935B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004025581A JP4439935B2 (ja) 2004-02-02 2004-02-02 半導体装置の製造方法
US10/942,828 US7238592B2 (en) 2004-02-02 2004-09-17 Method of manufacturing a semiconductor device having an alignment mark

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004025581A JP4439935B2 (ja) 2004-02-02 2004-02-02 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2005217365A JP2005217365A (ja) 2005-08-11
JP2005217365A5 JP2005217365A5 (https=) 2006-10-05
JP4439935B2 true JP4439935B2 (ja) 2010-03-24

Family

ID=34805805

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004025581A Expired - Fee Related JP4439935B2 (ja) 2004-02-02 2004-02-02 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US7238592B2 (https=)
JP (1) JP4439935B2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007053255A (ja) * 2005-08-18 2007-03-01 Oki Electric Ind Co Ltd アライメントマークの形成方法
KR100630768B1 (ko) 2005-09-26 2006-10-04 삼성전자주식회사 캡핑층을 구비한 얼라인먼트 키 형성방법 및 이를 이용한반도체 장치의 제조방법
US9000525B2 (en) 2010-05-19 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for alignment marks
US9165889B2 (en) * 2013-06-28 2015-10-20 Infineon Technologies Ag Alignment mark definer
CN106783803B (zh) * 2016-11-30 2019-01-25 武汉新芯集成电路制造有限公司 一种减少光刻标记图形损失的方法和半导体结构

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62128118A (ja) 1985-11-29 1987-06-10 Nec Corp 半導体装置
JP2660405B2 (ja) 1987-06-10 1997-10-08 三菱電機株式会社 マスクアライメント方法
JP3174786B2 (ja) * 1991-05-31 2001-06-11 富士通株式会社 半導体装置の製造方法
US6307273B1 (en) * 1996-06-07 2001-10-23 Vanguard International Semiconductor Corporation High contrast, low noise alignment mark for laser trimming of redundant memory arrays
JP3447231B2 (ja) 1998-11-20 2003-09-16 セイコーインスツルメンツ株式会社 半導体集積回路の製造方法
JP2001307999A (ja) 2000-04-27 2001-11-02 Oki Electric Ind Co Ltd アライメントマークの構造およびその製造方法
JP3665275B2 (ja) 2001-05-28 2005-06-29 沖電気工業株式会社 位置合わせマークの形成方法
JP2003100861A (ja) * 2001-09-20 2003-04-04 Mitsubishi Electric Corp 半導体装置の製造方法
JP2003332270A (ja) * 2002-05-15 2003-11-21 Renesas Technology Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2005217365A (ja) 2005-08-11
US7238592B2 (en) 2007-07-03
US20050170615A1 (en) 2005-08-04

Similar Documents

Publication Publication Date Title
JP4537124B2 (ja) オーバーレイキー、アラインキーを有する集積回路半導体素子およびその製造方法
US9188883B2 (en) Alignment mark
JP4843304B2 (ja) フォトマスクの製造方法、デバイスの製造方法、及び、フォトマスクのモニタ方法
US20080146017A1 (en) Method for manufacturing semiconductor device
US6809002B2 (en) Method of manufacturing an alignment mark
JP4439935B2 (ja) 半導体装置の製造方法
JP4397248B2 (ja) 半導体装置及びその製造方法
JP2001307999A (ja) アライメントマークの構造およびその製造方法
US7611961B2 (en) Method for fabricating semiconductor wafer with enhanced alignment performance
JP4450743B2 (ja) フォトマスク、フォトマスクの製造方法及び半導体装置の製造方法
WO1999008314A1 (en) Semiconductor integrated circuit device and method of fabrication thereof
JP2001052993A (ja) 半導体装置及び半導体装置の製造方法
CN116759298A (zh) 一种形成光刻对准标记的方法和半导体器件
JP2004273612A (ja) 半導体装置及びその製造方法、フォトマスク
JP4794377B2 (ja) 半導体装置の製造方法
JP2009218379A (ja) 半導体装置の製造方法
JP2975871B2 (ja) 合わせマークの位置ずれ検査方法
US8043770B2 (en) Photomask and method of forming overlay vernier of semiconductor device using the same
JP4998665B2 (ja) 半導体装置の製造方法
KR20060076498A (ko) 반도체 소자의 소자 분리막 형성 방법
JP2007053255A (ja) アライメントマークの形成方法
JP2004319637A (ja) アライメントマークの形成方法およびそれを用いた半導体装置の製造方法
KR20080039037A (ko) 반도체 소자의 제조 방법
KR20060114434A (ko) 반도체소자의 제조방법
KR20050033682A (ko) 웨이퍼 정렬키 형성방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060822

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20060822

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A712

Effective date: 20081126

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7423

Effective date: 20090204

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20090226

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20090310

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090508

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20091215

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20100106

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130115

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

LAPS Cancellation because of no payment of annual fees