JP4437113B2 - 積層型キャパシターアレイ及びその配線接続構造 - Google Patents
積層型キャパシターアレイ及びその配線接続構造 Download PDFInfo
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Description
21 キャパシター本体
21a 第1誘電体層
21b 第2誘電体層
21c 第3誘電体層
21d 第4誘電体層
21e 第5誘電体層
22a、22b 第2内部電極
23a、23b 第1内部電極
24a、24b 第2導電性ビアホール
25 第1導電性ビアホール
26a,26b 第2外部端子
27 第1外部端子
50 積層型キャパシターアレイ50
51 キャパシター本体
52a,52b 第2内部電極
53a、53b 第1内部電極
54a 第2導電性ビアホール
54b 第2導電性ビアホール
55 第1導電性ビアホール
56a、56b 第2外部端子
57 第1外部端子57
60 積層型キャパシターアレイ
61 キャパシター本体
64a、64b、64c 第2導電性ビアホール
65 第1導電性ビアホール
66a、66b、66c 第2外部端子
67 第1外部端子
80 積層型キャパシターアレイパッケージ
81 配線基板
82a、82b ソケット構造
83a、83b、84a、84b、84c、87a、87b、87c、88a、88b、88c 内部回路構造
84c、87c、88c 内部回路
85 マイクロプロセシングユニット(MPU)
86 端子
91 母基板
100 配線接続構造100
110 積層型キャパシターアレイパッケージ
111 配線基板
115 マイクロプロセシングユニット(MPU)
116 端子
117a、117b、117c 垂直接続構造
121 母基板
130 配線接続構造
C キャビティ領域
GND 接地ライン
PWL1 第1電源供給ライン
PWL2 第2電源供給ライン
S ソルダリング
Claims (16)
- 複数個の誘電体層が積層され形成されたキャパシター本体;
上記複数個の誘電体層上に各々形成され、一誘電体層を間に挟んで対向するよう交代に配置された複数組の第1及び第2内部電極;
上記キャパシター本体の上面及び下面中少なくとも一面に形成された少なくとも一つの第1外部端子と複数個の第2外部端子;及び、
上記キャパシター本体の積層方向に形成され上記第1外部端子と上記第2外部端子に各々連結された少なくとも一つの第1導電性ビアホールと複数個の第2導電性ビアホールを含み、
上記少なくとも一つの第1導電性ビアホールは上記第1内部電極に接続され、上記第2内部電極とは電気的に絶縁され、
上記複数個の第2導電性ビアホールは少なくとも一つの第2導電性ビアホールを含むk個(k≧2)のグループに区分され、上記第2内部電極は少なくとも一つの第2内部電極を含むk個のグループに区分され、上記各グループの第2導電性ビアホールは上記各グループの第2内部電極に接続され他のグループの第2内部電極及び上記第1内部電極とは電気的に絶縁されることを特徴とする積層型キャパシターアレイ。 - 上記第1及び第2導電性ビアホールは各々に連結された内部電極に流れる電流により誘導される磁界が相互相殺されるよう配置されたことを特徴とする請求項1に記載の積層型キャパシターアレイ。
- 上記第1導電性ビアホールに隣接した各グループの第2導電性ビアホールは上記第1導電性ビアホールと同一間隔で配列されたことを特徴とする請求項2に記載の積層型キャパシターアレイ。
- 上記第1導電性ビアホールは複数個であることを特徴とする請求項1に記載の積層型キャパシターアレイ。
- 上記第1及び第2導電性ビアホールは四角形の各コーナー位置に配列されたことを特徴とする請求項4に記載の積層型キャパシターアレイ。
- 上記第1導電性ビアホールは上記コーナー中対角線方向に対向する両コーナーに配置され、
他のグループの第2導電性ビアホールが各々残り両コーナーに配列されたことを特徴とする請求項5に記載の積層型キャパシターアレイ。 - 少なくとも一つのグループの第2導電性ビアホールの数は他のグループの第2導電性ビアホールの数と異なることを特徴とする請求項1に記載の積層型キャパシターアレイ。
- 上記各グループの第2内部電極は、2つ以上のグループに属した第2導電型ビアホールに重複して連結されたことを特徴とする請求項1に記載の積層型キャパシターアレイ。
- 上記各グループの第2内部電極は、2つ以上のグループに属した第2導電型ビアホールに重複して連結されていないことを特徴とする請求項1に記載の積層型キャパシターアレイ。
- 上記各グループの第2内部電極は同一数であることを特徴とする請求項1に記載の積層型キャパシターアレイ。
- 上記少なくとも一つのグループの第2内部電極の数は他のグループの第2内部電極の数と異なることを特徴とする請求項1に記載の積層型キャパシターアレイ。
- 少なくとも2個の電源供給ラインと接地ラインが具備された母基板;及び、
上記母基板に実装され、マイクロプロセシングユニット(MPU)チップが具備された配線基板と上記配線基板の下部に装着された積層型キャパシターアレイを含む積層型キャパシターアレイパッケージを含み、
上記積層型キャパシターアレイは、
複数個の誘電体層が積層され形成されたキャパシター本体と、上記複数の誘電体層上に各々形成され、一誘電体層を間に挟んで対向するよう交代に配置された複数組の第1及び第2内部電極と、上記キャパシター本体の上面及び下面中少なくとも一面に形成された複数の第1及び第2外部端子と、上記キャパシター本体の積層方向に形成され上記第1及び上記第2外部端子に各々連結された複数の第1及び第2導電性ビアホールを含み、上記複数個の第1導電性ビアホールは上記第1内部電極に接続され、上記第2内部電極とは電気的に絶縁され、上記複数個の第2導電性ビアホールは少なくとも一つの第2導電性ビアホールを含むk個(k≧2)のグループに区分され、上記複数個の第2内部電極は少なくとも一つの第2内部電極を含むk個のグループに区分され、上記各グループの第2導電性ビアホールは上記各グループの第2内部電極に接続され他のグループの第2内部電極及び上記第1内部電極とは電気的に絶縁され、
上記接地ラインは上記第1外部端子ラインに連結され、上記少なくとも2個の電源ラインは各々上記k個のグループの第2導電性ビアホールに連結された第2外部端子に各々連結され、
上記少なくとも2個の電源ライン及び接地ライン中少なくとも一つは上記積層型キャパシターの関連第1または第2導電性ビアホールを通じ上記MPUチップに連結されたことを特徴とする積層型キャパシターアレイの配線接続構造。 - 上記少なくとも2個の電源ライン及び接地ライン中少なくとも一つと上記MPUチップを連結する第1または第2導電性ビアホールに関連する第1及び第2外部端子は上記キャパシター本体の上下面全てに形成されたことを特徴とする請求項12に記載の積層型キャパシターアレイの配線接続構造。
- 上記印刷回路基板の少なくとも2個の電源ラインは各々上記k個グループの第2導電性ビアホールを通じ上記MPUチップに連結されたことを特徴とする請求項12に記載の積層型キャパシターアレイの配線接続構造。
- 上記印刷回路基板の接地ラインは上記第1導電性ビアホールを通じ上記MPUチップに連結されたことを特徴とする請求項14に記載の積層型キャパシターアレイの配線接続構造。
- 上記積層型キャパシターアレイの第1及び第2外部端子の配列と間隔は上記MPUチップ端子の配列及び間隔と同一であることを特徴とする請求項12に記載の積層型キャパシターアレイの配線接続構造。
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Application Number | Priority Date | Filing Date | Title |
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KR1020040089314A KR100674830B1 (ko) | 2004-11-04 | 2004-11-04 | 적층형 캐패시터 어레이 |
KR1020040102609A KR100674823B1 (ko) | 2004-12-07 | 2004-12-07 | 적층형 캐패시터 어레이의 배선접속구조 |
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JP2006135333A JP2006135333A (ja) | 2006-05-25 |
JP4437113B2 true JP4437113B2 (ja) | 2010-03-24 |
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JP5029299B2 (ja) * | 2007-11-08 | 2012-09-19 | 富士通株式会社 | キャパシタ及びキャパシタを含む半導体装置、及びキャパシタの製造方法 |
US20090296310A1 (en) * | 2008-06-03 | 2009-12-03 | Azuma Chikara | Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors |
US8183678B2 (en) * | 2009-08-04 | 2012-05-22 | Amkor Technology Korea, Inc. | Semiconductor device having an interposer |
US8699204B2 (en) * | 2010-02-23 | 2014-04-15 | Avx Corporation | Element array and footprint layout for element array |
US8760847B2 (en) | 2010-11-30 | 2014-06-24 | Pratt & Whitney Canada Corp. | Low inductance capacitor assembly |
EP2670212B1 (en) | 2012-06-01 | 2016-03-09 | Electrolux Home Products Corporation N.V. | A half bridge induction heating generator and a capacitor assembly for a half bridge induction heating generator |
AU2013309044A1 (en) | 2012-08-30 | 2015-02-05 | Allison Transmission, Inc. | Method and system for reducing audible and/or electrical noise from electrically or mechanically excited capacitors |
US9299498B2 (en) * | 2012-11-15 | 2016-03-29 | Eulex Corp. | Miniature wire-bondable capacitor |
EP2819166B1 (en) * | 2013-06-26 | 2018-03-14 | Nexperia B.V. | Electric field gap device and manufacturing method |
CN103532554B (zh) * | 2013-10-23 | 2016-04-27 | 中国电子科技集团公司第二十四研究所 | 电容阵列及其版图设计方法 |
US9093295B2 (en) * | 2013-11-13 | 2015-07-28 | Qualcomm Incorporated | Embedded sheet capacitor |
US10229789B2 (en) * | 2016-10-28 | 2019-03-12 | Samsung Electro-Mechanics Co., Ltd. | Multilayer thin-film capacitor |
KR102391585B1 (ko) * | 2017-08-25 | 2022-04-28 | 삼성전기주식회사 | 커패시터 부품 |
JP7103835B2 (ja) * | 2018-04-24 | 2022-07-20 | 太陽誘電株式会社 | 積層セラミック電子部品及びその製造方法、並びに回路基板 |
CN116075913A (zh) * | 2020-08-12 | 2023-05-05 | 株式会社村田制作所 | 多端子层叠电容器 |
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US5880925A (en) | 1997-06-27 | 1999-03-09 | Avx Corporation | Surface mount multilayer capacitor |
US6034864A (en) * | 1997-11-14 | 2000-03-07 | Murata Manufacturing Co., Ltd. | Multilayer capacitor |
JP3489728B2 (ja) | 1999-10-18 | 2004-01-26 | 株式会社村田製作所 | 積層コンデンサ、配線基板および高周波回路 |
JP3489729B2 (ja) | 1999-11-19 | 2004-01-26 | 株式会社村田製作所 | 積層コンデンサ、配線基板、デカップリング回路および高周波回路 |
US6801422B2 (en) * | 1999-12-28 | 2004-10-05 | Intel Corporation | High performance capacitor |
JP2001189234A (ja) * | 1999-12-28 | 2001-07-10 | Tdk Corp | 積層コンデンサ |
US6532143B2 (en) | 2000-12-29 | 2003-03-11 | Intel Corporation | Multiple tier array capacitor |
US6606237B1 (en) * | 2002-06-27 | 2003-08-12 | Murata Manufacturing Co., Ltd. | Multilayer capacitor, wiring board, decoupling circuit, and high frequency circuit incorporating the same |
JP4548571B2 (ja) * | 2002-10-08 | 2010-09-22 | 日本特殊陶業株式会社 | 積層コンデンサの製造方法 |
JP4458812B2 (ja) * | 2002-10-30 | 2010-04-28 | 京セラ株式会社 | コンデンサ、コンデンサの製造方法、配線基板、デカップリング回路及び高周波回路 |
JP2004153043A (ja) * | 2002-10-31 | 2004-05-27 | Ngk Spark Plug Co Ltd | 積層セラミックコンデンサ及びその製造方法 |
US6891258B1 (en) * | 2002-12-06 | 2005-05-10 | Xilinx, Inc. | Interposer providing low-inductance decoupling capacitance for a packaged integrated circuit |
-
2005
- 2005-11-01 US US11/264,486 patent/US7149072B2/en not_active Expired - Fee Related
- 2005-11-04 JP JP2005321344A patent/JP4437113B2/ja not_active Expired - Fee Related
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US7149072B2 (en) | 2006-12-12 |
US20060092595A1 (en) | 2006-05-04 |
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