JP4434845B2 - 半導体モジュールとその製造方法および半導体装置 - Google Patents
半導体モジュールとその製造方法および半導体装置 Download PDFInfo
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- JP4434845B2 JP4434845B2 JP2004169600A JP2004169600A JP4434845B2 JP 4434845 B2 JP4434845 B2 JP 4434845B2 JP 2004169600 A JP2004169600 A JP 2004169600A JP 2004169600 A JP2004169600 A JP 2004169600A JP 4434845 B2 JP4434845 B2 JP 4434845B2
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- resin film
- insulating resin
- semiconductor module
- film
- solder resist
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Description
本発明の半導体モジュールの製造方法は、回路素子を固定した状態で、絶縁樹脂膜および導電性膜の積層体を配置し、前記回路素子を前記絶縁樹脂膜内に埋め込む工程と、圧着により前記回路素子を前記絶縁樹脂膜内に固定する工程と、前記回路素子を埋め込まれた絶縁樹脂膜より上層にソルダーレジスト層を形成する工程と、を含み、前記ソルダーレジスト層はカルド型ポリマーを含むことを特徴とする。
さらに本発明の半導体モジュールの製造方法は、表面に凹部を備える膜を形成する工程と、前記凹部の内部に埋込材料を埋め込み、前記凹部の内部に前記回路素子の一部または全部を構成する埋込部材を形成する工程と、を含んでもよい。
(i)−CO−A1−CO−
(但しA1は、芳香環を含有する2価の結合基を示す。)
(ii)−O−A2−O−
(但しA2は、芳香環を含有する2価の結合基を示す。)
(iii)−CO−A3−O−
(但しA3は、芳香環を含有する2価の結合基を示す。)
図2は、本発明の実施の形態における回路装置の製造工程の後半部分を示す断面図である。
次いで、図2(j)に示すように、ガラスをマスクとして露光することでパターニングした後、フォトソルダーレジスト層220をマスクとして、たとえば、薬液による化学エッチング加工によって、ビアホールを形成し、めっき工程、配線形成工程を繰り返して、3層配線形成工程を行う。そして、最上層の上部に形成された導電性膜126上に、半田印刷法などにより裏面電極として半田電極(ハンダボール)230を形成する半田電極形成工程を行う。
(1)ポリマー主鎖の回転拘束
(2)主鎖及び側鎖のコンフォメーション規制
(3)分子間パッキングの阻害
(4)側鎖の芳香族置換基導入等による芳香族性の増加
といった効果を奏する。
(ISBパッケージへの適用)
このパッケージによれば、以下の利点が得られる。
(i)コアレスで実装できるため、トランジスタ、IC、LSIの小型・薄型化を実現できる。
(ii)トランジスタからシステムLSI、さらにチップタイプのコンデンサや抵抗を回路形成し、パッケージングすることができるため、高度なSIP(System in Package)を実現できる。
(iii)現有の半導体チップを組み合わせできるため、システムLSIを短期間に開発できる。
(iv)半導体ベアチップが直下の銅材に直接マウントされており、良好な放熱性を得ることができる。
(v)回路配線が銅材でありコア材がないため、低誘電率の回路配線となり、高速データ転送や高周波回路で優れた特性を発揮する。
(vi)電極がパッケージの内部に埋め込まれる構造のため、電極材料のパーティクルコンタミの発生を抑制できる。
(vii)パッケージサイズはフリーであり、1個あたりの廃材を64ピンのSQFPパッケージと比較すると、約1/10の量となるため、環境負荷を低減できる。
(viii)部品を載せるプリント回路基板から、機能の入った回路基板へと、新しい概念のシステム構成を実現できる。
(ix)ISBのパターン設計は、プリント回路基板のパターン設計と同じように容易であり、セットメーカーのエンジニアが自ら設計できる。
Claims (8)
- 第1の絶縁樹脂膜と、
前記第1の絶縁樹脂膜に埋め込まれた第1の複数の回路素子と、
前記第1の絶縁樹脂膜より上層に設けられ、埋込材料からなる第2の複数の回路素子を内部に備えた第2の絶縁樹脂膜と、
前記第2の回路素子を覆うように形成されたソルダーレジスト層と、
を含み、
前記第1の複数の回路素子は、前記第1の絶縁樹脂膜に固着され、
前記ソルダーレジスト層は、カルド型ポリマーを含むことを特徴とする半導体モジュール。 - 請求項1に記載の半導体モジュールにおいて、
前記第1の回路素子の一部または全部を構成する一以上の部材のうちいずれかの部材の上部の一面と、前記第1の回路素子間の前記第1の絶縁樹脂膜の上部の一面と、が同一平面を形成し、
前記一以上の部材のうちいずれかの部材の下部の一面と、前記第1の回路素子間の前記第1の絶縁樹脂膜の下部の一面と、が同一平面を形成するように構成されていることを特徴とする半導体モジュール。 - 請求項1または2に記載の半導体モジュールにおいて、
前記ソルダーレジスト層に前記第1の回路素子を接続する配線が設けられていることを特徴とする半導体モジュール。 - 請求項1から3のいずれかに記載の半導体モジュールにおいて、
前記ソルダーレジスト層のガラス転移温度が180℃以上220℃以下であり、
前記ソルダーレジスト層の周波数1MHzの交流電界を印加した場合の誘電正接が0.001以上0.04以下であることを特徴とする半導体モジュール。 - 請求項4に記載の半導体モジュールにおいて、
前記ソルダーレジスト層のガラス転移温度以下の領域における線膨張係数が50ppm/℃以上80ppm/℃以下であることを特徴とする半導体モジュール。 - 第1の回路素子を固定した状態で、第1の絶縁樹脂膜および導電性膜の積層体を配置し、前記第1の回路素子を前記第1の絶縁樹脂膜内に埋め込む工程と、
圧着により前記第1の回路素子を前記第1の絶縁樹脂膜内に固定する工程と、
前記第1の回路素子を埋め込まれた前記第1の絶縁樹脂膜より上層に設けられ、埋込材料からなる第2の複数の回路素子を内部に備えた第2の絶縁樹脂膜と、前記第2の回路素子を覆うように形成されたソルダーレジスト層とを形成する工程と、
を含み、
前記ソルダーレジスト層はカルド型ポリマーを含むことを特徴とする半導体モジュールの製造方法。 - 請求項6に記載の半導体モジュールの製造方法において、
表面に凹部を備える第2の絶縁樹脂膜を形成する工程と、
前記凹部の内部に埋込材料を埋め込み、前記凹部の内部に前記第2の回路素子の一部または全部を構成する埋込部材を形成する工程と、
をさらに含むことを特徴とする半導体モジュールの製造方法。 - 請求項1から5のいずれかに記載の半導体モジュールと、
前記半導体モジュールに搭載されている半導体素子と、
を備えることを特徴とする半導体装置。
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JP2004169600A JP4434845B2 (ja) | 2004-06-08 | 2004-06-08 | 半導体モジュールとその製造方法および半導体装置 |
TW094115866A TWI261862B (en) | 2004-06-08 | 2005-05-17 | Semiconductor module with high manufacture precision, method for making such module, and semiconductor device |
US11/147,778 US7683268B2 (en) | 2004-06-08 | 2005-06-07 | Semiconductor module with high process accuracy, manufacturing method thereof, and semiconductor device therewith |
CNB2005100761554A CN100394599C (zh) | 2004-06-08 | 2005-06-08 | 加工精度良好的半导体模块及其制造方法和半导体装置 |
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- 2005-05-17 TW TW094115866A patent/TWI261862B/zh not_active IP Right Cessation
- 2005-06-07 US US11/147,778 patent/US7683268B2/en not_active Expired - Fee Related
- 2005-06-08 CN CNB2005100761554A patent/CN100394599C/zh not_active Expired - Fee Related
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CN100394599C (zh) | 2008-06-11 |
US7683268B2 (en) | 2010-03-23 |
CN1707792A (zh) | 2005-12-14 |
US20050269128A1 (en) | 2005-12-08 |
TW200601405A (en) | 2006-01-01 |
TWI261862B (en) | 2006-09-11 |
JP2005353644A (ja) | 2005-12-22 |
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