JP4397248B2 - 半導体装置及びその製造方法 - Google Patents

半導体装置及びその製造方法 Download PDF

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Publication number
JP4397248B2
JP4397248B2 JP2004044788A JP2004044788A JP4397248B2 JP 4397248 B2 JP4397248 B2 JP 4397248B2 JP 2004044788 A JP2004044788 A JP 2004044788A JP 2004044788 A JP2004044788 A JP 2004044788A JP 4397248 B2 JP4397248 B2 JP 4397248B2
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JP
Japan
Prior art keywords
formation region
nitride film
film
mark
forming
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Expired - Fee Related
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JP2004044788A
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English (en)
Japanese (ja)
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JP2005236118A (ja
JP2005236118A5 (enExample
Inventor
幸子 矢部
隆 田口
実 渡辺
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Lapis Semiconductor Co Ltd
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Oki Semiconductor Co Ltd
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Publication date
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Priority to JP2004044788A priority Critical patent/JP4397248B2/ja
Priority to US11/048,891 priority patent/US7332405B2/en
Publication of JP2005236118A publication Critical patent/JP2005236118A/ja
Publication of JP2005236118A5 publication Critical patent/JP2005236118A5/ja
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Publication of JP4397248B2 publication Critical patent/JP4397248B2/ja
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    • H10W46/00—
    • H10W46/501—

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  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2004044788A 2004-02-20 2004-02-20 半導体装置及びその製造方法 Expired - Fee Related JP4397248B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004044788A JP4397248B2 (ja) 2004-02-20 2004-02-20 半導体装置及びその製造方法
US11/048,891 US7332405B2 (en) 2004-02-20 2005-02-03 Method of forming alignment marks for semiconductor device fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004044788A JP4397248B2 (ja) 2004-02-20 2004-02-20 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2005236118A JP2005236118A (ja) 2005-09-02
JP2005236118A5 JP2005236118A5 (enExample) 2006-09-28
JP4397248B2 true JP4397248B2 (ja) 2010-01-13

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ID=34858080

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JP2004044788A Expired - Fee Related JP4397248B2 (ja) 2004-02-20 2004-02-20 半導体装置及びその製造方法

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US (1) US7332405B2 (enExample)
JP (1) JP4397248B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7435659B2 (en) * 2005-02-28 2008-10-14 Texas Instruments Incorporated Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process
JP4794377B2 (ja) * 2006-07-06 2011-10-19 Ｏｋｉセミコンダクタ株式会社 半導体装置の製造方法
US7723178B2 (en) * 2008-07-18 2010-05-25 International Business Machines Corporation Shallow and deep trench isolation structures in semiconductor integrated circuits
US9000525B2 (en) 2010-05-19 2015-04-07 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for alignment marks
JP2014216377A (ja) * 2013-04-23 2014-11-17 イビデン株式会社 電子部品とその製造方法及び多層プリント配線板の製造方法
US9178066B2 (en) * 2013-08-30 2015-11-03 Taiwan Semiconductor Manufacturing Company Limited Methods for forming a semiconductor arrangement with structures having different heights
US12347787B2 (en) * 2022-06-13 2025-07-01 Yangtze Memory Technologies Co., Ltd. Three dimensional (3D) memory device and fabrication method
CN119381339B (zh) * 2023-07-20 2025-09-26 长鑫科技集团股份有限公司 半导体结构及其形成方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3174786B2 (ja) * 1991-05-31 2001-06-11 富士通株式会社 半導体装置の製造方法
JP3447231B2 (ja) * 1998-11-20 2003-09-16 セイコーインスツルメンツ株式会社 半導体集積回路の製造方法
WO2001067509A1 (fr) * 2000-03-09 2001-09-13 Fujitsu Limited Dispositif semi-conducteur et procede de fabrication
JP5194328B2 (ja) * 2001-02-01 2013-05-08 ソニー株式会社 半導体装置及びその製造方法
US6656815B2 (en) * 2001-04-04 2003-12-02 International Business Machines Corporation Process for implanting a deep subcollector with self-aligned photo registration marks
JP3665275B2 (ja) * 2001-05-28 2005-06-29 沖電気工業株式会社 位置合わせマークの形成方法
US6635576B1 (en) * 2001-12-03 2003-10-21 Taiwan Semiconductor Manufacturing Company Method of fabricating borderless contact using graded-stair etch stop layers
JP4227341B2 (ja) * 2002-02-21 2009-02-18 セイコーインスツル株式会社 半導体集積回路の構造及びその製造方法
US7105442B2 (en) * 2002-05-22 2006-09-12 Applied Materials, Inc. Ashable layers for reducing critical dimensions of integrated circuit features
US6673635B1 (en) * 2002-06-28 2004-01-06 Advanced Micro Devices, Inc. Method for alignment mark formation for a shallow trench isolation process
US7045837B2 (en) * 2003-01-31 2006-05-16 Infineon Technologies Ag Hardmask with high selectivity for Ir barriers for ferroelectric capacitor manufacturing

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Publication number Publication date
US7332405B2 (en) 2008-02-19
JP2005236118A (ja) 2005-09-02
US20050186756A1 (en) 2005-08-25

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