JP2005236118A5 - - Google Patents
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- Publication number
- JP2005236118A5 JP2005236118A5 JP2004044788A JP2004044788A JP2005236118A5 JP 2005236118 A5 JP2005236118 A5 JP 2005236118A5 JP 2004044788 A JP2004044788 A JP 2004044788A JP 2004044788 A JP2004044788 A JP 2004044788A JP 2005236118 A5 JP2005236118 A5 JP 2005236118A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004044788A JP4397248B2 (ja) | 2004-02-20 | 2004-02-20 | 半導体装置及びその製造方法 |
| US11/048,891 US7332405B2 (en) | 2004-02-20 | 2005-02-03 | Method of forming alignment marks for semiconductor device fabrication |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004044788A JP4397248B2 (ja) | 2004-02-20 | 2004-02-20 | 半導体装置及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2005236118A JP2005236118A (ja) | 2005-09-02 |
| JP2005236118A5 true JP2005236118A5 (enExample) | 2006-09-28 |
| JP4397248B2 JP4397248B2 (ja) | 2010-01-13 |
Family
ID=34858080
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004044788A Expired - Fee Related JP4397248B2 (ja) | 2004-02-20 | 2004-02-20 | 半導体装置及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7332405B2 (enExample) |
| JP (1) | JP4397248B2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7435659B2 (en) * | 2005-02-28 | 2008-10-14 | Texas Instruments Incorporated | Method for manufacturing a semiconductor device having an alignment feature formed using an N-type dopant and a wet oxidation process |
| JP4794377B2 (ja) * | 2006-07-06 | 2011-10-19 | Ｏｋｉセミコンダクタ株式会社 | 半導体装置の製造方法 |
| US7723178B2 (en) * | 2008-07-18 | 2010-05-25 | International Business Machines Corporation | Shallow and deep trench isolation structures in semiconductor integrated circuits |
| US9000525B2 (en) | 2010-05-19 | 2015-04-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for alignment marks |
| JP2014216377A (ja) * | 2013-04-23 | 2014-11-17 | イビデン株式会社 | 電子部品とその製造方法及び多層プリント配線板の製造方法 |
| US9178066B2 (en) * | 2013-08-30 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company Limited | Methods for forming a semiconductor arrangement with structures having different heights |
| US12347787B2 (en) * | 2022-06-13 | 2025-07-01 | Yangtze Memory Technologies Co., Ltd. | Three dimensional (3D) memory device and fabrication method |
| CN119381339B (zh) * | 2023-07-20 | 2025-09-26 | 长鑫科技集团股份有限公司 | 半导体结构及其形成方法 |
Family Cites Families (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3174786B2 (ja) * | 1991-05-31 | 2001-06-11 | 富士通株式会社 | 半導体装置の製造方法 |
| JP3447231B2 (ja) * | 1998-11-20 | 2003-09-16 | セイコーインスツルメンツ株式会社 | 半導体集積回路の製造方法 |
| WO2001067509A1 (fr) * | 2000-03-09 | 2001-09-13 | Fujitsu Limited | Dispositif semi-conducteur et procede de fabrication |
| JP5194328B2 (ja) * | 2001-02-01 | 2013-05-08 | ソニー株式会社 | 半導体装置及びその製造方法 |
| US6656815B2 (en) * | 2001-04-04 | 2003-12-02 | International Business Machines Corporation | Process for implanting a deep subcollector with self-aligned photo registration marks |
| JP3665275B2 (ja) * | 2001-05-28 | 2005-06-29 | 沖電気工業株式会社 | 位置合わせマークの形成方法 |
| US6635576B1 (en) * | 2001-12-03 | 2003-10-21 | Taiwan Semiconductor Manufacturing Company | Method of fabricating borderless contact using graded-stair etch stop layers |
| JP4227341B2 (ja) * | 2002-02-21 | 2009-02-18 | セイコーインスツル株式会社 | 半導体集積回路の構造及びその製造方法 |
| US7105442B2 (en) * | 2002-05-22 | 2006-09-12 | Applied Materials, Inc. | Ashable layers for reducing critical dimensions of integrated circuit features |
| US6673635B1 (en) * | 2002-06-28 | 2004-01-06 | Advanced Micro Devices, Inc. | Method for alignment mark formation for a shallow trench isolation process |
| US7045837B2 (en) * | 2003-01-31 | 2006-05-16 | Infineon Technologies Ag | Hardmask with high selectivity for Ir barriers for ferroelectric capacitor manufacturing |
-
2004
- 2004-02-20 JP JP2004044788A patent/JP4397248B2/ja not_active Expired - Fee Related
-
2005
- 2005-02-03 US US11/048,891 patent/US7332405B2/en not_active Expired - Lifetime