JP4334128B2 - 半導体実装方法および半導体実装装置 - Google Patents

半導体実装方法および半導体実装装置 Download PDF

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Publication number
JP4334128B2
JP4334128B2 JP2000327884A JP2000327884A JP4334128B2 JP 4334128 B2 JP4334128 B2 JP 4334128B2 JP 2000327884 A JP2000327884 A JP 2000327884A JP 2000327884 A JP2000327884 A JP 2000327884A JP 4334128 B2 JP4334128 B2 JP 4334128B2
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JP
Japan
Prior art keywords
semiconductor
position confirmation
circuit board
mounting
confirmation mark
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000327884A
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English (en)
Japanese (ja)
Other versions
JP2002134561A (ja
JP2002134561A5 (enExample
Inventor
良典 酒井
一博 登
真 北畠
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2000327884A priority Critical patent/JP4334128B2/ja
Publication of JP2002134561A publication Critical patent/JP2002134561A/ja
Publication of JP2002134561A5 publication Critical patent/JP2002134561A5/ja
Application granted granted Critical
Publication of JP4334128B2 publication Critical patent/JP4334128B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Wire Bonding (AREA)
JP2000327884A 2000-10-27 2000-10-27 半導体実装方法および半導体実装装置 Expired - Fee Related JP4334128B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2000327884A JP4334128B2 (ja) 2000-10-27 2000-10-27 半導体実装方法および半導体実装装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000327884A JP4334128B2 (ja) 2000-10-27 2000-10-27 半導体実装方法および半導体実装装置

Publications (3)

Publication Number Publication Date
JP2002134561A JP2002134561A (ja) 2002-05-10
JP2002134561A5 JP2002134561A5 (enExample) 2007-04-12
JP4334128B2 true JP4334128B2 (ja) 2009-09-30

Family

ID=18804824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000327884A Expired - Fee Related JP4334128B2 (ja) 2000-10-27 2000-10-27 半導体実装方法および半導体実装装置

Country Status (1)

Country Link
JP (1) JP4334128B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005301056A (ja) * 2004-04-14 2005-10-27 Hitachi Displays Ltd 表示装置とその製造方法
CN100463130C (zh) * 2004-05-20 2009-02-18 威盛电子股份有限公司 倒装芯片封装工艺
TWI299555B (en) * 2006-04-28 2008-08-01 Taiwan Tft Lcd Ass Semiconductor flip-chip package component and fabricating method
TW201018340A (en) * 2008-10-30 2010-05-01 Nan Ya Printed Circuit Board Method for improving yield of solder bumps
JP5191927B2 (ja) * 2009-02-26 2013-05-08 アルプス電気株式会社 Memsセンサ及びその製造方法
JP2012089563A (ja) * 2010-10-15 2012-05-10 Sanken Electric Co Ltd 半導体モジュール
JP2019121704A (ja) * 2018-01-09 2019-07-22 トヨタ自動車株式会社 半導体装置
JP7655141B2 (ja) * 2021-08-05 2025-04-02 住友電気工業株式会社 半導体装置の製造方法
JP7428916B2 (ja) * 2021-12-27 2024-02-07 日亜化学工業株式会社 発光装置の製造方法および発光装置
CN116110805B (zh) * 2023-04-13 2023-07-11 深圳宏芯宇电子股份有限公司 芯片键合方法、结构及存储器

Also Published As

Publication number Publication date
JP2002134561A (ja) 2002-05-10

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