JP4295922B2 - 小型集積回路の作製における用途に適したガス浸漬レーザアニーリング方法 - Google Patents

小型集積回路の作製における用途に適したガス浸漬レーザアニーリング方法 Download PDF

Info

Publication number
JP4295922B2
JP4295922B2 JP2000568107A JP2000568107A JP4295922B2 JP 4295922 B2 JP4295922 B2 JP 4295922B2 JP 2000568107 A JP2000568107 A JP 2000568107A JP 2000568107 A JP2000568107 A JP 2000568107A JP 4295922 B2 JP4295922 B2 JP 4295922B2
Authority
JP
Japan
Prior art keywords
silicon
layer
mosfets
metallic material
depth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000568107A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002524846A (ja
JP2002524846A5 (enExample
Inventor
ソミット タルワー,
カート ウェイナー,
Original Assignee
ウルトラテック ステッパー インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ウルトラテック ステッパー インコーポレイテッド filed Critical ウルトラテック ステッパー インコーポレイテッド
Publication of JP2002524846A publication Critical patent/JP2002524846A/ja
Publication of JP2002524846A5 publication Critical patent/JP2002524846A5/ja
Application granted granted Critical
Publication of JP4295922B2 publication Critical patent/JP4295922B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/268Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/942Masking
    • Y10S438/948Radiation resist
    • Y10S438/952Utilizing antireflective layer

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Optics & Photonics (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP2000568107A 1998-08-27 1998-11-25 小型集積回路の作製における用途に適したガス浸漬レーザアニーリング方法 Expired - Fee Related JP4295922B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/141,842 1998-08-27
US09/141,842 US5956603A (en) 1998-08-27 1998-08-27 Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits
PCT/US1998/025264 WO2000013213A1 (en) 1998-08-27 1998-11-25 Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits

Publications (3)

Publication Number Publication Date
JP2002524846A JP2002524846A (ja) 2002-08-06
JP2002524846A5 JP2002524846A5 (enExample) 2006-01-19
JP4295922B2 true JP4295922B2 (ja) 2009-07-15

Family

ID=22497510

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000568107A Expired - Fee Related JP4295922B2 (ja) 1998-08-27 1998-11-25 小型集積回路の作製における用途に適したガス浸漬レーザアニーリング方法

Country Status (7)

Country Link
US (1) US5956603A (enExample)
EP (1) EP1121713B1 (enExample)
JP (1) JP4295922B2 (enExample)
KR (1) KR100582484B1 (enExample)
DE (1) DE69837054T2 (enExample)
TW (1) TW409293B (enExample)
WO (1) WO2000013213A1 (enExample)

Families Citing this family (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6521501B1 (en) * 1999-05-11 2003-02-18 Advanced Micro Devices, Inc. Method of forming a CMOS transistor having ultra shallow source and drain regions
US6586318B1 (en) * 1999-12-28 2003-07-01 Xerox Corporation Thin phosphorus nitride film as an N-type doping source used in laser doping technology
JP2001313390A (ja) * 2000-02-29 2001-11-09 Agere Systems Inc 半導体材料における選択的レーザ・アニール
US6570656B1 (en) 2000-04-10 2003-05-27 Ultratech Stepper, Inc. Illumination fluence regulation system and method for use in thermal processing employed in the fabrication of reduced-dimension integrated circuits
US6645838B1 (en) * 2000-04-10 2003-11-11 Ultratech Stepper, Inc. Selective absorption process for forming an activated doped region in a semiconductor
US6635588B1 (en) * 2000-06-12 2003-10-21 Ultratech Stepper, Inc. Method for laser thermal processing using thermally induced reflectivity switch
JP4389359B2 (ja) * 2000-06-23 2009-12-24 日本電気株式会社 薄膜トランジスタ及びその製造方法
US6335253B1 (en) 2000-07-12 2002-01-01 Chartered Semiconductor Manufacturing Ltd. Method to form MOS transistors with shallow junctions using laser annealing
JP2002050764A (ja) * 2000-08-02 2002-02-15 Matsushita Electric Ind Co Ltd 薄膜トランジスタ、アレイ基板、液晶表示装置、有機el表示装置およびその製造方法
US6391695B1 (en) * 2000-08-07 2002-05-21 Advanced Micro Devices, Inc. Double-gate transistor formed in a thermal process
US6635541B1 (en) * 2000-09-11 2003-10-21 Ultratech Stepper, Inc. Method for annealing using partial absorber layer exposed to radiant energy and article made with partial absorber layer
US6479821B1 (en) * 2000-09-11 2002-11-12 Ultratech Stepper, Inc. Thermally induced phase switch for laser thermal processing
US6730583B2 (en) * 2000-10-26 2004-05-04 Hynix Semiconductor Inc. Method for fabricating semiconductor device
US6365476B1 (en) 2000-10-27 2002-04-02 Ultratech Stepper, Inc. Laser thermal process for fabricating field-effect transistors
JP4845299B2 (ja) 2001-03-09 2011-12-28 富士通セミコンダクター株式会社 半導体装置の製造方法
US6720241B2 (en) * 2001-06-18 2004-04-13 Matsushita Electric Industrial Co., Ltd. Method for manufacturing semiconductor device
JP4209606B2 (ja) * 2001-08-17 2009-01-14 株式会社半導体エネルギー研究所 半導体装置の作製方法
TWI282126B (en) * 2001-08-30 2007-06-01 Semiconductor Energy Lab Method for manufacturing semiconductor device
US7112517B2 (en) 2001-09-10 2006-09-26 Semiconductor Energy Laboratory Co., Ltd. Laser treatment device, laser treatment method, and semiconductor device fabrication method
US7317205B2 (en) * 2001-09-10 2008-01-08 Semiconductor Energy Laboratory Co., Ltd. Light emitting device and method of manufacturing a semiconductor device
US6734081B1 (en) * 2001-10-24 2004-05-11 Lsi Logic Corporation Shallow trench isolation structure for laser thermal processing
US6723634B1 (en) * 2002-03-14 2004-04-20 Advanced Micro Devices, Inc. Method of forming interconnects with improved barrier layer adhesion
US7135423B2 (en) * 2002-05-09 2006-11-14 Varian Semiconductor Equipment Associates, Inc Methods for forming low resistivity, ultrashallow junctions with low damage
US6803270B2 (en) * 2003-02-21 2004-10-12 International Business Machines Corporation CMOS performance enhancement using localized voids and extended defects
JP4589606B2 (ja) 2003-06-02 2010-12-01 住友重機械工業株式会社 半導体装置の製造方法
JP2005101196A (ja) * 2003-09-24 2005-04-14 Hitachi Ltd 半導体集積回路装置の製造方法
US7109087B2 (en) * 2003-10-03 2006-09-19 Applied Materials, Inc. Absorber layer for DSA processing
US6897118B1 (en) * 2004-02-11 2005-05-24 Chartered Semiconductor Manufacturing Ltd. Method of multiple pulse laser annealing to activate ultra-shallow junctions
US7145104B2 (en) * 2004-02-26 2006-12-05 Ultratech, Inc. Silicon layer for uniformizing temperature during photo-annealing
US7622374B2 (en) * 2005-12-29 2009-11-24 Infineon Technologies Ag Method of fabricating an integrated circuit
US20070212859A1 (en) * 2006-03-08 2007-09-13 Paul Carey Method of thermal processing structures formed on a substrate
WO2007103643A2 (en) * 2006-03-08 2007-09-13 Applied Materials, Inc. Method and apparatus for thermal processing structures formed on a substrate
US7548364B2 (en) 2006-07-31 2009-06-16 Applied Materials, Inc. Ultra-fast beam dithering with surface acoustic wave modulator
US20080025354A1 (en) * 2006-07-31 2008-01-31 Dean Jennings Ultra-Fast Beam Dithering with Surface Acoustic Wave Modulator
US20080045041A1 (en) * 2006-08-17 2008-02-21 Toshiba America Electronic Components, Inc. Liquid Immersion Laser Spike Anneal
US7692275B2 (en) * 2007-02-26 2010-04-06 International Business Machines Corporation Structure and method for device-specific fill for improved anneal uniformity
US7759773B2 (en) * 2007-02-26 2010-07-20 International Business Machines Corporation Semiconductor wafer structure with balanced reflectance and absorption characteristics for rapid thermal anneal uniformity
US7745909B2 (en) * 2007-02-26 2010-06-29 International Business Machines Corporation Localized temperature control during rapid thermal anneal
US20090096066A1 (en) * 2007-10-10 2009-04-16 Anderson Brent A Structure and Method for Device-Specific Fill for Improved Anneal Uniformity
US7679166B2 (en) * 2007-02-26 2010-03-16 International Business Machines Corporation Localized temperature control during rapid thermal anneal
US7732353B2 (en) * 2007-04-18 2010-06-08 Ultratech, Inc. Methods of forming a denuded zone in a semiconductor wafer using rapid laser annealing
US8148663B2 (en) 2007-07-31 2012-04-03 Applied Materials, Inc. Apparatus and method of improving beam shaping and beam homogenization
US20110185971A1 (en) * 2009-11-30 2011-08-04 Uvtech Systems, Inc. Laser doping
US8021950B1 (en) 2010-10-26 2011-09-20 International Business Machines Corporation Semiconductor wafer processing method that allows device regions to be selectively annealed following back end of the line (BEOL) metal wiring layer formation
US9302348B2 (en) 2011-06-07 2016-04-05 Ultratech Inc. Ultrafast laser annealing with reduced pattern density effects in integrated circuit fabrication
US10591687B2 (en) 2017-05-19 2020-03-17 Adolite Inc. Optical interconnect modules with 3D polymer waveguide
JP7542350B2 (ja) * 2020-07-21 2024-08-30 Jswアクティナシステム株式会社 レーザアニール装置、レーザアニール方法、及び半導体装置の製造方法

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5669837A (en) * 1979-11-12 1981-06-11 Fujitsu Ltd Manufacture of semiconductor device
US4371421A (en) * 1981-04-16 1983-02-01 Massachusetts Institute Of Technology Lateral epitaxial growth by seeded solidification
JPS5856409A (ja) * 1981-09-30 1983-04-04 Toshiba Corp 半導体装置の製造方法
JPS59115574A (ja) * 1982-12-23 1984-07-04 Semiconductor Energy Lab Co Ltd 光電変換装置作製方法
EP0178447B1 (en) * 1984-10-09 1993-02-17 Fujitsu Limited A manufacturing method of an integrated circuit based on semiconductor-on-insulator technology
US4659392A (en) * 1985-03-21 1987-04-21 Hughes Aircraft Company Selective area double epitaxial process for fabricating silicon-on-insulator structures for use with MOS devices and integrated circuits
JPH0793258B2 (ja) * 1985-12-04 1995-10-09 富士通株式会社 導電体膜の再結晶化方法
US4753895A (en) * 1987-02-24 1988-06-28 Hughes Aircraft Company Method of forming low leakage CMOS device on insulating substrate
US5087576A (en) * 1987-10-26 1992-02-11 North Carolina State University Implantation and electrical activation of dopants into monocrystalline silicon carbide
US5318915A (en) * 1993-01-25 1994-06-07 North Carolina State University At Raleigh Method for forming a p-n junction in silicon carbide
US5908307A (en) * 1997-01-31 1999-06-01 Ultratech Stepper, Inc. Fabrication method for reduced-dimension FET devices
US5918915A (en) * 1997-11-03 1999-07-06 Calteux; Kenneth J. Sliding door lock

Also Published As

Publication number Publication date
DE69837054D1 (de) 2007-03-22
JP2002524846A (ja) 2002-08-06
EP1121713B1 (en) 2007-02-07
DE69837054T2 (de) 2007-06-06
EP1121713A1 (en) 2001-08-08
EP1121713A4 (en) 2003-07-16
WO2000013213A1 (en) 2000-03-09
KR20010074629A (ko) 2001-08-04
US5956603A (en) 1999-09-21
KR100582484B1 (ko) 2006-05-24
TW409293B (en) 2000-10-21

Similar Documents

Publication Publication Date Title
JP4295922B2 (ja) 小型集積回路の作製における用途に適したガス浸漬レーザアニーリング方法
KR100511765B1 (ko) 소형 집적회로의 제조방법
US6365476B1 (en) Laser thermal process for fabricating field-effect transistors
US6936505B2 (en) Method of forming a shallow junction
US6300208B1 (en) Methods for annealing an integrated device using a radiant energy absorber layer
US20010012693A1 (en) Method for forming a silicide region on a silicon body
US6927130B2 (en) Method of manufacturing a trench gate type field effect transistor
JP3277533B2 (ja) 半導体装置の製造方法
JPH0669149A (ja) 半導体装置の製造方法
US20020192914A1 (en) CMOS device fabrication utilizing selective laser anneal to form raised source/drain areas
KR20040029423A (ko) 반도체 게이트의 도핑 방법
KR20010072876A (ko) 집적장치의 실리사이드 영역 형성방법
JPS61179578A (ja) 電界効果トランジスタの製作方法
US6040224A (en) Method of manufacturing semiconductor devices
JP2002246329A (ja) 半導体基板の極浅pn接合の形成方法
JP5103695B2 (ja) 電界効果型半導体装置の製造方法
JP3031398B2 (ja) Misトランジスタの作製方法
US20010018258A1 (en) Method for fabricating semiconductor device
JPH0677155A (ja) 半導体基板の熱処理方法
KR102608340B1 (ko) 엑시머 레이저 어닐링을 이용한 초저접합 실리사이드층 형성방법
JP2830718B2 (ja) 薄膜トランジスタの製造方法
JP3370029B2 (ja) 半導体装置の作製方法
JP3387862B2 (ja) 半導体装置の作製方法
JPH0845837A (ja) 多結晶半導体膜の製造方法
KR20000026834A (ko) 반도체 소자의 실리사이드 형성방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20051121

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20051121

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20071206

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20071217

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080306

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080313

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20080411

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20080418

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080613

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080728

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20081007

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20081015

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20081126

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20081203

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20081218

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20081226

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20090127

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20090407

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20090413

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120417

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130417

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130417

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140417

Year of fee payment: 5

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees