JP4141656B2 - 半導体メモリ集積回路および半導体メモリ装置をテストする方法 - Google Patents

半導体メモリ集積回路および半導体メモリ装置をテストする方法 Download PDF

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JP4141656B2
JP4141656B2 JP2001116661A JP2001116661A JP4141656B2 JP 4141656 B2 JP4141656 B2 JP 4141656B2 JP 2001116661 A JP2001116661 A JP 2001116661A JP 2001116661 A JP2001116661 A JP 2001116661A JP 4141656 B2 JP4141656 B2 JP 4141656B2
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spare
signal line
cell array
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JP2001116661A
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Japanese (ja)
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JP2002063798A (ja
JP2002063798A5 (https=
Inventor
瀬 覚 高
井 健 永
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Toshiba Corp
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Toshiba Corp
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Priority to JP2001116661A priority Critical patent/JP4141656B2/ja
Priority to US09/867,796 priority patent/US6490210B2/en
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Publication of JP2002063798A5 publication Critical patent/JP2002063798A5/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/14—Implementation of control logic, e.g. test mode decoders
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Dram (AREA)
JP2001116661A 2000-06-07 2001-04-16 半導体メモリ集積回路および半導体メモリ装置をテストする方法 Expired - Fee Related JP4141656B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001116661A JP4141656B2 (ja) 2000-06-07 2001-04-16 半導体メモリ集積回路および半導体メモリ装置をテストする方法
US09/867,796 US6490210B2 (en) 2000-06-07 2001-05-31 Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2000-170613 2000-06-07
JP2000170613 2000-06-07
JP2001116661A JP4141656B2 (ja) 2000-06-07 2001-04-16 半導体メモリ集積回路および半導体メモリ装置をテストする方法

Publications (3)

Publication Number Publication Date
JP2002063798A JP2002063798A (ja) 2002-02-28
JP2002063798A5 JP2002063798A5 (https=) 2005-06-09
JP4141656B2 true JP4141656B2 (ja) 2008-08-27

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JP2001116661A Expired - Fee Related JP4141656B2 (ja) 2000-06-07 2001-04-16 半導体メモリ集積回路および半導体メモリ装置をテストする方法

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Country Link
US (1) US6490210B2 (https=)
JP (1) JP4141656B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230267987A1 (en) * 2022-02-24 2023-08-24 Changxin Memory Technologies, Inc. Method and apparatus for intensifying current leakage between adjacent memory cells, and method and apparatus for current leakage detection

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6915467B2 (en) * 2001-12-11 2005-07-05 International Business Machines Corporation System and method for testing a column redundancy of an integrated circuit memory
KR100474510B1 (ko) * 2002-05-07 2005-03-08 주식회사 하이닉스반도체 플래시 메모리 소자의 테스트 회로
US6731550B2 (en) * 2002-05-31 2004-05-04 Stmicroelectronics, Inc. Redundancy circuit and method for semiconductor memory devices
KR20030093410A (ko) * 2002-06-03 2003-12-11 삼성전자주식회사 반도체 메모리 장치에서의 리던던시 메모리 셀의 번인제어 회로 및 그 제어 방법
JP2005092963A (ja) * 2003-09-16 2005-04-07 Renesas Technology Corp 不揮発性記憶装置
JP4424952B2 (ja) * 2003-09-16 2010-03-03 株式会社ルネサステクノロジ 不揮発性半導体記憶装置
US6894937B2 (en) * 2003-09-26 2005-05-17 Freescale Semiconductor, Inc. Accelerated life test of MRAM cells
US20050144524A1 (en) * 2003-12-04 2005-06-30 International Business Machines Corporation Digital reliability monitor having autonomic repair and notification capability
US7287177B2 (en) * 2003-12-04 2007-10-23 International Business Machines Corporation Digital reliability monitor having autonomic repair and notification capability
JP2005267817A (ja) * 2004-03-22 2005-09-29 Oki Electric Ind Co Ltd 半導体記憶装置と冗長救済アドレスの読出方法
JP2006185488A (ja) * 2004-12-27 2006-07-13 Elpida Memory Inc 半導体記憶装置
JP2006196700A (ja) * 2005-01-13 2006-07-27 Toshiba Corp 不揮発性半導体記憶装置
US20080291760A1 (en) * 2007-05-23 2008-11-27 Micron Technology, Inc. Sub-array architecture memory devices and related systems and methods
JP5513730B2 (ja) * 2008-02-08 2014-06-04 ピーエスフォー ルクスコ エスエイアールエル 半導体記憶装置
JP2009187641A (ja) * 2008-02-08 2009-08-20 Elpida Memory Inc 半導体記憶装置及びその制御方法、並びに不良アドレスの救済可否判定方法
US11024352B2 (en) 2012-04-10 2021-06-01 Samsung Electronics Co., Ltd. Memory system for access concentration decrease management and access concentration decrease method
KR20140094668A (ko) * 2013-01-17 2014-07-30 삼성전자주식회사 리던던시 회로 및 이를 포함하는 반도체 메모리 장치
KR20160001097A (ko) * 2014-06-26 2016-01-06 에스케이하이닉스 주식회사 반도체 장치

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960002777B1 (ko) * 1992-07-13 1996-02-26 삼성전자주식회사 반도체 메모리 장치의 로우 리던던시 장치
JPH06275094A (ja) * 1993-03-23 1994-09-30 Mitsubishi Electric Corp 半導体装置および半導体メモリ装置
JP2570203B2 (ja) * 1994-11-22 1997-01-08 日本電気株式会社 半導体記憶装置
JP3865828B2 (ja) * 1995-11-28 2007-01-10 株式会社ルネサステクノロジ 半導体記憶装置
US5699307A (en) * 1996-06-28 1997-12-16 Intel Corporation Method and apparatus for providing redundant memory in an integrated circuit utilizing a subarray shuffle replacement scheme
US6188618B1 (en) 1998-04-23 2001-02-13 Kabushiki Kaisha Toshiba Semiconductor device with flexible redundancy system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20230267987A1 (en) * 2022-02-24 2023-08-24 Changxin Memory Technologies, Inc. Method and apparatus for intensifying current leakage between adjacent memory cells, and method and apparatus for current leakage detection
US12094516B2 (en) * 2022-02-24 2024-09-17 Changxin Memory Technologies, Inc. Method and apparatus for intensifying current leakage between adjacent memory cells, and method and apparatus for current leakage detection

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JP2002063798A (ja) 2002-02-28
US6490210B2 (en) 2002-12-03
US20010050871A1 (en) 2001-12-13

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