JP2002063798A5 - - Google Patents
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- JP2002063798A5 JP2002063798A5 JP2001116661A JP2001116661A JP2002063798A5 JP 2002063798 A5 JP2002063798 A5 JP 2002063798A5 JP 2001116661 A JP2001116661 A JP 2001116661A JP 2001116661 A JP2001116661 A JP 2001116661A JP 2002063798 A5 JP2002063798 A5 JP 2002063798A5
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- 238000012360 testing method Methods 0.000 claims 24
- 239000004065 semiconductor Substances 0.000 claims 20
- 238000010998 test method Methods 0.000 claims 3
- 238000003491 array Methods 0.000 claims 2
- 230000007547 defect Effects 0.000 claims 2
- 230000002950 deficient Effects 0.000 claims 2
- 238000000034 method Methods 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001116661A JP4141656B2 (ja) | 2000-06-07 | 2001-04-16 | 半導体メモリ集積回路および半導体メモリ装置をテストする方法 |
| US09/867,796 US6490210B2 (en) | 2000-06-07 | 2001-05-31 | Semiconductor memory integrated circuit employing a redundant circuit system for compensating for defectiveness |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000-170613 | 2000-06-07 | ||
| JP2000170613 | 2000-06-07 | ||
| JP2001116661A JP4141656B2 (ja) | 2000-06-07 | 2001-04-16 | 半導体メモリ集積回路および半導体メモリ装置をテストする方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2002063798A JP2002063798A (ja) | 2002-02-28 |
| JP2002063798A5 true JP2002063798A5 (https=) | 2005-06-09 |
| JP4141656B2 JP4141656B2 (ja) | 2008-08-27 |
Family
ID=26593487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001116661A Expired - Fee Related JP4141656B2 (ja) | 2000-06-07 | 2001-04-16 | 半導体メモリ集積回路および半導体メモリ装置をテストする方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6490210B2 (https=) |
| JP (1) | JP4141656B2 (https=) |
Families Citing this family (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6915467B2 (en) * | 2001-12-11 | 2005-07-05 | International Business Machines Corporation | System and method for testing a column redundancy of an integrated circuit memory |
| KR100474510B1 (ko) * | 2002-05-07 | 2005-03-08 | 주식회사 하이닉스반도체 | 플래시 메모리 소자의 테스트 회로 |
| US6731550B2 (en) * | 2002-05-31 | 2004-05-04 | Stmicroelectronics, Inc. | Redundancy circuit and method for semiconductor memory devices |
| KR20030093410A (ko) * | 2002-06-03 | 2003-12-11 | 삼성전자주식회사 | 반도체 메모리 장치에서의 리던던시 메모리 셀의 번인제어 회로 및 그 제어 방법 |
| JP2005092963A (ja) * | 2003-09-16 | 2005-04-07 | Renesas Technology Corp | 不揮発性記憶装置 |
| JP4424952B2 (ja) * | 2003-09-16 | 2010-03-03 | 株式会社ルネサステクノロジ | 不揮発性半導体記憶装置 |
| US6894937B2 (en) * | 2003-09-26 | 2005-05-17 | Freescale Semiconductor, Inc. | Accelerated life test of MRAM cells |
| US20050144524A1 (en) * | 2003-12-04 | 2005-06-30 | International Business Machines Corporation | Digital reliability monitor having autonomic repair and notification capability |
| US7287177B2 (en) * | 2003-12-04 | 2007-10-23 | International Business Machines Corporation | Digital reliability monitor having autonomic repair and notification capability |
| JP2005267817A (ja) * | 2004-03-22 | 2005-09-29 | Oki Electric Ind Co Ltd | 半導体記憶装置と冗長救済アドレスの読出方法 |
| JP2006185488A (ja) * | 2004-12-27 | 2006-07-13 | Elpida Memory Inc | 半導体記憶装置 |
| JP2006196700A (ja) * | 2005-01-13 | 2006-07-27 | Toshiba Corp | 不揮発性半導体記憶装置 |
| US20080291760A1 (en) * | 2007-05-23 | 2008-11-27 | Micron Technology, Inc. | Sub-array architecture memory devices and related systems and methods |
| JP5513730B2 (ja) * | 2008-02-08 | 2014-06-04 | ピーエスフォー ルクスコ エスエイアールエル | 半導体記憶装置 |
| JP2009187641A (ja) * | 2008-02-08 | 2009-08-20 | Elpida Memory Inc | 半導体記憶装置及びその制御方法、並びに不良アドレスの救済可否判定方法 |
| US11024352B2 (en) | 2012-04-10 | 2021-06-01 | Samsung Electronics Co., Ltd. | Memory system for access concentration decrease management and access concentration decrease method |
| KR20140094668A (ko) * | 2013-01-17 | 2014-07-30 | 삼성전자주식회사 | 리던던시 회로 및 이를 포함하는 반도체 메모리 장치 |
| KR20160001097A (ko) * | 2014-06-26 | 2016-01-06 | 에스케이하이닉스 주식회사 | 반도체 장치 |
| US12094516B2 (en) * | 2022-02-24 | 2024-09-17 | Changxin Memory Technologies, Inc. | Method and apparatus for intensifying current leakage between adjacent memory cells, and method and apparatus for current leakage detection |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR960002777B1 (ko) * | 1992-07-13 | 1996-02-26 | 삼성전자주식회사 | 반도체 메모리 장치의 로우 리던던시 장치 |
| JPH06275094A (ja) * | 1993-03-23 | 1994-09-30 | Mitsubishi Electric Corp | 半導体装置および半導体メモリ装置 |
| JP2570203B2 (ja) * | 1994-11-22 | 1997-01-08 | 日本電気株式会社 | 半導体記憶装置 |
| JP3865828B2 (ja) * | 1995-11-28 | 2007-01-10 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US5699307A (en) * | 1996-06-28 | 1997-12-16 | Intel Corporation | Method and apparatus for providing redundant memory in an integrated circuit utilizing a subarray shuffle replacement scheme |
| US6188618B1 (en) | 1998-04-23 | 2001-02-13 | Kabushiki Kaisha Toshiba | Semiconductor device with flexible redundancy system |
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2001
- 2001-04-16 JP JP2001116661A patent/JP4141656B2/ja not_active Expired - Fee Related
- 2001-05-31 US US09/867,796 patent/US6490210B2/en not_active Expired - Fee Related
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