JP4138254B2 - 記憶セル構造、およびこれを製造する方法 - Google Patents

記憶セル構造、およびこれを製造する方法 Download PDF

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Publication number
JP4138254B2
JP4138254B2 JP2000603042A JP2000603042A JP4138254B2 JP 4138254 B2 JP4138254 B2 JP 4138254B2 JP 2000603042 A JP2000603042 A JP 2000603042A JP 2000603042 A JP2000603042 A JP 2000603042A JP 4138254 B2 JP4138254 B2 JP 4138254B2
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Japan
Prior art keywords
wiring
layer
groove
magnetoresistive
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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JP2000603042A
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English (en)
Japanese (ja)
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JP2002538614A5 (enExample
JP2002538614A (ja
Inventor
シュヴァルツル，ジークフリート
シェーラー，ウルリッヒ
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Infineon Technologies AG
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Infineon Technologies AG
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Publication date
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Publication of JP2002538614A publication Critical patent/JP2002538614A/ja
Publication of JP2002538614A5 publication Critical patent/JP2002538614A5/ja
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Publication of JP4138254B2 publication Critical patent/JP4138254B2/ja
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
    • G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Semiconductor Memories (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
JP2000603042A 1999-02-26 2000-02-01 記憶セル構造、およびこれを製造する方法 Expired - Fee Related JP4138254B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19908518.8 1999-02-26
DE19908518 1999-02-26
PCT/DE2000/000305 WO2000052701A1 (de) 1999-02-26 2000-02-01 Speicherzellenanordnung und verfahren zu deren herstellung

Publications (3)

Publication Number Publication Date
JP2002538614A JP2002538614A (ja) 2002-11-12
JP2002538614A5 JP2002538614A5 (enExample) 2006-03-02
JP4138254B2 true JP4138254B2 (ja) 2008-08-27

Family

ID=7899068

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000603042A Expired - Fee Related JP4138254B2 (ja) 1999-02-26 2000-02-01 記憶セル構造、およびこれを製造する方法

Country Status (8)

Country Link
US (1) US6630703B2 (enExample)
EP (1) EP1157388B1 (enExample)
JP (1) JP4138254B2 (enExample)
KR (1) KR100450468B1 (enExample)
CN (1) CN1183545C (enExample)
DE (1) DE50000341D1 (enExample)
TW (1) TW462051B (enExample)
WO (1) WO2000052701A1 (enExample)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1157388B1 (de) 1999-02-26 2002-07-31 Infineon Technologies AG Speicherzellenanordnung und verfahren zu deren herstellung
US6392922B1 (en) * 2000-08-14 2002-05-21 Micron Technology, Inc. Passivated magneto-resistive bit structure and passivation method therefor
DE10043159A1 (de) 2000-09-01 2002-03-21 Infineon Technologies Ag Speicherzellenanordnung und Verfahren zu deren Herstellung
DE10050076C2 (de) 2000-10-10 2003-09-18 Infineon Technologies Ag Verfahren zur Herstellung einer ferromagnetischen Struktur und ferromagnetisches Bauelement
US6555858B1 (en) * 2000-11-15 2003-04-29 Motorola, Inc. Self-aligned magnetic clad write line and its method of formation
US6440753B1 (en) * 2001-01-24 2002-08-27 Infineon Technologies North America Corp. Metal hard mask for ILD RIE processing of semiconductor memory devices to prevent oxidation of conductive lines
DE10103868A1 (de) * 2001-01-30 2002-08-22 Bosch Gmbh Robert GMR-Struktur und Verfahren zu deren Herstellung
US6358756B1 (en) * 2001-02-07 2002-03-19 Micron Technology, Inc. Self-aligned, magnetoresistive random-access memory (MRAM) structure utilizing a spacer containment scheme
JP3892736B2 (ja) * 2001-03-29 2007-03-14 株式会社東芝 半導体記憶装置
JP2002299575A (ja) 2001-03-29 2002-10-11 Toshiba Corp 半導体記憶装置
DE10124366A1 (de) * 2001-05-18 2002-11-28 Infineon Technologies Ag Verfahren zum Herstellen einer Halbleiterspeichereinrichtung
DE10125594A1 (de) 2001-05-25 2002-12-05 Infineon Technologies Ag Halbleiterspeichereinrichtung sowie Verfahren zu deren Herstellung
US6485989B1 (en) 2001-08-30 2002-11-26 Micron Technology, Inc. MRAM sense layer isolation
US6751149B2 (en) 2002-03-22 2004-06-15 Micron Technology, Inc. Magnetic tunneling junction antifuse device
US6783995B2 (en) * 2002-04-30 2004-08-31 Micron Technology, Inc. Protective layers for MRAM devices
US6784091B1 (en) * 2003-06-05 2004-08-31 International Business Machines Corporation Maskless array protection process flow for forming interconnect vias in magnetic random access memory devices
US6885577B2 (en) * 2003-06-18 2005-04-26 Taiwan Semiconductor Manufacturing Company, Ltd. Magnetic RAM cell device and array architecture
US7112454B2 (en) * 2003-10-14 2006-09-26 Micron Technology, Inc. System and method for reducing shorting in memory cells
JP2005260082A (ja) * 2004-03-12 2005-09-22 Toshiba Corp 磁気ランダムアクセスメモリ
JP4131869B2 (ja) * 2005-01-31 2008-08-13 Ｔｄｋ株式会社 電流センサ
US8698490B2 (en) * 2010-12-15 2014-04-15 Infineon Technologies Ag Magnetoresistive angle sensors having conductors arranged in multiple planes

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5587943A (en) * 1995-02-13 1996-12-24 Integrated Microtransducer Electronics Corporation Nonvolatile magnetoresistive memory with fully closed flux operation
KR100262282B1 (ko) * 1996-04-30 2000-10-02 니시무로 타이죠 자기 저항 효과 소자
US5920500A (en) * 1996-08-23 1999-07-06 Motorola, Inc. Magnetic random access memory having stacked memory cells and fabrication method therefor
US5861328A (en) * 1996-10-07 1999-01-19 Motorola, Inc. Method of fabricating GMR devices
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
EP1157388B1 (de) 1999-02-26 2002-07-31 Infineon Technologies AG Speicherzellenanordnung und verfahren zu deren herstellung

Also Published As

Publication number Publication date
JP2002538614A (ja) 2002-11-12
WO2000052701A1 (de) 2000-09-08
CN1183545C (zh) 2005-01-05
EP1157388A1 (de) 2001-11-28
EP1157388B1 (de) 2002-07-31
US20020041514A1 (en) 2002-04-11
DE50000341D1 (de) 2002-09-05
KR20010103779A (ko) 2001-11-23
CN1349650A (zh) 2002-05-15
US6630703B2 (en) 2003-10-07
TW462051B (en) 2001-11-01
KR100450468B1 (ko) 2004-09-30

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