JP4048048B2 - 基板処理方法 - Google Patents

基板処理方法 Download PDF

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Publication number
JP4048048B2
JP4048048B2 JP2001385108A JP2001385108A JP4048048B2 JP 4048048 B2 JP4048048 B2 JP 4048048B2 JP 2001385108 A JP2001385108 A JP 2001385108A JP 2001385108 A JP2001385108 A JP 2001385108A JP 4048048 B2 JP4048048 B2 JP 4048048B2
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JP
Japan
Prior art keywords
substrate
plasma
substrate processing
oxygen
treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001385108A
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English (en)
Japanese (ja)
Other versions
JP2003188172A (ja
Inventor
卓也 菅原
征嗣 松山
勝 佐々木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tokyo Electron Ltd
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Priority to JP2001385108A priority Critical patent/JP4048048B2/ja
Priority to AU2002357591A priority patent/AU2002357591A1/en
Priority to PCT/JP2002/013134 priority patent/WO2003052810A1/ja
Priority to TW091136459A priority patent/TW200301311A/zh
Publication of JP2003188172A publication Critical patent/JP2003188172A/ja
Priority to US11/076,282 priority patent/US7517751B2/en
Application granted granted Critical
Publication of JP4048048B2 publication Critical patent/JP4048048B2/ja
Priority to US12/392,630 priority patent/US20090163036A1/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2001385108A 2001-12-18 2001-12-18 基板処理方法 Expired - Fee Related JP4048048B2 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2001385108A JP4048048B2 (ja) 2001-12-18 2001-12-18 基板処理方法
AU2002357591A AU2002357591A1 (en) 2001-12-18 2002-12-16 Substrate treating method
PCT/JP2002/013134 WO2003052810A1 (en) 2001-12-18 2002-12-16 Substrate treating method
TW091136459A TW200301311A (en) 2001-12-18 2002-12-17 Method for processing substrates
US11/076,282 US7517751B2 (en) 2001-12-18 2005-03-10 Substrate treating method
US12/392,630 US20090163036A1 (en) 2001-12-18 2009-02-25 Substrate Treating Method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001385108A JP4048048B2 (ja) 2001-12-18 2001-12-18 基板処理方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2007120837A Division JP2007201507A (ja) 2007-05-01 2007-05-01 基板処理方法および基板処理装置

Publications (2)

Publication Number Publication Date
JP2003188172A JP2003188172A (ja) 2003-07-04
JP4048048B2 true JP4048048B2 (ja) 2008-02-13

Family

ID=19187790

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001385108A Expired - Fee Related JP4048048B2 (ja) 2001-12-18 2001-12-18 基板処理方法

Country Status (4)

Country Link
JP (1) JP4048048B2 (enrdf_load_stackoverflow)
AU (1) AU2002357591A1 (enrdf_load_stackoverflow)
TW (1) TW200301311A (enrdf_load_stackoverflow)
WO (1) WO2003052810A1 (enrdf_load_stackoverflow)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003098678A1 (en) 2002-05-16 2003-11-27 Tokyo Electron Limited Method of treating substrate
US20080233764A1 (en) * 2004-04-09 2008-09-25 Tsuyoshi Takahashi Formation of Gate Insulation Film
JP2006245528A (ja) * 2005-02-01 2006-09-14 Tohoku Univ 誘電体膜及びその形成方法
JP2007012788A (ja) * 2005-06-29 2007-01-18 Elpida Memory Inc 半導体装置の製造方法
JP2008192975A (ja) * 2007-02-07 2008-08-21 Hitachi Kokusai Electric Inc 基板処理方法
JP6039996B2 (ja) * 2011-12-09 2016-12-07 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
JP6032963B2 (ja) * 2012-06-20 2016-11-30 キヤノン株式会社 Ｓｏｉ基板、ｓｏｉ基板の製造方法および半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4001960B2 (ja) * 1995-11-03 2007-10-31 フリースケール セミコンダクター インコーポレイテッド 窒化酸化物誘電体層を有する半導体素子の製造方法
JP3485403B2 (ja) * 1995-11-28 2004-01-13 沖電気工業株式会社 半導体装置の製造方法
JPH1027795A (ja) * 1996-07-12 1998-01-27 Toshiba Corp 半導体装置の製造方法
JP3399413B2 (ja) * 1999-09-13 2003-04-21 日本電気株式会社 酸窒化膜およびその形成方法
JP4731694B2 (ja) * 2000-07-21 2011-07-27 東京エレクトロン株式会社 半導体装置の製造方法および基板処理装置
JP4713752B2 (ja) * 2000-12-28 2011-06-29 財団法人国際科学振興財団 半導体装置およびその製造方法

Also Published As

Publication number Publication date
TW200301311A (en) 2003-07-01
AU2002357591A1 (en) 2003-06-30
TWI292441B (enrdf_load_stackoverflow) 2008-01-11
JP2003188172A (ja) 2003-07-04
WO2003052810A1 (en) 2003-06-26

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