TW200301311A - Method for processing substrates - Google Patents

Method for processing substrates Download PDF

Info

Publication number
TW200301311A
TW200301311A TW091136459A TW91136459A TW200301311A TW 200301311 A TW200301311 A TW 200301311A TW 091136459 A TW091136459 A TW 091136459A TW 91136459 A TW91136459 A TW 91136459A TW 200301311 A TW200301311 A TW 200301311A
Authority
TW
Taiwan
Prior art keywords
treatment
plasma
scope
item
substrate processing
Prior art date
Application number
TW091136459A
Other languages
English (en)
Chinese (zh)
Other versions
TWI292441B (enrdf_load_stackoverflow
Inventor
Takuya Sugawara
Seiji Matsuyama
Masaru Sasaki
Original Assignee
Tokyo Electron Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Ltd filed Critical Tokyo Electron Ltd
Publication of TW200301311A publication Critical patent/TW200301311A/zh
Application granted granted Critical
Publication of TWI292441B publication Critical patent/TWI292441B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
TW091136459A 2001-12-18 2002-12-17 Method for processing substrates TW200301311A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001385108A JP4048048B2 (ja) 2001-12-18 2001-12-18 基板処理方法

Publications (2)

Publication Number Publication Date
TW200301311A true TW200301311A (en) 2003-07-01
TWI292441B TWI292441B (enrdf_load_stackoverflow) 2008-01-11

Family

ID=19187790

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091136459A TW200301311A (en) 2001-12-18 2002-12-17 Method for processing substrates

Country Status (4)

Country Link
JP (1) JP4048048B2 (enrdf_load_stackoverflow)
AU (1) AU2002357591A1 (enrdf_load_stackoverflow)
TW (1) TW200301311A (enrdf_load_stackoverflow)
WO (1) WO2003052810A1 (enrdf_load_stackoverflow)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2003098678A1 (en) 2002-05-16 2003-11-27 Tokyo Electron Limited Method of treating substrate
US20080233764A1 (en) * 2004-04-09 2008-09-25 Tsuyoshi Takahashi Formation of Gate Insulation Film
JP2006245528A (ja) * 2005-02-01 2006-09-14 Tohoku Univ 誘電体膜及びその形成方法
JP2007012788A (ja) * 2005-06-29 2007-01-18 Elpida Memory Inc 半導体装置の製造方法
JP2008192975A (ja) * 2007-02-07 2008-08-21 Hitachi Kokusai Electric Inc 基板処理方法
JP6039996B2 (ja) * 2011-12-09 2016-12-07 株式会社日立国際電気 半導体装置の製造方法、基板処理方法、基板処理装置およびプログラム
JP6032963B2 (ja) * 2012-06-20 2016-11-30 キヤノン株式会社 Soi基板、soi基板の製造方法および半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4001960B2 (ja) * 1995-11-03 2007-10-31 フリースケール セミコンダクター インコーポレイテッド 窒化酸化物誘電体層を有する半導体素子の製造方法
JP3485403B2 (ja) * 1995-11-28 2004-01-13 沖電気工業株式会社 半導体装置の製造方法
JPH1027795A (ja) * 1996-07-12 1998-01-27 Toshiba Corp 半導体装置の製造方法
JP3399413B2 (ja) * 1999-09-13 2003-04-21 日本電気株式会社 酸窒化膜およびその形成方法
JP4731694B2 (ja) * 2000-07-21 2011-07-27 東京エレクトロン株式会社 半導体装置の製造方法および基板処理装置
JP4713752B2 (ja) * 2000-12-28 2011-06-29 財団法人国際科学振興財団 半導体装置およびその製造方法

Also Published As

Publication number Publication date
AU2002357591A1 (en) 2003-06-30
TWI292441B (enrdf_load_stackoverflow) 2008-01-11
JP2003188172A (ja) 2003-07-04
WO2003052810A1 (en) 2003-06-26
JP4048048B2 (ja) 2008-02-13

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