JP4001960B2 - 窒化酸化物誘電体層を有する半導体素子の製造方法 - Google Patents

窒化酸化物誘電体層を有する半導体素子の製造方法 Download PDF

Info

Publication number
JP4001960B2
JP4001960B2 JP29822096A JP29822096A JP4001960B2 JP 4001960 B2 JP4001960 B2 JP 4001960B2 JP 29822096 A JP29822096 A JP 29822096A JP 29822096 A JP29822096 A JP 29822096A JP 4001960 B2 JP4001960 B2 JP 4001960B2
Authority
JP
Japan
Prior art keywords
layer
silicon dioxide
oxidizing
semiconductor substrate
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP29822096A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09139437A5 (enExample
JPH09139437A (ja
Inventor
バイカス・マイティ
フィリップ・ジェイ・トビン
セルジオ・エー・アジュリア
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JPH09139437A publication Critical patent/JPH09139437A/ja
Publication of JPH09139437A5 publication Critical patent/JPH09139437A5/ja
Application granted granted Critical
Publication of JP4001960B2 publication Critical patent/JP4001960B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0411Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02329Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen
    • H01L21/02332Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of nitrogen into an oxide layer, e.g. changing SiO to SiON
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02296Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28202Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Formation Of Insulating Films (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP29822096A 1995-11-03 1996-10-21 窒化酸化物誘電体層を有する半導体素子の製造方法 Expired - Fee Related JP4001960B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US55245195A 1995-11-03 1995-11-03
US552451 1995-11-03

Publications (3)

Publication Number Publication Date
JPH09139437A JPH09139437A (ja) 1997-05-27
JPH09139437A5 JPH09139437A5 (enExample) 2004-10-14
JP4001960B2 true JP4001960B2 (ja) 2007-10-31

Family

ID=24205400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP29822096A Expired - Fee Related JP4001960B2 (ja) 1995-11-03 1996-10-21 窒化酸化物誘電体層を有する半導体素子の製造方法

Country Status (3)

Country Link
US (1) US5885870A (enExample)
JP (1) JP4001960B2 (enExample)
KR (1) KR970030859A (enExample)

Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100230429B1 (ko) * 1997-06-27 1999-11-15 윤종용 반도체장치의 실리콘 옥시나이트라이드막 형성방법
US6399445B1 (en) 1997-12-18 2002-06-04 Texas Instruments Incorporated Fabrication technique for controlled incorporation of nitrogen in gate dielectric
US6303942B1 (en) * 1998-03-17 2001-10-16 Farmer, Ii Kenneth Rudolph Multi-layer charge injection barrier and uses thereof
JP3472482B2 (ja) * 1998-06-30 2003-12-02 富士通株式会社 半導体装置の製造方法と製造装置
US6972436B2 (en) * 1998-08-28 2005-12-06 Cree, Inc. High voltage, high temperature capacitor and interconnection structures
KR20000018524A (ko) * 1998-09-02 2000-04-06 김영환 비휘발성 메모리 소자 및 그의 제조방법
US6323114B1 (en) * 1998-11-24 2001-11-27 Texas Instruments Incorporated Stacked/composite gate dielectric which incorporates nitrogen at an interface
US6541394B1 (en) * 1999-01-12 2003-04-01 Agere Systems Guardian Corp. Method of making a graded grown, high quality oxide layer for a semiconductor device
US6261976B1 (en) * 1999-03-18 2001-07-17 Chartered Semiconductor Manufacturing Ltd. Method of forming low pressure silicon oxynitride dielectrics having high reliability
US6492712B1 (en) 1999-06-24 2002-12-10 Agere Systems Guardian Corp. High quality oxide for use in integrated circuits
US6395610B1 (en) 1999-06-24 2002-05-28 Lucent Technologies Inc. Method of making bipolar transistor semiconductor device including graded, grown, high quality oxide layer
US6670242B1 (en) 1999-06-24 2003-12-30 Agere Systems Inc. Method for making an integrated circuit device including a graded, grown, high quality gate oxide layer and a nitride layer
US6509230B1 (en) 1999-06-24 2003-01-21 Lucent Technologies Inc. Non-volatile memory semiconductor device including a graded, grown, high quality oxide layer and associated methods
US6521496B1 (en) 1999-06-24 2003-02-18 Lucent Technologies Inc. Non-volatile memory semiconductor device including a graded, grown, high quality control gate oxide layer and associated methods
US6551946B1 (en) 1999-06-24 2003-04-22 Agere Systems Inc. Two-step oxidation process for oxidizing a silicon substrate wherein the first step is carried out at a temperature below the viscoelastic temperature of silicon dioxide and the second step is carried out at a temperature above the viscoelastic temperature
KR100682190B1 (ko) * 1999-09-07 2007-02-12 동경 엘렉트론 주식회사 실리콘 산질화물을 포함하는 절연막의 형성 방법 및 장치
US6284602B1 (en) * 1999-09-20 2001-09-04 Advanced Micro Devices, Inc. Process to reduce post cycling program VT dispersion for NAND flash memory devices
US6380033B1 (en) 1999-09-20 2002-04-30 Advanced Micro Devices, Inc. Process to improve read disturb for NAND flash memory devices
JP3558565B2 (ja) 1999-11-08 2004-08-25 Necエレクトロニクス株式会社 不揮発性半導体装置の製造方法
US20030235957A1 (en) * 2002-06-25 2003-12-25 Samir Chaudhry Method and structure for graded gate oxides on vertical and non-planar surfaces
US6597047B2 (en) * 2000-03-22 2003-07-22 Matsushita Electric Industrial Co., Ltd. Method for fabricating a nonvolatile semiconductor device
JP2002009282A (ja) * 2000-04-19 2002-01-11 Seiko Instruments Inc 半導体装置の製造方法
DE10029658C2 (de) * 2000-06-16 2003-01-09 Infineon Technologies Ag Verfahren zur Herstellung einer Barrierenschicht auf einem Siliziumsubstrat
US6956238B2 (en) 2000-10-03 2005-10-18 Cree, Inc. Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel
US6610366B2 (en) 2000-10-03 2003-08-26 Cree, Inc. Method of N2O annealing an oxide layer on a silicon carbide layer
US6767843B2 (en) * 2000-10-03 2004-07-27 Cree, Inc. Method of N2O growth of an oxide layer on a silicon carbide layer
US7067176B2 (en) 2000-10-03 2006-06-27 Cree, Inc. Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment
US6850446B1 (en) 2001-12-06 2005-02-01 Virage Logic Corporation Memory cell sensing with low noise generation
US6788574B1 (en) 2001-12-06 2004-09-07 Virage Logic Corporation Electrically-alterable non-volatile memory cell
US7130213B1 (en) * 2001-12-06 2006-10-31 Virage Logic Corporation Methods and apparatuses for a dual-polarity non-volatile memory cell
US6842375B1 (en) 2001-12-06 2005-01-11 Virage Logic Corporation Methods and apparatuses for maintaining information stored in a non-volatile memory cell
US6992938B1 (en) 2001-12-06 2006-01-31 Virage Logic Corporation Methods and apparatuses for test circuitry for a dual-polarity non-volatile memory cell
US7517751B2 (en) * 2001-12-18 2009-04-14 Tokyo Electron Limited Substrate treating method
JP4048048B2 (ja) * 2001-12-18 2008-02-13 東京エレクトロン株式会社 基板処理方法
KR100451768B1 (ko) * 2001-12-28 2004-10-08 주식회사 하이닉스반도체 반도체 소자의 게이트 절연막 형성 방법
KR100548550B1 (ko) * 2002-07-12 2006-02-02 주식회사 하이닉스반도체 반도체 소자의 옥사이드와 나이트라이드의 인시튜 형성방법
US7022378B2 (en) * 2002-08-30 2006-04-04 Cree, Inc. Nitrogen passivation of interface states in SiO2/SiC structures
US7221010B2 (en) * 2002-12-20 2007-05-22 Cree, Inc. Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
US6979863B2 (en) * 2003-04-24 2005-12-27 Cree, Inc. Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same
US7074643B2 (en) * 2003-04-24 2006-07-11 Cree, Inc. Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same
US7709403B2 (en) * 2003-10-09 2010-05-04 Panasonic Corporation Silicon carbide-oxide layered structure, production method thereof, and semiconductor device
US7183143B2 (en) * 2003-10-27 2007-02-27 Macronix International Co., Ltd. Method for forming nitrided tunnel oxide layer
US7135361B2 (en) * 2003-12-11 2006-11-14 Texas Instruments Incorporated Method for fabricating transistor gate structures and gate dielectrics thereof
KR100602322B1 (ko) * 2004-04-20 2006-07-14 에스티마이크로일렉트로닉스 엔.브이. 플래시 메모리 소자의 제조방법 및 이를 통해 제조된플래시 메모리 소자
US7405125B2 (en) * 2004-06-01 2008-07-29 Macronix International Co., Ltd. Tunnel oxynitride in flash memories
US7060594B2 (en) * 2004-10-19 2006-06-13 Macronix International Co., Ltd. Memory device and method of manufacturing including deuterated oxynitride charge trapping structure
KR100673205B1 (ko) * 2004-11-24 2007-01-22 주식회사 하이닉스반도체 플래쉬 메모리소자의 제조방법
US7212457B2 (en) * 2005-05-18 2007-05-01 Macronix International Co., Ltd. Method and apparatus for implementing high speed memory
US7727904B2 (en) * 2005-09-16 2010-06-01 Cree, Inc. Methods of forming SiC MOSFETs with high inversion layer mobility
US7381620B1 (en) * 2006-03-09 2008-06-03 Spansion Llc Oxygen elimination for device processing
US8432012B2 (en) 2006-08-01 2013-04-30 Cree, Inc. Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same
US7728402B2 (en) * 2006-08-01 2010-06-01 Cree, Inc. Semiconductor devices including schottky diodes with controlled breakdown
EP2631951B1 (en) 2006-08-17 2017-10-11 Cree, Inc. High power insulated gate bipolar transistors
US8835987B2 (en) * 2007-02-27 2014-09-16 Cree, Inc. Insulated gate bipolar transistors including current suppressing layers
KR100942343B1 (ko) * 2008-01-31 2010-02-12 광주과학기술원 저온 고압 열처리를 이용한 비휘발성 메모리 제조방법
US8232558B2 (en) 2008-05-21 2012-07-31 Cree, Inc. Junction barrier Schottky diodes with current surge capability
US8288220B2 (en) 2009-03-27 2012-10-16 Cree, Inc. Methods of forming semiconductor devices including epitaxial layers and related structures
US8294507B2 (en) 2009-05-08 2012-10-23 Cree, Inc. Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits
US8629509B2 (en) * 2009-06-02 2014-01-14 Cree, Inc. High voltage insulated gate bipolar transistors with minority carrier diverter
US8193848B2 (en) 2009-06-02 2012-06-05 Cree, Inc. Power switching devices having controllable surge current capabilities
US8541787B2 (en) * 2009-07-15 2013-09-24 Cree, Inc. High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability
US8354690B2 (en) 2009-08-31 2013-01-15 Cree, Inc. Solid-state pinch off thyristor circuits
US9117739B2 (en) 2010-03-08 2015-08-25 Cree, Inc. Semiconductor devices with heterojunction barrier regions and methods of fabricating same
US8415671B2 (en) 2010-04-16 2013-04-09 Cree, Inc. Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices
US9142662B2 (en) 2011-05-06 2015-09-22 Cree, Inc. Field effect transistor devices with low source resistance
US9029945B2 (en) 2011-05-06 2015-05-12 Cree, Inc. Field effect transistor devices with low source resistance
US9984894B2 (en) 2011-08-03 2018-05-29 Cree, Inc. Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions
US9640617B2 (en) 2011-09-11 2017-05-02 Cree, Inc. High performance power module
US8618582B2 (en) 2011-09-11 2013-12-31 Cree, Inc. Edge termination structure employing recesses for edge termination elements
WO2013036370A1 (en) 2011-09-11 2013-03-14 Cree, Inc. High current density power module comprising transistors with improved layout
US8664665B2 (en) 2011-09-11 2014-03-04 Cree, Inc. Schottky diode employing recesses for elements of junction barrier array
US8680587B2 (en) 2011-09-11 2014-03-25 Cree, Inc. Schottky diode
US9373617B2 (en) 2011-09-11 2016-06-21 Cree, Inc. High current, low switching loss SiC power module
US9378821B1 (en) 2013-01-18 2016-06-28 Cypress Semiconductor Corporation Endurance of silicon-oxide-nitride-oxide-silicon (SONOS) memory cells
JP5788448B2 (ja) * 2013-09-09 2015-09-30 株式会社日立国際電気 半導体装置の製造方法、基板処理装置及びプログラム
CN116741712A (zh) * 2022-03-03 2023-09-12 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构
US12341073B2 (en) 2022-03-03 2025-06-24 Changxin Memory Technologies, Inc. Forming method of semiconductor structure and semiconductor structure

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4584205A (en) * 1984-07-02 1986-04-22 Signetics Corporation Method for growing an oxide layer on a silicon surface
KR920007450B1 (ko) * 1987-07-31 1992-09-01 마쯔시다덴기산교 가부시기가이샤 반도체장치 및 그 제조방법
US4894353A (en) * 1988-04-29 1990-01-16 Advanced Micro Devices, Inc. Method of fabricating passivated tunnel oxide
DD298329A5 (de) * 1988-12-14 1992-02-13 Halbleiterwerk-Gmbh Frankfurt (Oder),De Verfahren zur herstellung von sio tief 2-schichten mit guten durchbruchseigenschaften
US5254506A (en) * 1988-12-20 1993-10-19 Matsushita Electric Industrial Co., Ltd. Method for the production of silicon oxynitride film where the nitrogen concentration at the wafer-oxynitride interface is 8 atomic precent or less
JPH0325728A (ja) * 1989-06-23 1991-02-04 Daicel Chem Ind Ltd 光ディスクトラック位置制御装置
US5198392A (en) * 1989-11-20 1993-03-30 Oki Electric Industry Co., Ltd. Method of forming a nitrided silicon dioxide (SiOx Ny) film
US5057463A (en) * 1990-02-28 1991-10-15 Sgs-Thomson Microelectronics, Inc. Thin oxide structure and method
US5219773A (en) * 1990-06-26 1993-06-15 Massachusetts Institute Of Technology Method of making reoxidized nitrided oxide MOSFETs
JP3041065B2 (ja) * 1991-03-15 2000-05-15 沖電気工業株式会社 絶縁膜形成方法
US5244843A (en) * 1991-12-17 1993-09-14 Intel Corporation Process for forming a thin oxide layer
US5393683A (en) * 1992-05-26 1995-02-28 Micron Technology, Inc. Method of making semiconductor devices having two-layer gate structure
JP3214092B2 (ja) * 1992-09-18 2001-10-02 ソニー株式会社 半導体装置の製法及び半導体製造装置
KR100275712B1 (ko) * 1992-10-12 2000-12-15 윤종용 반도체 소자의 게이트 산화막 형성방법
US5360769A (en) * 1992-12-17 1994-11-01 Micron Semiconductor, Inc. Method for fabricating hybrid oxides for thinner gate devices
US5376593A (en) * 1992-12-31 1994-12-27 Micron Semiconductor, Inc. Method for fabricating stacked layer Si3 N4 for low leakage high capacitance films using rapid thermal nitridation
DE69405438T2 (de) * 1993-03-24 1998-04-02 At & T Corp Verfahren zur Bildung dielektrischer Oxynitridschichten bei der Herstellung integrierter Schaltungen
US5407807A (en) * 1993-04-23 1995-04-18 Daymark Medical Industries, Inc. Method and apparatus for detecting sepsis causation in a catheter
US5397720A (en) * 1994-01-07 1995-03-14 The Regents Of The University Of Texas System Method of making MOS transistor having improved oxynitride dielectric
TW236710B (enExample) * 1994-04-08 1994-12-21
US5478765A (en) * 1994-05-04 1995-12-26 Regents Of The University Of Texas System Method of making an ultra thin dielectric for electronic devices

Also Published As

Publication number Publication date
US5885870A (en) 1999-03-23
JPH09139437A (ja) 1997-05-27
KR970030859A (ko) 1997-06-26

Similar Documents

Publication Publication Date Title
JP4001960B2 (ja) 窒化酸化物誘電体層を有する半導体素子の製造方法
US6319775B1 (en) Nitridation process for fabricating an ONO floating-gate electrode in a two-bit EEPROM device
JP4617574B2 (ja) 不揮発性半導体記憶装置およびその製造方法
US6653683B2 (en) Method and structure for an oxide layer overlying an oxidation-resistant layer
JPH1174485A (ja) 半導体装置およびその製造方法
JPH10163348A (ja) 不揮発性半導体記憶装置の製造方法
JP3558565B2 (ja) 不揮発性半導体装置の製造方法
US6984562B2 (en) Method for forming dielectric layer between gates in flash memory device
US20020168869A1 (en) Method for fabricating an ONO layer
US6962728B2 (en) Method for forming ONO top oxide in NROM structure
JPH03257828A (ja) 半導体装置の製造方法
KR20020002266A (ko) 반도체 장치 및 반도체 장치의 제조 방법
JP3548563B2 (ja) 半導体装置の製造方法
KR100543209B1 (ko) Sonos 구조를 갖는 트랜지스터 제조 방법
JPH07297182A (ja) SiN系絶縁膜の形成方法
US6620705B1 (en) Nitriding pretreatment of ONO nitride for oxide deposition
JPH09153492A (ja) 絶縁膜の形成方法
US7358198B2 (en) Semiconductor device and method for fabricating same
JPH11261065A (ja) シリコンゲートfetの製造方法
KR100799057B1 (ko) 플래시 메모리 소자의 제조 방법
JPH08213611A (ja) 半導体装置の製造方法及び半導体装置
KR100268124B1 (ko) 반도체 소자의 전하저장전극 제조방법
US6858496B1 (en) Oxidizing pretreatment of ONO layer for flash memory
KR100223676B1 (ko) 불휘발성 반도체 메모리 장치에 사용되는 메모리 셀의 층간절연막의 제조방법
JPH0334469A (ja) 不揮発生メモリの製造方法

Legal Events

Date Code Title Description
A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20041217

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20050325

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20050518

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070109

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070409

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070515

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070628

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070724

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070816

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100824

Year of fee payment: 3

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100824

Year of fee payment: 3

RD03 Notification of appointment of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: R3D03

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110824

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110824

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120824

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120824

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130824

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees