KR100275712B1 - 반도체 소자의 게이트 산화막 형성방법 - Google Patents

반도체 소자의 게이트 산화막 형성방법 Download PDF

Info

Publication number
KR100275712B1
KR100275712B1 KR1019920018695A KR920018695A KR100275712B1 KR 100275712 B1 KR100275712 B1 KR 100275712B1 KR 1019920018695 A KR1019920018695 A KR 1019920018695A KR 920018695 A KR920018695 A KR 920018695A KR 100275712 B1 KR100275712 B1 KR 100275712B1
Authority
KR
South Korea
Prior art keywords
oxide film
gate oxide
oxide layer
hto
gate
Prior art date
Application number
KR1019920018695A
Other languages
English (en)
Inventor
양창집
정전교
Original Assignee
윤종용
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윤종용, 삼성전자주식회사 filed Critical 윤종용
Priority to KR1019920018695A priority Critical patent/KR100275712B1/ko
Priority to JP5253241A priority patent/JPH06204209A/ja
Priority to US08/338,816 priority patent/US5470611A/en
Application granted granted Critical
Publication of KR100275712B1 publication Critical patent/KR100275712B1/ko

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
    • C23C16/401—Oxides containing silicon
    • C23C16/402—Silicon dioxide
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/04—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02205—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition
    • H01L21/02208—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si
    • H01L21/02211—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being characterised by the precursor material for deposition the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02233—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer
    • H01L21/02236—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor
    • H01L21/02238—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of the semiconductor substrate or a semiconductor layer group IV semiconductor silicon in uncombined form, i.e. pure silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02255—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by thermal treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28185—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the gate insulator and before the formation of the definitive gate conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28194—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation by deposition, e.g. evaporation, ALD, CVD, sputtering, laser deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31608—Deposition of SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Abstract

본 발명은 MOS소자의 게이트 산화막과 같은 얇은 산화막 형성방법에 관한 것이다.
본 발명은 반도체소자에 사용되는 게이트 산화막의 형성방법에 있어서, 반도체기판상에 저압 화학기상 증착방법을 사용하여 제 1 게이트산화막으로 HTO막을 성장시킨 후, 상기 제 1 게이트 산화막위에 제 2게이트 산화막으로 습식산화막을 성장시켜 게이트 산화막을 형성하는 것을 특징으로 하는 반도체소자의 게이트 산화막 형성방법을 제공한다.
본 발명에 의하면, 우수한 전기적 특성을 갖는 좋은 막질의 게이트 산화막을 형성할 수 있다.

Description

반도체소자의 게이트 산화막 형성방법
제1a도 내지 제1c도는 종래의 산화막과 본 발명의 게이트 산화막 각각의 T.D.D.B특성을 나타낸 것이고,
제2a도 내지 제2c도는 종래의 산화막과 본 발명의 게이트 산화막 각각의 I-V특성을 나타낸 것이고,
제3a도 내지 제3c도는 종래의 산화막과 본 발명의 게이트 산화막 각각의 SIMS분석결과를 나타낸 것이다.
본 발명은 반도체 소자의 절연막 형성방법에 관한 것으로, 반도체 소자의 게이트 산화막 형성방법에 관한 것이다.
반도체 소자의 고집적화에 비례하여 MOS소자의 절연막으로 사용되고 있는 얇은 산화막의 두께 또한 점점 얇아지고 있지만 산화막에 인가되는 전압은 감소되지 않는다. 따라서 이러한 얇은 산화막은 미세한 결합에 민감하게 반응을 하기 때문에 결함에 오래 견디는 특성을 가진 산화막을 만드는 것이 필요하다.
MOS소자에 사용되고 있는 얇은 산화막의 종류는 여러가지이다. 이중, O2만을 이용하거나 또는 O2+ HC1을 이용하여 형성하는 건식산화막에는 미세기공(micropore)이나 보이드(void)와 같은 결함이 존재하는 것으로 알려져 있고, 습식산화막의 경우는 전기적특성은 우수하나, 게이트 산화막으로 사용할 경우, 게이트 전극물질인 폴리실리콘에 POCl3을 주입했을 때 폴리실리콘의 Si원자와 POCl3의 P-이온이 반응하여 Si-P부피팽창의 결과로 게이트 산화막과 폴리실리콘 계면에 스트레스를 주게 되고, 폴리실리콘 하부의 게이트 산화막이 결합력이 약해지면서 계면에 쌓여 있는 P-이온과 게이트 산화막의 Si가 반응하여 결국 게이트 산화막과 폴리실리콘 계면에서 게이트 산화막의 소모가 일어나게 되어 게이트 산화막의 내압 특성이 나빠지는 것으로 알려져 있다. 또한 상기 건식산화막과 습식산화막은 실리콘 배어웨이퍼(Bare wafer)에 존재하는 미세한 피팅(pitting)에 대한 내성이 없다.
따라서 MOS집적소자의 커패시터절연막 또는 게이트산화막에 적용할 경우 산화막 자체의 신뢰성저하에 따라 소자의 수율에 나쁜 영향을 미치게 된다.
또한, HTO(High Temperature Oxide)의 경우는 상기 건식산화막과 습식산화막등의 열산화막과는 달리 실리콘 표면의 조건에 상관없이 증착(Deposition)방법으로 성장시키는 막으로서 하부막에 영향을 주지 않는 산화막으로 널리 사용되고 있으나, T.D.D.B(Time Dependence Dielectric Breakdown Voltage)특성과 I-V특성이 좋지 않은 단점이 있다.
따라서 본 발명은 상기한 종래의 산화막의 단점을 극복한 고품질의 게이트 산화막을 형성함으로써 반도체소자에의 적용시 신뢰성을 향상시키는 것을 그 목적으로 한다.
상기 목적을 달성하기 위해 본 발명에 의한 게이트 산화막 형성방법은 실리콘기판위에 제 1 게이트 산화막으로 LPCVD(Low Pressure Chemical Vapor Deposition)법을 이용하여 성장시킨 HTO막을 형성하고, 이어서 제 1 게이트 산화막위에 제 2 게이트 산화막으로 습식산화를 이용하여 성장시킨 습식산화막을 형성하는 것을 특징으로 한다.
상기 제 1 게이트 산화막은 LPCVD법을 이용하여 압력 0.5Torr, 온도 750℃∼850℃에서 SiH4가스와 N2O가스를 반응시켜 50Å∼200Å 두께로 형성한다.
상기 제 2 게이트 산화막은 800℃∼900℃에서 통상의 석영반응관(Quartz tube)를 이용하여 발열시스템(Pyrogenic system)에서 50Å∼200Å 두께로 형성한다.
상기와 같이 HTO의 장점인 막질의 균일성과 산화막 성장전의 청정상태에 무관하게 성장시킬 수 있는 점, 그리고 증착방식에 따른 실리콘기판 표면에 존재하는 미세한 미팅들을 보상해 줄 수 있는 유리한 면이 있는 제 1 게이트 산화막과, 습식산화막의 장점인 산화막내의 스트레스완화 및 우수한 전기적 특성을 갖는 제 2 게이트 산화막을 조합하여 게이트 산화막을 형성함으로써 게이트 산화막의 막질을 향상시킬 수 있으며, MOS소자에의 적용시 소자의 신뢰성을 확보할 수 있다.
이하, 본 발명의 일실시예를 설명한다.
본 발명의 효과를 명확하게 설명하기 위해 종래의 열산화막과 HTO산화막의 형성방법에 의해 형성된 산화막의 특성을 비교예를 들고, 이를 본 발명의 일실시예에 의한 게이트 산화막 형성방법에 의해 형성된 산화막의 특성과 비교하여 설명하면 다음과 같다.
[비교예 1]
통상의 석영반응관내에서 950℃에서 O2+ HCl(1%)을 이용하여 건식산화하여 200Å두께의 열산화막을 형성한다.
[비교예 2]
통상의 LPCVD 반응관내에서 온도 750℃∼850℃, 압력 0.5Torr, 반응가스 SiH4, N2O를 이용하여 200Å두께의 HTO를 형성한다.
[실시예]
제 1 게이트 산화막으로서 상기 [비교예 2]의 조건과 동일한 조건으로 100Å두께의 HTO를 형성하고, 이어서 상기 형성된 제 1 게이트 산화막인 HTO위에 제 2 게이트 산화막으로서 통상의 석영반응관을 이용한 발열시스템에서 습식분위기로 100Å두께의 습식산화막을 형성한다.
제1a도 및 제1b도는 상기 비교예 1과 비교예 2 및 실시예에 의해 형성된 산화막들의 상온에서의 T.D.D.B특성을 평가하여 나타낸 그래프로서, 제1a도는 비교예 1의 건식산화막의 T.D.D.B특성을 나타내고, 제1b도는 비교예 2의 HTO의 T.D.D.B특성을 나타내며, 제1c도는 실시예의 HTO+습식산화막의 T.D.D.B특성을 나타낸다.
제1a도 내지 제1c도에서 알 수 있는 바와 같이 본 발명의 실시예에 의한 HTO+습식산화막의 T.D.D.B특성이 종래의 건식산화막 및 HTO의 T.D.D.B특성보다 우수하다.
다음에 제2a도 내지 제2b도는 상기 비교예1과 비교예2 및 실시예에 의해 형성된 산화막들의 I-V특성을 나타낸 것으로, 제2a도는 비교예1의 건식산화막의 I-V특성을 나타내고, 제2b도는 비교예2의 HTO의 I-V특성을 나타내며, 제2c도는 실시예의 HTO+습식산화막의 I-V특성을 각각 나타낸다. I+V 특성의 측정장비로는 HP4145B를 사용하였으며, 스위프모드(sweep mode)로 램프스텝 3V, 전류 10μA, 척(Chuck)의 온도 100℃, 측정사이즈 0.004㎠의 조건에서 측정하였다.
상기 제2a도 내지 제2c도에서 알 수 있는 바와 같이 본 발명의 실시예에 의한 HTO+습식산화막이 중래의 건식산화막 및 HTO보다 브레이크다운(Breakdown)되는 전압 및 전류특성이 우수하다.
제3a도 내지 제3b도는 상기 비교예1과 비교예2 및 실시예에 의해 형성된 산화막들의 SIMS(Secondary Ion Mass Spectroscopy)분석결과를 나타낸 것으로, 제3a도는 비교예1의 건식산화막의 SIMS분석결과를 나타내고, 제3b도는 비교예2의 HTO의 SIMS분석결과를 나타내며, 제3c도는 실시예의 HTO+습식산화막의 SIMS분석결과를 각각 나타낸다.
제3a도의 건식산화막의 경우는 Cl-이온의 분포가 산화막내에서 산화막과 실리콘기판의 경계쪽으로 갈수록 많이 존재함을 알 수 있고, 제3b도의 HTO의 경우는 산화막내에 Cl-이온의 분포가 산화막과 실리콘기판의 경계쪽으로 갈수록 그 양이 줄어드는 것을 알 수 있다.
그러나 제3c도의 본 발명의 실시예에 의한 산화막의 경우는 산화막내에 Cl-이온이 골고루 전면적으로 같은 양이 분포함을 알 수 있다.
이상에서 알 수 있는 바와 같이 제 1 게이트 산화막으로 100Å강도 두께의 HTO를 성장시키고 제 1 게이트 산화막상에 제 2 게이트 산화막으로 100Å성도 두께의 습식산화막을 성장시켜 형성한 산화막의 막질이 가장 좋은 특성을 나타낸다. 이는 실리콘기판 표면의 상태와 무관하게 성장시킬 수 있고 실리콘기판 표면의 미세한 피팅등을 완화시킬 수 있으며 막질이 균일한 HTO의 장점과 전기적특성이 우수한 습식산화막의 장점을 조합시켜 산화막을 형성함으로써 나타나는 특징이다.
본 발명에 의한 HTO와 습식산화막의 제 1 및 제 2 게이트 산화막으로 이루어진 산화막을 MOS소자의 얇은 게이트 산화막으로 사용할 경우의 T.D.D.B특성을 종래의 건식산화막 및 HTO와 비교하면 다음과 같다.
이상 상술한 바와 같이 본 발명에 의하면, 우수한 전기적 특성을 갖는 좋은 막질의 게이트 산화막을 형성할 수 있음에 따라 반도체소자에의 적용시 소자의 신뢰성향상을 도모할 수 있다.
이상 상술한 바와 같이 본 발명에 의하면, 우수한 전기적 특성을 갖는 좋은 막질의 게이트 산화막을 형성할 수 있음에 따라 반도체소자에의 적용시 소자의 신뢰성향상을 도모할 수 있다.

Claims (5)

  1. 반도체 기판 상에 저압 화학기상 증착방법을 사용하여 제 1 게이트 산화막으로 HTO(High Temperature Oxide)막을 형성하는 단계; 및 상기 제 1 게이트 산화막 상에 제 2 게이트 산화막으로 습식산화막을 형성하는 단게를 포함하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 형성방법.
  2. 제1항에 있어서, 상기 제 1 게이트 산화막은 700℃∼850℃의 온도범위에서 형성하는 것을 특징으로 하는 반도체소자의 게이트 산화막 형성방법.
  3. 제2항에 있어서, 상기 제 1 게이트 산화막의 두께는 50Å∼200Å임을 특징으로 하는 반도체소자의 게이트 산화막 형성방법.
  4. 제1항에 있어서, 상기 제 2 게이트 산화막은 800℃∼900℃의 온도범위에서 발열시스템(Pyrogenic system)을 이용하여 형성하는 것을 특징으로 하는 반도체소자의 게이트 산화막 형성방법.
  5. 제4항에 있어서, 상기 제 2 게이트 산화막의 두께는 50Å∼200Å임을 특징으로 하는 반도체소자의 게이트 산화막 형성방법.
KR1019920018695A 1992-10-12 1992-10-12 반도체 소자의 게이트 산화막 형성방법 KR100275712B1 (ko)

Priority Applications (3)

Application Number Priority Date Filing Date Title
KR1019920018695A KR100275712B1 (ko) 1992-10-12 1992-10-12 반도체 소자의 게이트 산화막 형성방법
JP5253241A JPH06204209A (ja) 1992-10-12 1993-10-08 半導体素子の酸化膜形成方法
US08/338,816 US5470611A (en) 1992-10-12 1994-11-10 Method for forming an oxide film of a semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920018695A KR100275712B1 (ko) 1992-10-12 1992-10-12 반도체 소자의 게이트 산화막 형성방법

Publications (1)

Publication Number Publication Date
KR100275712B1 true KR100275712B1 (ko) 2000-12-15

Family

ID=19340986

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920018695A KR100275712B1 (ko) 1992-10-12 1992-10-12 반도체 소자의 게이트 산화막 형성방법

Country Status (3)

Country Link
US (1) US5470611A (ko)
JP (1) JPH06204209A (ko)
KR (1) KR100275712B1 (ko)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5712177A (en) * 1994-08-01 1998-01-27 Motorola, Inc. Method for forming a reverse dielectric stack
JP4001960B2 (ja) * 1995-11-03 2007-10-31 フリースケール セミコンダクター インコーポレイテッド 窒化酸化物誘電体層を有する半導体素子の製造方法
US5646074A (en) * 1995-12-15 1997-07-08 Mosel Vitelic, Inc. Method of forming gate oxide for field effect transistor
US6211098B1 (en) 1999-02-18 2001-04-03 Taiwan Semiconductor Manufacturing Company Wet oxidation method for forming silicon oxide dielectric layer
US6706577B1 (en) 1999-04-26 2004-03-16 Taiwan Semiconductor Manufacturing Company Formation of dual gate oxide by two-step wet oxidation
DE10050009A1 (de) * 2000-10-10 2002-04-18 Forschungszentrum Juelich Gmbh Keramischer Werkstoff als Korrosionsschutz
KR100780643B1 (ko) * 2006-06-29 2007-11-29 주식회사 하이닉스반도체 반도체 소자의 소자 분리막 형성방법
CN112992672B (zh) * 2019-12-16 2022-10-14 山东有研半导体材料有限公司 一种硅基二氧化硅背封薄膜的制备方法
CN116741712A (zh) * 2022-03-03 2023-09-12 长鑫存储技术有限公司 半导体结构的形成方法及半导体结构

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910020809A (ko) * 1990-05-10 1991-12-20 문정환 누설전류가 낮은 단일층 질화막의 제조방법

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07118505B2 (ja) * 1990-12-28 1995-12-18 信越半導体株式会社 誘電体分離基板の製造方法

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910020809A (ko) * 1990-05-10 1991-12-20 문정환 누설전류가 낮은 단일층 질화막의 제조방법

Also Published As

Publication number Publication date
US5470611A (en) 1995-11-28
JPH06204209A (ja) 1994-07-22

Similar Documents

Publication Publication Date Title
US4851370A (en) Fabricating a semiconductor device with low defect density oxide
Parsons et al. Low hydrogen content stoichiometric silicon nitride films deposited by plasma‐enhanced chemical vapor deposition
Kamiyama et al. Ultrathin tantalum oxide capacitor dielectric layers fabricated using rapid thermal nitridation prior to low pressure chemical vapor deposition
KR19990064143A (ko) 실리콘 카바이드 상의 산화막 결함의 감소방법
US4725560A (en) Silicon oxynitride storage node dielectric
US5153701A (en) Semiconductor device with low defect density oxide
Faraone et al. Characterization of thermally oxidized n+ polycrystalline silicon
KR100275712B1 (ko) 반도체 소자의 게이트 산화막 형성방법
Shiono et al. Surface State Formation during Long-Term Bias-Temperature Stress Aging of Thin SiO2–Si Interfaces
JPH06101466B2 (ja) シリコン層上に２酸化シリコンの絶縁誘電体層を作る方法
Yamada Reliability of ultimate ultrathin silicon oxide films produced by the continuous ultradry process
Moslehi et al. Interfacial and breakdown characteristics of MOS devices with rapidly grown ultrathin SiO 2 gate insulators
US6211098B1 (en) Wet oxidation method for forming silicon oxide dielectric layer
Chatterjee et al. Effect of the stack layer on the electrical properties of Ta2O5 gate dielectrics deposited on strained-Si0. 82Ge0. 18 substrates
Yamada Continuous ultra‐dry process for enhancing the reliability of ultrathin silicon oxide films in metal–oxide semiconductors
Punchaipetch et al. Growth and characterization of hafnium silicate films prepared by UV/ozone oxidation
Sturm et al. Limited reaction processing: In-situ metal—oxide—semiconductor capacitors
Peters Low temperature photo-CVD oxide processing for semiconductor device applications
Bashir et al. Degradation of insulators in silicon selective epitaxial growth (SEG) ambient
Gaind et al. Preparation and Properties of SiO2 Films from SiH4‐CO 2‐H 2
KR100244400B1 (ko) 유전체막 형성방법
Fultz et al. A Nitrided-oxide Dielectric for Epitaxial Lateral Overgrowth Applications
JPH06302591A (ja) 絶縁被膜および半導体装置の作製方法
Queirolo et al. Polycrystalline Silicon Oxidation Kinetics and Si/SiO2 Interface Width
Lam Measurements of Commercial MIS Capacitors by the Surface-Photovoltage Methods

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
AMND Amendment
E601 Decision to refuse application
J201 Request for trial against refusal decision
AMND Amendment
E902 Notification of reason for refusal
B701 Decision to grant
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20090914

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee