JP3988227B2 - 半導体チップ搭載用基板の製造法および半導体装置 - Google Patents

半導体チップ搭載用基板の製造法および半導体装置 Download PDF

Info

Publication number
JP3988227B2
JP3988227B2 JP33005297A JP33005297A JP3988227B2 JP 3988227 B2 JP3988227 B2 JP 3988227B2 JP 33005297 A JP33005297 A JP 33005297A JP 33005297 A JP33005297 A JP 33005297A JP 3988227 B2 JP3988227 B2 JP 3988227B2
Authority
JP
Japan
Prior art keywords
metal layer
semiconductor chip
layer
manufacturing
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33005297A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11163207A5 (https=
JPH11163207A (ja
Inventor
英博 中村
聡夫 山崎
茂樹 市村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Showa Denko Materials Co Ltd, Resonac Corp filed Critical Hitachi Chemical Co Ltd
Priority to JP33005297A priority Critical patent/JP3988227B2/ja
Publication of JPH11163207A publication Critical patent/JPH11163207A/ja
Publication of JPH11163207A5 publication Critical patent/JPH11163207A5/ja
Application granted granted Critical
Publication of JP3988227B2 publication Critical patent/JP3988227B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP33005297A 1997-12-01 1997-12-01 半導体チップ搭載用基板の製造法および半導体装置 Expired - Fee Related JP3988227B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33005297A JP3988227B2 (ja) 1997-12-01 1997-12-01 半導体チップ搭載用基板の製造法および半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33005297A JP3988227B2 (ja) 1997-12-01 1997-12-01 半導体チップ搭載用基板の製造法および半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006293148A Division JP4428376B2 (ja) 2006-10-27 2006-10-27 半導体チップ搭載用基板の製造法

Publications (3)

Publication Number Publication Date
JPH11163207A JPH11163207A (ja) 1999-06-18
JPH11163207A5 JPH11163207A5 (https=) 2005-07-14
JP3988227B2 true JP3988227B2 (ja) 2007-10-10

Family

ID=18228248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33005297A Expired - Fee Related JP3988227B2 (ja) 1997-12-01 1997-12-01 半導体チップ搭載用基板の製造法および半導体装置

Country Status (1)

Country Link
JP (1) JP3988227B2 (https=)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW522530B (en) * 1999-08-02 2003-03-01 Toyo Kohan Co Ltd Semiconductor package unit
TW512467B (en) 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
JP3752949B2 (ja) 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
JP4023076B2 (ja) * 2000-07-27 2007-12-19 富士通株式会社 表裏導通基板及びその製造方法
JP2002050870A (ja) * 2000-08-01 2002-02-15 Hitachi Chem Co Ltd 接続基板とその接続基板を用いた多層配線板と半導体パッケージ用基板と半導体パッケージ並びに接続基板の製造方法とその方法を用いた多層配線板の製造方法と半導体パッケージ用基板の製造方法と半導体パッケージの製造方法
KR100695303B1 (ko) * 2000-10-31 2007-03-14 삼성전자주식회사 제어 신호부 및 그 제조 방법과 이를 포함하는 액정 표시장치 및 그 제조 방법
JP4586058B2 (ja) * 2001-03-28 2010-11-24 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 層間接続部材
JP3682500B2 (ja) * 2001-04-16 2005-08-10 日本重化学工業株式会社 プリント配線基板、及び、プリント配線基板の製造方法
JPWO2003021668A1 (ja) * 2001-08-31 2004-12-24 日立化成工業株式会社 配線基板、半導体装置及びそれらの製造方法
WO2003100850A1 (en) * 2002-05-28 2003-12-04 Hitachi Chemical Co., Ltd. Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them
JP2004079773A (ja) * 2002-08-19 2004-03-11 Taiyo Yuden Co Ltd 多層プリント配線板及びその製造方法
US20060286301A1 (en) * 2003-09-12 2006-12-21 National Institute Of Advanced Industrial Science Substrates and method of manufacturing same
JP2005340372A (ja) * 2004-05-25 2005-12-08 Toyo Ink Mfg Co Ltd 配線回路基板用の積層体ユニットの製造方法
JP2006147810A (ja) * 2004-11-19 2006-06-08 Casio Comput Co Ltd 半導体装置およびその製造方法
JP4798557B2 (ja) * 2005-01-31 2011-10-19 独立行政法人産業技術総合研究所 プローブカード、およびその製造方法。
US7759782B2 (en) * 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
JP4407702B2 (ja) * 2007-02-09 2010-02-03 富士通株式会社 表裏導通基板の製造方法および表裏導電基板
KR100866577B1 (ko) * 2007-09-28 2008-11-03 삼성전기주식회사 인쇄회로기판의 층간 도통방법
JP4603080B2 (ja) * 2009-01-13 2010-12-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板
JP5152601B2 (ja) * 2010-06-01 2013-02-27 日立化成工業株式会社 薄板状物品を用いた接続基板の製造方法と多層配線板の製造方法
US9365947B2 (en) 2013-10-04 2016-06-14 Invensas Corporation Method for preparing low cost substrates
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects

Also Published As

Publication number Publication date
JPH11163207A (ja) 1999-06-18

Similar Documents

Publication Publication Date Title
JP3988227B2 (ja) 半導体チップ搭載用基板の製造法および半導体装置
US7923367B2 (en) Multilayer wiring substrate mounted with electronic component and method for manufacturing the same
JP3173410B2 (ja) パッケージ基板およびその製造方法
KR100908759B1 (ko) 범프레스 적층식 상호 연결 층을 갖는 초소형 전자 패키지
CN100417310C (zh) 具有散热元件的印刷电路板,其制作方法和包含它的器件
JP2003522401A (ja) 積層型集積回路パッケージ
JP3533284B2 (ja) 半導体装置用基板及びその製造方法並びに半導体装置
JP2003007916A (ja) 回路装置の製造方法
JP3879135B2 (ja) 転写配線支持部材及びそれを使用した半導体パッケージの製造法
JP2003007917A (ja) 回路装置の製造方法
JP2004193297A (ja) ウェハレベルパッケージおよびその製造方法
US6432748B1 (en) Substrate structure for semiconductor package and manufacturing method thereof
KR100346899B1 (ko) 반도체장치 및 그 제조방법
JP2002118204A (ja) 半導体装置、並びに半導体搭載用基板及びその製造方法
JP2004119730A (ja) 回路装置の製造方法
CN101958292B (zh) 印刷电路板、封装件及其制造方法
JP3780688B2 (ja) Ｃｓｐ用基板の製造法
JP3616742B2 (ja) 半導体パッケージ用チップ支持基板
JP4428376B2 (ja) 半導体チップ搭載用基板の製造法
JP2000200855A (ja) Ｐｇａ型配線基板及びその製造方法並びに半導体装置
JPH0982835A (ja) 回路基板および多層回路基板
JP2002270726A (ja) 半導体装置およびその製造方法
JPH06177275A (ja) 放熱性プラスチックｉｃチップキャリア
JPH0358455A (ja) 半導体パッケージ
JPH08330472A (ja) 半導体装置とその製造方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20041115

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20041115

RD02 Notification of acceptance of power of attorney

Free format text: JAPANESE INTERMEDIATE CODE: A7422

Effective date: 20041115

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060821

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060829

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061027

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061205

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070205

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20070306

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070501

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20070521

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070626

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070709

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100727

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100727

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110727

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110727

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120727

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130727

Year of fee payment: 6

LAPS Cancellation because of no payment of annual fees