JP3949193B2 - 絶縁ゲイト型半導体装置 - Google Patents
絶縁ゲイト型半導体装置 Download PDFInfo
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- JP3949193B2 JP3949193B2 JP23255296A JP23255296A JP3949193B2 JP 3949193 B2 JP3949193 B2 JP 3949193B2 JP 23255296 A JP23255296 A JP 23255296A JP 23255296 A JP23255296 A JP 23255296A JP 3949193 B2 JP3949193 B2 JP 3949193B2
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- insulated gate
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/213—Channel regions of field-effect devices
- H10D62/221—Channel regions of field-effect devices of FETs
- H10D62/235—Channel regions of field-effect devices of FETs of IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
- H10D62/815—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW]
- H10D62/8181—Structures having no potential periodicity in the vertical direction, e.g. lateral superlattices or lateral surface superlattices [LSS]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
- H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
- H10D84/401—Combinations of FETs or IGBTs with BJTs
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Nanotechnology (AREA)
- Chemical & Material Sciences (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Mathematical Physics (AREA)
- Theoretical Computer Science (AREA)
- Crystallography & Structural Chemistry (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23255296A JP3949193B2 (ja) | 1996-08-13 | 1996-08-13 | 絶縁ゲイト型半導体装置 |
| US08/907,579 US6218714B1 (en) | 1996-08-13 | 1997-08-08 | Insulated gate semiconductor device and method of manufacturing the same |
| KR1019970039449A KR100443436B1 (ko) | 1996-08-13 | 1997-08-13 | 절연게이트형반도체장치 |
| US09/811,238 US6617647B2 (en) | 1996-08-13 | 2001-03-16 | Insulated gate semiconductor device and method of manufacturing the same |
| KR1020020047936A KR100453400B1 (ko) | 1996-08-13 | 2002-08-13 | 반도체 장치 제작 방법 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23255296A JP3949193B2 (ja) | 1996-08-13 | 1996-08-13 | 絶縁ゲイト型半導体装置 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006344148A Division JP4896699B2 (ja) | 2006-12-21 | 2006-12-21 | 絶縁ゲイト型半導体装置およびその作製方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH1065163A JPH1065163A (ja) | 1998-03-06 |
| JPH1065163A5 JPH1065163A5 (enExample) | 2004-10-21 |
| JP3949193B2 true JP3949193B2 (ja) | 2007-07-25 |
Family
ID=16941122
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23255296A Expired - Fee Related JP3949193B2 (ja) | 1996-08-13 | 1996-08-13 | 絶縁ゲイト型半導体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US6218714B1 (enExample) |
| JP (1) | JP3949193B2 (enExample) |
| KR (2) | KR100443436B1 (enExample) |
Families Citing this family (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4103968B2 (ja) * | 1996-09-18 | 2008-06-18 | 株式会社半導体エネルギー研究所 | 絶縁ゲイト型半導体装置 |
| US6590230B1 (en) | 1996-10-15 | 2003-07-08 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| US6118148A (en) | 1996-11-04 | 2000-09-12 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method thereof |
| JP4017706B2 (ja) | 1997-07-14 | 2007-12-05 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US6686623B2 (en) | 1997-11-18 | 2004-02-03 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile memory and electronic apparatus |
| JP4236722B2 (ja) * | 1998-02-05 | 2009-03-11 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| US7015546B2 (en) * | 2000-02-23 | 2006-03-21 | Semiconductor Research Corporation | Deterministically doped field-effect devices and methods of making same |
| US6724037B2 (en) * | 2000-07-21 | 2004-04-20 | Semiconductor Energy Laboratory Co., Ltd. | Nonvolatile memory and semiconductor device |
| JP4275336B2 (ja) | 2001-11-16 | 2009-06-10 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| KR100493018B1 (ko) * | 2002-06-12 | 2005-06-07 | 삼성전자주식회사 | 반도체 장치의 제조방법 |
| US7052966B2 (en) * | 2003-04-09 | 2006-05-30 | Newport Fab, Llc | Deep N wells in triple well structures and method for fabricating same |
| US7829394B2 (en) * | 2005-05-26 | 2010-11-09 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and manufacturing method of the same |
| US8304783B2 (en) * | 2009-06-03 | 2012-11-06 | Cree, Inc. | Schottky diodes including polysilicon having low barrier heights and methods of fabricating the same |
| US20130137235A1 (en) * | 2010-07-15 | 2013-05-30 | University Of Electronic Science And Technology Of China | Mos transistor using stress concentration effect for enhancing stress in channel area |
| JP5897910B2 (ja) | 2011-01-20 | 2016-04-06 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
| TWI491050B (zh) | 2011-11-25 | 2015-07-01 | Sony Corp | 電晶體，顯示器及電子裝置 |
| FR3011678B1 (fr) * | 2013-10-07 | 2017-01-27 | St Microelectronics Crolles 2 Sas | Procede de relaxation des contraites mecaniques transversales dans la region active d'un transistor mos, et circuit integre correspondant |
| JP2016029719A (ja) * | 2014-07-17 | 2016-03-03 | 出光興産株式会社 | 薄膜トランジスタ |
| US20210036163A1 (en) * | 2018-03-09 | 2021-02-04 | Sakai Display Products Corporation | Thin film transistor and production method therefor |
| US20200194555A1 (en) * | 2018-12-18 | 2020-06-18 | United Microelectronics Corp. | Semiconductor device with reduced floating body effects and fabrication method thereof |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS55151363A (en) * | 1979-05-14 | 1980-11-25 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Mos semiconductor device and fabricating method of the same |
| US5350940A (en) * | 1984-02-02 | 1994-09-27 | Fastran, Inc. | Enhanced mobility metal oxide semiconductor devices |
| US4697198A (en) * | 1984-08-22 | 1987-09-29 | Hitachi, Ltd. | MOSFET which reduces the short-channel effect |
| IT1213234B (it) * | 1984-10-25 | 1989-12-14 | Sgs Thomson Microelectronics | Procedimento perfezionato per la fabbricazione di dispositivi a semiconduttore dmos. |
| JPS61256769A (ja) * | 1985-05-10 | 1986-11-14 | Toshiba Corp | 半導体装置 |
| EP0287658A1 (en) | 1986-10-27 | 1988-10-26 | Hughes Aircraft Company | Striped-channel transistor and method of forming the same |
| JPH0231464A (ja) * | 1988-07-21 | 1990-02-01 | Mitsubishi Electric Corp | 半導体装置 |
| JPH02105467A (ja) * | 1988-10-13 | 1990-04-18 | Nec Corp | Ｍｏｓ型半導体装置 |
| JPH02159070A (ja) * | 1988-12-13 | 1990-06-19 | Matsushita Electric Ind Co Ltd | 半導体装置とその製造方法 |
| JPH02196468A (ja) * | 1989-01-25 | 1990-08-03 | Nec Corp | 半導体装置 |
| JPH0738447B2 (ja) * | 1989-02-02 | 1995-04-26 | 松下電器産業株式会社 | Ｍｏｓ型半導体装置 |
| JPH036863A (ja) * | 1989-06-05 | 1991-01-14 | Takehide Shirato | 半導体装置 |
| US5210437A (en) * | 1990-04-20 | 1993-05-11 | Kabushiki Kaisha Toshiba | MOS device having a well layer for controlling threshold voltage |
| JPH05283687A (ja) * | 1992-03-31 | 1993-10-29 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
-
1996
- 1996-08-13 JP JP23255296A patent/JP3949193B2/ja not_active Expired - Fee Related
-
1997
- 1997-08-08 US US08/907,579 patent/US6218714B1/en not_active Expired - Fee Related
- 1997-08-13 KR KR1019970039449A patent/KR100443436B1/ko not_active Expired - Fee Related
-
2001
- 2001-03-16 US US09/811,238 patent/US6617647B2/en not_active Expired - Lifetime
-
2002
- 2002-08-13 KR KR1020020047936A patent/KR100453400B1/ko not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| KR19980018784A (ko) | 1998-06-05 |
| US6218714B1 (en) | 2001-04-17 |
| KR100443436B1 (ko) | 2004-10-20 |
| US20010023105A1 (en) | 2001-09-20 |
| JPH1065163A (ja) | 1998-03-06 |
| KR100453400B1 (ko) | 2004-10-20 |
| US6617647B2 (en) | 2003-09-09 |
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