JP3746719B2 - フリップチップ実装方法 - Google Patents

フリップチップ実装方法 Download PDF

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Publication number
JP3746719B2
JP3746719B2 JP2002075863A JP2002075863A JP3746719B2 JP 3746719 B2 JP3746719 B2 JP 3746719B2 JP 2002075863 A JP2002075863 A JP 2002075863A JP 2002075863 A JP2002075863 A JP 2002075863A JP 3746719 B2 JP3746719 B2 JP 3746719B2
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JP
Japan
Prior art keywords
bump
gold
circuit board
chip mounting
semiconductor element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2002075863A
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English (en)
Japanese (ja)
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JP2003273148A5 (https=
JP2003273148A (ja
Inventor
智之 畠山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Olympus Corp
Original Assignee
Olympus Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Olympus Corp filed Critical Olympus Corp
Priority to JP2002075863A priority Critical patent/JP3746719B2/ja
Publication of JP2003273148A publication Critical patent/JP2003273148A/ja
Publication of JP2003273148A5 publication Critical patent/JP2003273148A5/ja
Application granted granted Critical
Publication of JP3746719B2 publication Critical patent/JP3746719B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts

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  • Wire Bonding (AREA)
JP2002075863A 2002-03-19 2002-03-19 フリップチップ実装方法 Expired - Fee Related JP3746719B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002075863A JP3746719B2 (ja) 2002-03-19 2002-03-19 フリップチップ実装方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002075863A JP3746719B2 (ja) 2002-03-19 2002-03-19 フリップチップ実装方法

Publications (3)

Publication Number Publication Date
JP2003273148A JP2003273148A (ja) 2003-09-26
JP2003273148A5 JP2003273148A5 (https=) 2005-06-02
JP3746719B2 true JP3746719B2 (ja) 2006-02-15

Family

ID=29204824

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002075863A Expired - Fee Related JP3746719B2 (ja) 2002-03-19 2002-03-19 フリップチップ実装方法

Country Status (1)

Country Link
JP (1) JP3746719B2 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354967B2 (en) 2016-09-29 2019-07-16 Samsung Electronics Co., Ltd. Metal pillar in a film-type semiconductor package
US20220045242A1 (en) * 2020-08-04 2022-02-10 Japan Display Inc. Led module, method for manufacturing led module, and circuit board

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006318974A (ja) * 2005-05-10 2006-11-24 Toshiba Components Co Ltd バンプ構造を用いた半導体素子及びその製造方法
CN111670488B (zh) 2018-02-01 2021-08-17 新唐科技日本株式会社 半导体装置

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354967B2 (en) 2016-09-29 2019-07-16 Samsung Electronics Co., Ltd. Metal pillar in a film-type semiconductor package
US10867948B2 (en) 2016-09-29 2020-12-15 Samsung Electronics Co., Ltd. Metal pillar in a film-type seconductor package
US20220045242A1 (en) * 2020-08-04 2022-02-10 Japan Display Inc. Led module, method for manufacturing led module, and circuit board
US12183853B2 (en) * 2020-08-04 2024-12-31 Japan Display Inc. LED module, method for manufacturing LED module, and circuit board

Also Published As

Publication number Publication date
JP2003273148A (ja) 2003-09-26

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