JP4934831B2 - 半導体パッケージの製造方法 - Google Patents
半導体パッケージの製造方法 Download PDFInfo
- Publication number
- JP4934831B2 JP4934831B2 JP2008267440A JP2008267440A JP4934831B2 JP 4934831 B2 JP4934831 B2 JP 4934831B2 JP 2008267440 A JP2008267440 A JP 2008267440A JP 2008267440 A JP2008267440 A JP 2008267440A JP 4934831 B2 JP4934831 B2 JP 4934831B2
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- Japan
- Prior art keywords
- bump
- solder
- chip
- jig
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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- 239000004065 semiconductor Substances 0.000 title claims description 64
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 229910000679 solder Inorganic materials 0.000 claims description 142
- 238000000034 method Methods 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 33
- 238000003825 pressing Methods 0.000 claims description 6
- 238000004806 packaging method and process Methods 0.000 claims description 4
- 230000008569 process Effects 0.000 description 17
- 238000010586 diagram Methods 0.000 description 12
- 239000002184 metal Substances 0.000 description 7
- 238000007747 plating Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005304 joining Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
- 238000000844 transformation Methods 0.000 description 1
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Description
14 回路パターン
16 電極パッド
18 ハンダバンプ
20 ドーム状の溝
22 治具
24 ポストバンプ
26 半導体チップ
28 針型バンプ
30 スクラッチ
32 円錐状凸部
34 噴火口状の凸部
Claims (1)
- チップバンプの形成された半導体チップをパッケージ基板に実装してパッケージする方法であって、
電極パッドが形成された回路基板を提供する段階と、
前記電極パッドにハンダバンプを形成する段階と、
前記チップバンプの形状に対応して凸部または凹部が形成された治具の前記凸部または前記凹部が前記ハンダバンプに対向するようにして、前記治具を前記回路基板に熱加圧する段階と、
前記治具を離型する段階と、
前記チップバンプと前記ハンダバンプとが対応するようにして前記半導体チップを前記回路基板に実装する段階と、
前記ハンダバンプをリフローして前記チップバンプと前記ハンダバンプとをボンディングする段階と、
を含み、
前記チップバンプの先端が平らなポストバンプであり、
前記凹部が、ドーム状の溝であることを特徴とする半導体パッケージの製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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KR10-2008-0019796 | 2008-03-03 | ||
KR1020080019796A KR20090094698A (ko) | 2008-03-03 | 2008-03-03 | 패키지 기판 제조방법 및 반도체 패키지 제조방법 |
Publications (2)
Publication Number | Publication Date |
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JP2009212492A JP2009212492A (ja) | 2009-09-17 |
JP4934831B2 true JP4934831B2 (ja) | 2012-05-23 |
Family
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Application Number | Title | Priority Date | Filing Date |
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JP2008267440A Expired - Fee Related JP4934831B2 (ja) | 2008-03-03 | 2008-10-16 | 半導体パッケージの製造方法 |
Country Status (3)
Country | Link |
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JP (1) | JP4934831B2 (ja) |
KR (1) | KR20090094698A (ja) |
TW (1) | TW201001576A (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2013098701A (ja) * | 2011-10-31 | 2013-05-20 | Daishinku Corp | 圧電振動デバイスおよび圧電振動デバイスの製造方法 |
JP6623508B2 (ja) | 2014-09-30 | 2019-12-25 | 日亜化学工業株式会社 | 光源及びその製造方法、実装方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06232205A (ja) * | 1992-12-11 | 1994-08-19 | Fujitsu Ltd | 半導体装置の実装方法と半導体装置 |
JP4570898B2 (ja) * | 1998-03-12 | 2010-10-27 | 富士通セミコンダクター株式会社 | コンタクタ製造装置 |
JP4159213B2 (ja) * | 1999-11-17 | 2008-10-01 | 日本アビオニクス株式会社 | フリップチップ実装方法 |
JP2005191132A (ja) * | 2003-12-24 | 2005-07-14 | Ngk Spark Plug Co Ltd | 半田バンプ平坦化装置 |
JP2006351589A (ja) * | 2005-06-13 | 2006-12-28 | Sony Corp | 半導体チップ、電子装置及びその製造方法 |
JP4661657B2 (ja) * | 2006-03-30 | 2011-03-30 | 株式会社デンソー | バンプ接合体の製造方法 |
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2008
- 2008-03-03 KR KR1020080019796A patent/KR20090094698A/ko not_active Application Discontinuation
- 2008-10-16 JP JP2008267440A patent/JP4934831B2/ja not_active Expired - Fee Related
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2009
- 2009-03-02 TW TW098106715A patent/TW201001576A/zh unknown
Also Published As
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JP2009212492A (ja) | 2009-09-17 |
TW201001576A (en) | 2010-01-01 |
KR20090094698A (ko) | 2009-09-08 |
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