TW201001576A - Manufacturing method of package board and manufacturing method of semiconductor package - Google Patents

Manufacturing method of package board and manufacturing method of semiconductor package Download PDF

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Publication number
TW201001576A
TW201001576A TW098106715A TW98106715A TW201001576A TW 201001576 A TW201001576 A TW 201001576A TW 098106715 A TW098106715 A TW 098106715A TW 98106715 A TW98106715 A TW 98106715A TW 201001576 A TW201001576 A TW 201001576A
Authority
TW
Taiwan
Prior art keywords
bump
wafer
manufacturing
solder
stage
Prior art date
Application number
TW098106715A
Other languages
Chinese (zh)
Inventor
Suk-Hyeon Cho
Ho-Jin Kim
Jae-Ean Lee
Young-Kwan Lee
Seung-Ho Beak
Original Assignee
Samsung Electro Mech
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electro Mech filed Critical Samsung Electro Mech
Publication of TW201001576A publication Critical patent/TW201001576A/en

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    • H—ELECTRICITY
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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

A method of manufacturing a package board and a method of manufacturing a semiconductor package are disclosed. The method of manufacturing a package board, on which a semiconductor chip having a chip bump is mounted, in accordance with an embodiment of the present invention can include: loading a circuit board, on which an electrode pad is formed; forming a solder bump on the electrode pad; thermo-pressing a jig on the board such that relievos or intaglios, which are formed on the jig in correspondence with the shape of the chip bump, face the solder bump; and removing the jig. The method can improve the bonding reliability between a chip bump of a semiconductor chip and a solder bump of a package board.

Description

201001576 六、發明說明： 【發明所屬之技術領域】 本發明係關於封裝基板的製造方法以及半導體封裝的 製造方法。 【先前技術】 覆晶封裝（Flip chip packaging)係指，將如半導體晶 片般的電子元件附著於電路基板上之際’不使用如導線般 的追加的連結構造’而於半導體晶片、電路基板的電極圖 樣上，熔接銲錫凸塊，接合半導體晶片與電路基板來實行 封裝的方式。 最近，因對於大容量資料的高速處理的要求、或是電 子製品的輕薄短小化，導致電子元件的凸塊的尺寸以及間 距（Bump pitch)不斷地變小。隨著如此的凸塊尺寸的小 型化，控制各凸塊的高度係變得重要，變得嚴格起來。 第1圖〜第4圖係表示依據先前技術之半導體晶片封 裝的製造方法的製程圖。若仔細觀察依據先前技術之半導 體封裝的製造方法，則首先，如帛i圖所示，於作為電路 基板102的電路圖樣1〇4的一部分而被形成的電極墊1〇6 上，熔接銲錫凸塊1 08。此時，被熔接於電極墊丨〇6上的 銲錫凸塊1〇8的尺寸、高度’並沒有一定。接著，如第2 圖所不’使用平坦的壓印（c〇ining)用加壓板U〇，加壓 鮮锡凸塊108的前端，使銲錫凸塊108的前端變平坦，而 201001576 使高度-定。接著，如第3圖所示，使加壓板ιι〇分離， 而於電路基;^ 102丨形成其前端平坦且高度一定的録錫凸 塊108接著，如第4圖所示，以使半導體晶片的凸塊丄14 與電路基板102的銲錫凸塊1〇8對應的方式，將半導體晶 片112載置於電路基板102上。接著，使鮮錫凸塊ι〇8迴 焊（reHow)’而將半導體晶片112接合於電路基板1〇2上。 但是，依據先前技術之半導體晶片封裝的製造方法， f ：目為最近電子元件的凸塊的尺寸、間距等有變小的傾向， 所以在半V體晶片的凸塊與電路基板的銲錫凸塊之間，會 有接合可靠性低的問題點。 特別是，將半導體晶片的凸塊，作成電鍍金屬而形成 的柱狀凸塊型式時，半導體晶片的凸塊的前端以及電路基 板的銲錫凸塊的前端的兩者，皆被形成平坦面，因此當使 半導體晶片的凸塊與電路基板的銲錫凸塊互相對應而進行 迴焊製程之際，於半導體晶片的凸塊與電路基板的銲錫凸 (. 塊的接合面，會發生空隙（Air void)，而有接合可靠性顯 著降低的問題點。 【發明内容】 [發明所欲解決的問題] 有鑑於如此的先前技術的問題點，本發明的目的是提 供一種封裝基板的製造方法及半導體封裝的製造方法，可 於半導體晶片的晶片凸塊與封裝基板的銲錫凸塊之間，使 4 201001576 接合可靠性提高的。 [解決問題之技術手段] 右依據本發明的一實施形態，則可提供一種封裝基板 的衣以方去，其係製造封裝基板（要被構裝已形成有晶片凸 東之半導體B日片）的方法，包含：提供已形成有電極塾之電 路基板的階段；在電極塾上形成銲錫凸塊（solder bump) 的階& ’對應晶片凸塊的形狀，冑已形成有凸部或凹部之 治具的凸部或凹部，面對鲜锡凸土鬼，而將治具熱加壓於基 板上的階段；以及使治具脫模的階段。 在使治具脫模的階段以前，更可包含使銲錫凸塊硬化 的階段。 曰形成銲錫凸塊的階段，可包含：將遮罩(已形成有對應 錫凸鬼之開口部），載置於電路基板上的階段；擠壓錫膏 而將其壓入開口部的階段；迴焊（reflow )錫膏的階段； 以及除去遮罩的階段。 BB片凸塊，可為前端平坦的柱狀凸塊；治具的凹部， 可為圓頂狀的溝的形態。 另外，晶片凸塊，可為前端平坦的柱狀凸塊；治具的 凹’可為到痕（scratch)狀的溝。 晶片凸塊，可為在前端已形成有圓錐狀突起之針型凸 塊’·治具的凸部’可為對應突起的圓錐狀凸部。 晶片凸塊’係前端平坦的柱狀凸塊時，治具的凸部， 可為中央部凹陷的喷火口狀的凸部。 另外右依據本發明的其他的實施形態，則可提供一 201001576 種半導體封裝的製造方法，Α 導俨”姓壯 -係將已形成有晶片凸塊之半 Τ體曰曰片’構裝於封褒基板上來實行封裝的方法，包含： 提供已形成有電極墊之雷玖Α |之电路基板的階段；在電極塾上形成 知·錫凸塊的階段：斜_處a μ π % , ,, 對應曰曰片凸塊的形狀，使已形成有凸部 U之治具的凸部或凹部，面對銲錫凸力，而將治具熱 :壓於基板上的階段；使治具脫模的階段；使晶片凸塊與 知錫凸塊對應’而將半導I# S g# 竹干导骽日日片構裝於電路基板上的階 段；以及迴焊銲錫凸塊，來接合晶片凸塊與鮮錫凸塊的階 段0 在使治具脫模的階段以前，更可包含使辉錫凸塊硬化 的階段。 形成上述銲錫凸塊的階段，可包含：將遮罩（已形成有 對應銲錫凸塊之開口部），載置於電路基板上的階段；擠壓 錫膏而將其壓人開Π部㈣段；迴焊錫#的階段；以及除 去遮罩的階段。 晶片凸塊，可為前端平坦的柱狀凸塊；治具的凹部， 可為圓頂狀的溝。 另外，晶片凸塊，係前端平坦的柱狀凸塊時，治具的 凹部可為刮痕狀的溝。 晶片凸塊’可為在前端已形成有圓錐狀突起之針型凸 塊’治具的凸部，可為對應突起的圓錐狀凸部。 B曰片凸境，係剛端平坦的柱狀凸塊時，治具的凸部， 可為中央部凹陷的喷火口狀的凸部。 201001576 [功效] 若依據本發明，即可提高半導體晶片的晶片凸塊與封 裝基板的銲錫凸塊之間的接合可靠性。 【實施方式】 本發明可作多樣的變換，可有各式各樣的實施例，因 此在本案中，於圖式例示並詳細地說明特定實施例。但是， 這並不是將本發明限定於特定的實施例，而是應被理解為 包括：被包含在本發明的思想以及技術範圍中的所有的變 換、均等物、以及代替物者。說明本發明時，被判斷為對 於相關的習知技術的具體說明，反而會造成本發明的要旨 不明確的情況時，則省略其詳細的說明。 ’、、顶理解地’本案巾所肖的用語係僅為說明特定的實 施例而採用者，並非限定本發明者。單一數的表現，只要 在文句之中未明確表現的前提下’包含複數的表現。本案 中，「包含」或「具有」等的用語，係用來指定被記载於說 明書上的特徵、數字、階段、動作、構成要素、構件、或 組合這些者的存在，而並非預先排除—個或一個以上的其 :的特徵、數字、階段、動作、構成要素、構件、或組ς 這些者的存在或是附加可能性。 以下，基於添附圖式，詳細地說明本發明之封裝基板 的製造方法及半導體封裝的製造方法的實施例，使二 201001576 圖式來進抒每aa 士 %，對於相同且對應的構成要素，係俨节 相㈣付號而省㈣㈣㈣㈣。 …己 造方表示依據本發明的—實施例之封裝基板的製 这万法的流程圖，第6圖〜第9圖孫本-> Α 實施例之封键H 圖係表不依據本發明的一 封裝基板的製造方法的製程圖。若參 圖’則電路基板12、電路圖媒14 ^ '、、 Η、電極墊16、銲錫凸塊 圓員狀溝20、以及治具22係被表示。 板（要㈣方法，係製造封裝基 _ 、已形成有晶片凸塊之半導體晶片）的方法，包 含.提供已形成有電極墊16之電路基板12的階段；在電 極墊16上形成鲜錫凸塊18的階段，·對應晶片凸塊的形狀， 使已形成有凸部或凹部之治具22(如）的凸部或凹部，面 對鮮錫凸塊18,而將治具22熱加壓於基板上的階段；以 及使治具22脫模的階段；此製造方法，可提高半導體晶片 的凸塊與封裝基板的銲錫凸塊18之間的接合可靠性。 若觀察依據本實施例之封裝基板的製造方法，首先， 如第6圖所示’在階段sl〇〇中’提供一種已形成有電極塾 16之電路基板12;在階段S2〇〇中，於電路基板η的電極 墊16上，形成銲錫凸塊18。電路基板12係要被載置半導 體晶片之封裝基板。被形成於電路基板12上的電極墊16 , 係可作為電路圖樣14的一部分而被形成。電極墊16，係 以銲錫凸塊18為媒介，用以電性連接電路基板12與半導 體晶片，可形成複數個，因此，銲錫凸塊18亦可形成複數 個0 201001576 鋒錫凸塊18係突出而被形成於電極墊i6上。鲜錫凸 塊工"皮形成於電極塾16上的方法，首先，將遮罩(已形成 有對應銲錫凸塊18之開口部)’載置於電路基板。上。接 著’於遮罩上，塗佈導電性的錫f，以擠壓（squeeze)的 方式將錫膏壓入開口部。接著’以遮罩被載置的狀態下， 加熱來實行迴焊、或使錫膏硬化。接著，除去遮罩，而在 電路基板12的電極墊16上形成銲錫凸塊18。 此外，亦可以喷墨方式將焊油墨印刷於電極塾Μ上， 來形成銲錫凸塊1 8。 若藉由上述的方法，於電路基板12的電極墊Μ上形 成銲錫凸塊18，則銲錫凸塊18的尺寸、高度係不均勻。 接著’如第7圓以及第8圖所示，在階段㈣。中，對 應晶片凸塊的形狀，使已形成有凸部或凹部之治具Μ的凸 部或凹部’面料錫凸《18 ’㈣治具22熱加壓於基板 上。 若藉由上述的方法，於電極墊16上形成銲錫凸塊Μ， 則鲜锡凸塊18的尺寸、古庚孫尤仏乂 . 又寸问度係不均勻，與半導體晶片的晶 片凸塊的接合可靠性會顯著地降低。因此，為了使銲錫凸 塊18的高度一定’使已形成有凸部或凹部之治具η進行 熱加壓，將銲錫凸塊18的高度作成一定。 最近，因對於大容量資料的高速處理的要求、以及因 電子製品的輕薄短小化而導致的電子元件的凸塊的尺寸及 間距不斷地變小的傾向，半導體晶片的凸塊與電路基板12 的銲錫凸塊18之間的接合可靠性係非常地低。 201001576 為了改善如此的接合可靠性，半導體晶片的晶片凸塊 的形癌，係漸漸變化為電鐘金屬而被得到的金屬柱狀凸塊 構造，但此亦難以提高接合可靠性。 另方面’以電鍍金屬而成的柱狀凸塊來作為半導體 曰曰片的凸塊的情況，半導體晶片的凸塊的前端及電路基板 12的銲錫凸塊18的前端，兩者皆被形成平坦面。因此， 當使半導體晶片的凸塊與電路基板12的銲錫凸塊18互相 ( 對應來進行迴焊（reflQW)製程之際，於半導體晶片的凸塊與 電路基板12的銲錫凸塊18的接合面發生空隙，而有接合 可靠性降低的問題點。 本發明係為了解決如此的接合可靠性降低的問題點， 其特徵在於：對應半導體晶片的晶片凸塊的形狀，使被形 成於電路基板12上的銲錫凸塊18的形狀變形。亦即為 了提高晶片凸塊與銲錫凸塊1 8之間的接合可靠性，對應半 導體晶片的晶片凸塊的形狀，使要被構裝半導體晶片之封 ί) 裝基板的銲錫凸塊18的形狀變形，來提高半導體晶片的晶 片凸塊與封裝基板的銲錫凸塊1 8之間的接合可靠性。 本實施例中’以電鍍金屬而被形成的柱狀凸塊來作為 半導體晶片的晶片凸塊的情況，使對應該晶片凸塊的銲錫 凸塊18的前端的形狀呈圓頂（Dome )狀，並使其具有— 定的高度’來使柱狀凸塊的平坦的前端與銲錫凸塊18的圓 頂狀的前端接觸’便能防止在接合部發生空隙。 為了對應晶片凸塊的形狀而變更銲錫凸塊18的形 狀，使用已形成有凸部或凹部之治具22。本實施例中，為 201001576 了將被形成於電路基板12上的銲錫凸塊18的前端形成一 定高度的圓頂狀，而將被形成於治具22上的凹部做成圓頂 狀的溝20。 為了將已被形成於電路基板12的電極墊16上的録錫 凸塊1 8的前端，形成一定高度的圓頂狀，係以治具22的 圓頂狀溝20面對銲錫凸塊18的方式，使治具22熱加壓於 電路基板12(亦即，治具22對電路基板作熱加壓）。在此， 所謂的熱加壓’係包含：一邊加熱來使銲錫凸塊18迴焊， 一邊將治具22加壓於電路基板1 2上’來使銲錫凸塊1 8的 前端成為圓頂狀的概念。 對應晶片凸塊的形狀而被變形的銲錫凸塊丨8的形 狀、以及用以形成此形狀的治具22的凸部或凹部的形狀， 係如後述。 接著，如第9圖所示’在階段S400中，使銲錫凸塊 1 8硬化，在階段S5〇〇中’使治具22脫模。在熱加壓治具 22的過程中，有銲錫凸塊18被融解而失去其形狀的情況 時’在使治具22脫模之前，先硬化銲錫凸塊1 8，之後， 從電路基板12，使治具22脫模，而在封裝基板上形成鮮 錫凸塊18。但是，當銲錫凸塊18的黏著性高，即使將治 具22脫模，其形狀亦被維持的情況時’亦可不硬化銲錫凸 塊1 8而立刻使治具22脫模。 經過上述的製程’在電路基板12上，形成銲錫凸塊 1 8，該銲錫凸塊1 8對應對應要被構裝的半導體晶片的晶片 凸塊的形狀，藉此，可提高接合可靠性。 11 201001576 …第1G圖係表示依據本發明之—實施例之銲錫凸塊的 形狀的使用狀_圖’第u圖係、表示依據本發明之其他實施 例之銲錫凸，的形狀的使用狀態圖1 12圖係表示依據本 發月之另實施例之銲錫凸塊的形狀的使用狀態圖。又， 帛13 w係表示依據本發明之另—實施例之銲錫凸塊的形 狀的使用狀態圖。若參照第！ 〇圖至第η圖，則電路基板 12電極墊16、銲錫凸塊18、柱狀凸塊24、半導體晶片 Γ 26、以及針型凸塊28係被表示。 第10圖係表示依據上述的一實施例而被形成的銲錫 凸塊18與半導體晶片26的晶片凸塊的連接狀態。本實施 例中半導體晶片26的晶片凸塊為電鍵金屬而被形成的柱 狀凸塊24時，先將對應該柱狀凸塊24之銲錫凸塊i 8的前 端仅成圓頂狀’然後使柱狀凸塊24的平坦的前端與銲錫凸 塊1 8的圓頂狀的别端接觸，便可防止於接合部發生空隙。 彳另方面，第11圖係表示在其前端已形成有之銲錫凸 U 塊18與晶片凸塊的接合構造。本實施例中，半導體晶片 26的晶片凸塊為柱狀凸塊24時，先在 對應該柱狀凸塊24之銲錫凸塊18的前端形成刮痕狀的 溝，然後與晶片&塊接合之際，使线經由刮痕狀的溝而 排除可防止在晶片凸塊與銲錫凸塊1 8的接合面發生空 隙。 第12圖係表示針型凸塊28與銲錫凸塊μ的接合構 &，忒針型凸塊2 8的前端已形成有圓錐狀突起，該銲錫凸 塊18，為了使針型凸塊28容易地插入，而在其前端形成 12 201001576 有對應針型凸塊28的形狀之圓錐狀溝。本實施例中，半導 =26的…塊為已形成有圓錐狀突起之針型凸塊 :的:障況’為了使針型凸塊28可容易地插入，而於銲錫 ^ =的前端形成圓錐狀溝，可增加針型凸塊28與㈣ 鬼u之間的接觸面積，提高接合可靠性。 第13圖係表示晶片凸塊為電鍍金屬而被形成的柱狀 凸塊Μ的情況’銲錫凸塊18的接合構造;該鮮錫凸塊a， 其中央部對應柱狀凸塊24而隆起’並形成有噴火口狀的前 端。本實施财，使柱狀凸塊24的平坦的前端與鲜锡凸塊 18的隆起的部分接觸，以防止發生"，迴焊之際，使銲 錫凸塊18合易包圍柱狀凸塊24的外廓，而可提高接合可 靠性。 第14目係、表不用以形成依據本發明之一實施例的鲜 錫凸塊之治具的形態的圖，第15圖係表示用以形成依據本 發明之其他實施例的銲锡凸塊之治具的形態的圖，第_ 係表示用以形成依據本發明之另一實施例的銲錫凸塊之治 '的®。另外’ S i7圖係表示用以形成依據本發明 之另—實施例的銲錫凸塊之治具的形態的圖。若參照第14 圖至第17圖’則治具22、gj頂狀溝2G、到痕3G、圓錐狀 凸部32、以及喷火口狀的凸部34係被表示。 在第14圖至第17圖中，係表示用以形成依據上述的 第1 〇圖至第13圖的貫施例的銲錫凸塊，且熱加壓已被形 成於電路基板上的銲錫凸塊之治具22的形態。 若觀察第14圖，為了將銲錫凸塊的前端形成一定尺寸 13 201001576 的圓頂狀，圓頂狀溝20被形成於治具22。藉由將銲錫凸 塊邊被插入圓頂狀溝2 〇 , —邊進行熱加壓，即可於電路 基板的電極墊上形成一定尺寸的圓頂狀的銲錫凸塊。 若觀察第1 5圖，為了將銲錫凸塊的前端形成刮痕％ 狀的溝，到痕30狀的溝被形成於治具22。銲錫凸塊被形 成於電極墊上之後，藉由將已形成有刮痕3 〇狀的溝之治具 22，熱加壓於電路基板，即可於銲錫凸塊的前端形成刮痕 30狀的溝。 若觀察第16圖，為了將銲錫凸塊的前端形成圓錐狀的 溝’圓錐狀的&冑32被形成於治具22。鲜錫凸塊被形成 於電極墊上之後，藉由將已形成有圓錐狀的凸部32之治具 22’熱加壓於電路基板，即可於銲錫凸塊的前端形成圓錐 狀的溝。 若觀察第17圖，了為將銲錫凸塊的前端形成中央隆起 的喷火口狀’其中央部凹陷的噴火口狀的凸部34，被形成 於治具22。銲錫凸塊被形成於電極墊上之後，藉由將已形 成有t央凹陷的喷火口狀的凸部34之治具22，熱加壓於 電路基板，即可形成-銲錫凸塊，其具有中央隆起的喷火 口狀的前端。 第1 8圖及第19圖，係表示依據本發明之另一實施例 之半導體封裝的製造方法的製程圖1參照帛18圖及第 19圖，則電路基板12、電路圖樣14、電極塾16、鲜錫凸 塊18、柱狀凸塊24、以及半導體晶片36係被表示。 依據本實施例之半導體封裝的製造方法，係依據上述 14 201001576 的一實施例，於電極墊16上形成具有一定尺寸的圓頂狀的 銲錫凸塊18，而完成封裝基板。 製造封裝基板的方法，係因與上述的内容相同，故於 本實施例中省略其說明。在此，對應半導體晶片％的晶片 凸塊，被形成於封裝基板上的銲錫凸塊18的形狀，係可用 上述的治具22而形成。 本實施例中，與上述的一實施例相同地，表示出先在 電路基板12的電極墊16上形成一定高度的圓頂狀的銲錫 凸塊18,然後構裝半導體晶片％的情況，但亦可先對應 半導體晶片36的晶片凸塊的形狀，於電路基板12上形成 上述的多樣的形態的銲錫凸塊丨8，然後構裝半導體晶片 3 6。 接著，對應晶片凸塊的銲錫凸塊18，被形成於電路基 板12的電極墊16上之後，如第18圖所示，使晶片凸塊與 銲錫凸塊18對應，而將半導體晶片36構裝於電路基板η 上。 接著，如第19圖所示，使銲錫凸塊18迴焊，來接合 晶片凸塊與銲錫凸& 18。藉由熱，使銲錫凸塊18迴焊， 可防止在硬化過程中發生空隙，#由晶片凸塊與銲錫凸塊 18的接觸面進行金屬接合，可提高接合強度。 如前所述，藉由對應半導體晶片36的晶片凸塊的形 狀’變化要被構裝半導體晶片36之封裝基板的銲錫凸塊 18的形狀’可提高晶片凸塊與銲錫凸塊18的接合可靠性。 以上，已對於本發明的較佳實施例作說明，但請理解’ 201001576 只要是該技術領域中具有通常知識者，便可於不脫逸被記 載於申請專利範圍中的本發明的思想及領域的範圍内，將 本發明作多樣地修正及變更。 【圖式簡單說明】 第1圖係表示依據先前技術之半導體晶片封裝的製造 方法的製程圖。 第2圖係表示依據先前技術之半導體晶片封裝的製造 方法的製程圖。 第3圖係表示依據先前技術之半導體晶片封裝的製造 方法的製程圖。 第4圖係表示依據先前技術之半導體晶片封裝的製造 方法的製程圖。 第 5 圖係表示依據本發明之一實施例的封裝基板的製 造方法的流程圖。 第 6 圖係表示依據本發明之一實施例的封裝基板的製 造方法的製程圖。 第 7 m / 圖係表示依據本發明之一實施例的封裝基板的製 造方法的製程圖。 第 8 w係表示依據本發明之一實施例的封裝基板的製 造方法的製程圖。 第 9 圖係表示依據本發明之一實施例的封裝基板的製 造方法的製程圖。 16 201001576 第1 〇圖係表示依撼★π。 據本發明之一實施例的銲錫凸塊的 形狀的使用狀態圖。 第11圖係表示佑诚士 β 依據本發明之其他實施例的銲錫凸塊 的形狀的使用狀態圖。 第12圖係表示依擔 攸據本發明之另一實施例的銲錫凸塊 的形狀的使用狀態圖。 第13圖係表示依擔 依·據本發明之另一實施例的銲錫凸塊 的形狀的使用狀態圖。 第 14 圖推± 一 、示用以形成依據本發明之一實施例的銲 錫凸塊之治具的形態的圖。 第 15 圖^系φ — m ’、衣不用以形成依據本發明之其他實施例的 銲錫凸塊之治具的形態的圖。 第 16圖择矣 示衣不用从形成依據本發明之另一實施例的 銲锡凸塊之治具的形態的圖。 第 17圖採矣 同你表不用以形成依據本發明之另一實施例的 銲锡凸塊之治具的形態的圖。 18 圖係表示依據本發明之另一實施例的半導體封 裝的製造方法的製程圖。 1 圖係表示依據本發明之另一實施例的半導體封 褒的製造方法的製程圖。 17 201001576 【主要元件符號說明】 12 ： 電路基板 14 ： 16 ： 電極塾 18 ： 20 ： 圓頂狀溝 22 ： 24 ： 柱狀凸塊 26 ： 28 ： 針型凸塊 30 ： 32 ： 圓錐狀凸部 34 ： 36 ： 半導體晶片 102 104 :電路圖樣 106 108 :鲜錫凸塊 110 112 :半導體晶片 114 電路圖樣 鮮錫凸塊 治具 半導體晶片 刮痕 喷火口狀凸部 :電路基板 :電極墊 :加壓板 :半導體晶片的凸塊 18201001576 6. Description of the Invention: TECHNICAL FIELD The present invention relates to a method of manufacturing a package substrate and a method of manufacturing a semiconductor package. [Prior Art] Flip chip packaging refers to a semiconductor wafer or a circuit board when an electronic component such as a semiconductor wafer is attached to a circuit board without using an additional connection structure such as a wire. On the electrode pattern, a solder bump is welded, and a semiconductor wafer and a circuit substrate are bonded to perform a package. Recently, the size and the bump pitch of electronic components have been steadily decreasing due to the demand for high-speed processing of large-capacity data or the reduction in thickness of electronic products. With such a miniaturization of the size of the bumps, it is important to control the height of each of the bumps to become strict. Figs. 1 to 4 are process diagrams showing a manufacturing method of a semiconductor wafer package according to the prior art. When the manufacturing method of the semiconductor package according to the prior art is carefully observed, first, as shown in FIG. 1, on the electrode pad 1〇6 formed as a part of the circuit pattern 1〇4 of the circuit substrate 102, the solder bump is welded. Block 1 08. At this time, the size and height ' of the solder bumps 1 8 which are welded to the electrode pads 6 are not constant. Next, as shown in Fig. 2, the front end of the solder bump 108 is pressed to flatten the front end of the solder bump 108 by using a flat embossing plate U 〇, and 201001576 makes the height -set. Next, as shown in FIG. 3, the pressure plate is separated, and the tin-plated bumps 108 whose front end is flat and of a constant height are formed on the circuit substrate. Next, as shown in FIG. 4, the semiconductor is The semiconductor wafer 112 is placed on the circuit substrate 102 in such a manner that the bumps 14 of the wafer correspond to the solder bumps 1 8 of the circuit substrate 102. Next, the solder bumps 8 are re-etched and the semiconductor wafer 112 is bonded to the circuit board 1'2. However, according to the manufacturing method of the semiconductor chip package of the prior art, f: the size, pitch, and the like of the bump of the electronic component tend to become smaller, so the solder bump of the bump of the half V body wafer and the circuit substrate There is a problem that the joint reliability is low. In particular, when the bump of the semiconductor wafer is formed into a columnar bump type formed by plating a metal, both the tip end of the bump of the semiconductor wafer and the tip end of the solder bump of the circuit board are formed into a flat surface. When the bump of the semiconductor wafer and the solder bump of the circuit board are mutually matched to perform the reflow process, the bump of the semiconductor wafer and the solder bump of the circuit board (the joint surface of the block may have a void (Air void) [Problems to be Solved by the Invention] In view of the problems of the prior art, an object of the present invention is to provide a method of manufacturing a package substrate and a semiconductor package. In the manufacturing method, the bonding reliability of the 4 201001576 can be improved between the wafer bumps of the semiconductor wafer and the solder bumps of the package substrate. [Technical means for solving the problem] According to an embodiment of the present invention, a A method of manufacturing a package substrate (which is to be configured to form a semiconductor B-day film in which a wafer is formed) The method includes: providing a circuit substrate on which the electrode 已 has been formed; forming a solder bump on the electrode & a shape of the corresponding wafer bump, and forming a fixture having a convex portion or a concave portion a convex portion or a concave portion facing the stage of hot pressing of the jig on the substrate; and a stage of demolding the jig. The solder may be included before the stage of demolding the jig The stage of hardening of the bumps. The stage of forming the solder bumps may include: placing a mask (an opening portion corresponding to the tin bumps) on the circuit substrate; pressing the solder paste to press it The stage of entering the opening; the stage of reflowing the solder paste; and the stage of removing the mask. The BB piece bump can be a flat columnar bump at the front end; the recess of the jig can be a dome-shaped groove In addition, the wafer bump may be a columnar bump having a flat front end; the concave portion of the jig may be a groove shaped like a groove. The wafer bump may have a conical protrusion formed at the front end. The pin-shaped bump '·the convex part of the jig' can be a cone corresponding to the protrusion When the wafer bump is a columnar bump having a flat front end, the convex portion of the jig may be a fire-blast-like convex portion recessed at the center portion. Further, according to another embodiment of the present invention, A method for manufacturing a semiconductor package of 201001576, Α 俨 俨 俨 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 姓 - - - - - 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构 构The stage of the circuit board of the electrode pad; the stage of forming the tin bump on the electrode :: the angle _ a π π % , , corresponding to the shape of the ridge bump, so that the convex has been formed a convex portion or a concave portion of the fixture of the U, facing the solder convex force, and heating the fixture: a stage of pressing on the substrate; a stage of demolding the fixture; and making the wafer bump correspond to the knowing tin bump a stage of mounting a semi-conductive I# S g# bamboo dry day sheet on a circuit substrate; and reflowing the solder bumps to bond the wafer bumps with the stage of the fresh tin bumps in the demolding of the fixture Before the stage, the stage of hardening the tin-tin bumps may be included. The step of forming the solder bump may include: placing a mask (an opening portion corresponding to the solder bump) on a circuit substrate; pressing the solder paste to press the opening portion (four) The stage of returning solder #; and the stage of removing the mask. The wafer bump may be a columnar bump having a flat front end; the recess of the jig may be a dome-shaped groove. Further, when the wafer bump is a columnar bump having a flat front end, the concave portion of the jig may be a scratch-like groove. The wafer bumps ' may be convex portions of the needle-shaped bumps of the conical protrusions formed at the front end, and may be conical convex portions corresponding to the protrusions. When the B-plate is convex and the columnar bump is flat at the end, the convex portion of the jig may be a fire-jet-like convex portion that is recessed at the center. 201001576 [Effect] According to the present invention, the bonding reliability between the wafer bumps of the semiconductor wafer and the solder bumps of the package substrate can be improved. [Embodiment] The present invention can be variously modified, and various embodiments can be made. Therefore, in the present invention, specific embodiments are illustrated and described in detail in the drawings. However, the present invention is not limited to the specific embodiments, but is intended to include all modifications, equivalents, and substitutes that are included in the scope of the inventions. In the description of the present invention, the detailed description of the related art will be omitted, and the detailed description of the present invention will be omitted if the gist of the present invention is not clear. The words used in the present disclosure are for the purpose of describing particular embodiments and are not intended to limit the invention. The performance of a single number, as long as it is not clearly expressed in the sentence, contains the performance of the plural. In this case, the terms "including" or "having" are used to specify the existence of features, numbers, stages, actions, constituent elements, components, or combinations described in the specification, and are not excluded in advance - The presence or additional possibility of one or more of its characteristics, numbers, stages, actions, components, components, or groups. Hereinafter, an embodiment of the method for manufacturing a package substrate and a method for manufacturing a semiconductor package according to the present invention will be described in detail based on the accompanying drawings, so that the second 201001576 schema is used for each aa-%, and the same and corresponding constituent elements are The 相 相 phase (4) pays the number and saves (4) (4) (4) (4). The present invention shows a flow chart of the method for manufacturing a package substrate according to the embodiment of the present invention, and FIG. 6 to FIG. 9 is a copy of the embodiment. The key diagram H of the embodiment is not in accordance with the present invention. A process map of a method of manufacturing a package substrate. Referring to Fig., the circuit board 12, the circuit board 14^', the crucible, the electrode pad 16, the solder bump rounded groove 20, and the jig 22 are shown. A method of manufacturing a package substrate _, a semiconductor wafer having a wafer bump formed thereon, including a stage of providing a circuit substrate 12 on which an electrode pad 16 has been formed; forming a tin bump on the electrode pad 16 At the stage of the block 18, corresponding to the shape of the wafer bump, the convex portion or the concave portion of the jig 22 (for example) in which the convex portion or the concave portion has been formed faces the fresh tin bump 18, and the jig 22 is thermally pressurized. a stage on the substrate; and a stage of demolding the jig 22; the manufacturing method improves the bonding reliability between the bumps of the semiconductor wafer and the solder bumps 18 of the package substrate. When observing the manufacturing method of the package substrate according to the present embodiment, first, as shown in FIG. 6, 'in the stage s1', a circuit substrate 12 on which the electrode 塾 16 has been formed is provided; in the stage S2 ,, Solder bumps 18 are formed on the electrode pads 16 of the circuit substrate η. The circuit board 12 is a package substrate on which a semiconductor wafer is to be placed. The electrode pad 16 formed on the circuit board 12 can be formed as a part of the circuit pattern 14. The electrode pad 16 is electrically connected to the circuit substrate 12 and the semiconductor wafer by using the solder bumps 18, and a plurality of solder bumps 18 can be formed. Therefore, the solder bumps 18 can also form a plurality of 0 201001576 front tin bumps 18 series protruding It is formed on the electrode pad i6. In the method of forming a thin tin bump on the electrode crucible 16, first, a mask (an opening portion on which the solder bump 18 is formed) is placed on the circuit board. on. Next, the conductive tin f was applied to the mask, and the solder paste was pressed into the opening portion in a squeeze manner. Then, in a state where the mask is placed, heating is performed to perform reflow or to cure the solder paste. Next, the mask is removed, and solder bumps 18 are formed on the electrode pads 16 of the circuit substrate 12. Alternatively, the solder bumps may be printed on the electrode pads by ink jetting to form solder bumps 18. When the solder bumps 18 are formed on the electrode pads of the circuit board 12 by the above-described method, the size and height of the solder bumps 18 are not uniform. Then, as shown in the 7th and 8th, in the stage (4). In response to the shape of the wafer bump, the convex or concave portion of the jig having the convex portion or the concave portion is formed, and the 18" (four) jig 22 is thermally pressed onto the substrate. If the solder bumps are formed on the electrode pads 16 by the above method, the size of the solder bumps 18, the Geng Sunyu, and the inhomogeneity are uneven, and the wafer bumps of the semiconductor wafer are Bonding reliability can be significantly reduced. Therefore, in order to make the height of the solder bump 18 constant, the jig θ in which the convex portion or the concave portion has been formed is thermally pressurized, and the height of the solder bump 18 is made constant. Recently, the requirements for high-speed processing of large-capacity data and the tendency of the size and pitch of bumps of electronic components to be steadily reduced due to the thinness and thinning of electronic products, the bumps of semiconductor wafers and the circuit board 12 The joint reliability between the solder bumps 18 is very low. 201001576 In order to improve such bonding reliability, the shape of the wafer bump of the semiconductor wafer is a metal stud bump structure obtained by gradually becoming a metal clock, but it is also difficult to improve the bonding reliability. On the other hand, in the case where a columnar bump made of a plated metal is used as a bump of a semiconductor wafer, the front end of the bump of the semiconductor wafer and the front end of the solder bump 18 of the circuit substrate 12 are both formed flat. surface. Therefore, when the bumps of the semiconductor wafer and the solder bumps 18 of the circuit substrate 12 are mutually reciprocated (reflQW), the bumps of the semiconductor wafer and the solder bumps 18 of the circuit substrate 12 are bonded to each other. The present invention is directed to solving the problem of such a reduction in bonding reliability, and is characterized in that the shape of the wafer bump corresponding to the semiconductor wafer is formed on the circuit substrate 12. The shape of the solder bump 18 is deformed, that is, in order to improve the bonding reliability between the wafer bump and the solder bump 18, the shape of the wafer bump corresponding to the semiconductor wafer is such that the semiconductor wafer is to be packaged) The shape of the solder bumps 18 on which the substrate is mounted is deformed to improve the bonding reliability between the wafer bumps of the semiconductor wafer and the solder bumps 18 of the package substrate. In the present embodiment, the case where the columnar bumps formed by plating metal are used as the wafer bumps of the semiconductor wafer, the shape of the front end of the solder bumps 18 corresponding to the wafer bumps is dome-shaped. By having a constant height 'to bring the flat front end of the stud bump into contact with the dome-shaped front end of the solder bump 18', it is possible to prevent a gap from occurring at the joint portion. In order to change the shape of the solder bump 18 in accordance with the shape of the wafer bump, the jig 22 in which the convex portion or the concave portion has been formed is used. In the present embodiment, in the case of 201001576, the tip end of the solder bump 18 formed on the circuit board 12 is formed into a dome shape having a certain height, and the recess portion formed on the jig 22 is formed into a dome-shaped groove 20 . In order to form the front end of the recording tin bump 18 which has been formed on the electrode pad 16 of the circuit substrate 12, a dome shape having a certain height is formed, and the dome-shaped groove 20 of the jig 22 faces the solder bump 18 In this manner, the jig 22 is thermally pressed against the circuit substrate 12 (that is, the jig 22 thermally presses the circuit substrate). Here, the term "hot press" includes heating the solder bump 18 back to the solder substrate 18 and pressing the jig 22 onto the circuit board 1 2 to make the tip end of the solder bump 18 dome-shaped. the concept of. The shape of the solder bump 8 deformed in accordance with the shape of the wafer bump, and the shape of the convex portion or the concave portion of the jig 22 for forming the shape are as follows. Next, as shown in Fig. 9, in the step S400, the solder bumps 18 are hardened, and the jig 22 is demolded in the step S5. In the process of thermally pressing the jig 22, when the solder bump 18 is melted to lose its shape, 'the solder bump 18 is hardened before the mold 22 is demolded, and then, from the circuit substrate 12, The jig 22 is demolded, and a bright tin bump 18 is formed on the package substrate. However, when the solder bumps 18 have high adhesion, even if the shape of the solder bumps 22 is released, the shape of the solder bumps 18 is maintained, and the jig 22 can be released immediately without hardening the solder bumps 18. Through the above-described process 'on the circuit substrate 12, solder bumps 18 are formed, which correspond to the shape of the wafer bumps corresponding to the semiconductor wafer to be mounted, whereby the bonding reliability can be improved. 11 201001576 ... 1G is a view showing the use of the shape of the solder bump according to the embodiment of the present invention - FIG. 5 is a view showing the state of use of the shape of the solder bump according to another embodiment of the present invention. 1 12 is a view showing a state of use of the shape of the solder bump according to another embodiment of the present month. Further, 帛13 w is a view showing a state of use of the shape of the solder bump according to another embodiment of the present invention. If you refer to the first! From the 〇 to the ηth diagram, the circuit substrate 12 electrode pad 16, the solder bump 18, the stud bump 24, the semiconductor wafer 26, and the pin bump 28 are shown. Fig. 10 is a view showing a state in which the solder bumps 18 formed in accordance with the above-described embodiment are connected to the wafer bumps of the semiconductor wafer 26. In the present embodiment, when the wafer bumps of the semiconductor wafer 26 are the columnar bumps 24 formed by the key metal, the front ends of the solder bumps i 8 corresponding to the columnar bumps 24 are first formed into a dome shape. The flat front end of the stud bump 24 is in contact with the other end of the dome of the solder bump 18 to prevent a gap from occurring in the joint portion. On the other hand, Fig. 11 shows the joint structure of the solder bump U block 18 and the wafer bump formed at the front end thereof. In the embodiment, when the wafer bump of the semiconductor wafer 26 is the stud bump 24, a scratch-like groove is formed on the front end of the solder bump 18 corresponding to the stud bump 24, and then bonded to the wafer & In the meantime, the elimination of the line through the scratch-shaped groove prevents the occurrence of a gap between the bonding surface of the wafer bump and the solder bump 18. Fig. 12 is a view showing the joint structure of the pin bumps 28 and the solder bumps μ, and the tip end of the pin-shaped bumps 28 has been formed with a conical projection 18 for the pin bumps 28 It is easy to insert, and at its front end, 12 201001576 has a conical groove corresponding to the shape of the needle-shaped bump 28. In the present embodiment, the block of semi-conductivity=26 is a pin-shaped bump having a conical protrusion formed: a barrier condition 'in order to allow the pin-shaped bump 28 to be easily inserted, and formed at the front end of the solder ^= The conical groove can increase the contact area between the pin bump 28 and the (four) ghost u, improving the joint reliability. Fig. 13 is a view showing a state in which the solder bumps are formed by plating the metal bumps, and the bonding structure of the solder bumps 18; the center portion of the solder bumps a corresponding to the columnar bumps 24 and bulging' A front end having a spout shape is formed. In this implementation, the flat front end of the stud bump 24 is brought into contact with the raised portion of the tin bump 18 to prevent the occurrence of the "bumping", so that the solder bump 18 can easily surround the stud bump 24 The outer profile improves the joint reliability. Figure 14 is a view showing a form of a jig for forming a tin bump according to an embodiment of the present invention, and Figure 15 is a view showing a solder bump for forming another embodiment according to the present invention. A diagram of the form of the jig, the _ series means a ® for forming a solder bump according to another embodiment of the present invention. Further, the 'S i7 diagram is a view showing a form of a jig for forming a solder bump according to another embodiment of the present invention. Referring to Figs. 14 to 17', the jig 22, the gj top groove 2G, the mark 3G, the conical convex portion 32, and the fire-jet-like convex portion 34 are shown. In FIGS. 14 to 17, the solder bumps for forming the solder bumps according to the above-described first to third embodiments are shown, and the solder bumps which have been thermally pressed have been formed on the circuit substrate. The shape of the fixture 22. When the figure 14 is observed, the dome-shaped groove 20 is formed in the jig 22 in order to form the tip end of the solder bump into a dome shape of a certain size 13 201001576. By inserting the solder bumps into the dome-shaped trenches 2, while performing thermal pressurization, a dome-shaped solder bump of a certain size can be formed on the electrode pads of the circuit board. When the figure 15 is observed, in order to form a groove having a scratch-like shape in the tip end of the solder bump, a groove having a mark 30 shape is formed in the jig 22. After the solder bump is formed on the electrode pad, the jig 22 having the groove 3 formed with the scratches 3 is thermally pressed against the circuit board, so that a groove 30-shaped groove can be formed at the tip end of the solder bump. . In the case of Fig. 16, in order to form a conical groove at the tip end of the solder bump, a conical & 胄 32 is formed in the jig 22. After the bright tin bumps are formed on the electrode pads, the jig 22' having the conical projections 32 formed thereon is thermally pressed against the circuit board, whereby a conical groove can be formed at the tip end of the solder bumps. When the front end of the solder bump is formed, a fire-jet-like convex portion 34 whose center portion is recessed at the tip end of the solder bump is formed in the jig 22. After the solder bumps are formed on the electrode pads, the solder bumps 22 are formed by heat-pressing the jigs 22 of the fire-blast-like convex portions 34 having the depressed portions to form a solder bump having a central portion. The swelled mouth of the fire-breathing mouth. FIGS. 18 and 19 are diagrams showing a manufacturing method of a semiconductor package in accordance with another embodiment of the present invention. FIG. 1 is a diagram showing a circuit board 12, a circuit pattern 14, and an electrode 塾16. The tin bumps 18, the stud bumps 24, and the semiconductor wafer 36 are shown. According to the manufacturing method of the semiconductor package of the present embodiment, according to an embodiment of the above-mentioned 14 201001576, a dome-shaped solder bump 18 having a certain size is formed on the electrode pad 16 to complete the package substrate. Since the method of manufacturing the package substrate is the same as that described above, the description thereof will be omitted in the present embodiment. Here, the shape of the solder bump 18 formed on the package substrate corresponding to the wafer bump of the semiconductor wafer % can be formed by the above-described jig 22. In the present embodiment, as in the above-described embodiment, the dome-shaped solder bumps 18 having a certain height are formed on the electrode pads 16 of the circuit board 12, and then the semiconductor wafers are mounted. First, in accordance with the shape of the wafer bump of the semiconductor wafer 36, the above-described various types of solder bumps 8 are formed on the circuit substrate 12, and then the semiconductor wafer 36 is mounted. Next, after the solder bumps 18 corresponding to the wafer bumps are formed on the electrode pads 16 of the circuit substrate 12, as shown in FIG. 18, the wafer bumps are associated with the solder bumps 18, and the semiconductor wafers 36 are mounted. On the circuit substrate η. Next, as shown in Fig. 19, the solder bumps 18 are soldered back to bond the wafer bumps to the solder bumps & By soldering the solder bumps 18 by heat, it is possible to prevent voids from occurring during the hardening process. # Metal bonding by the contact faces of the wafer bumps and the solder bumps 18 can improve the bonding strength. As described above, the shape of the wafer bumps corresponding to the semiconductor wafer 36 'changes the shape of the solder bumps 18 of the package substrate to which the semiconductor wafer 36 is to be mounted' can improve the bonding of the wafer bumps to the solder bumps 18 reliably. Sex. Hereinabove, the preferred embodiments of the present invention have been described, but it is understood that '201001576' can be used in the field of the invention as long as it is generally known in the art. The present invention has been variously modified and changed within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a process diagram showing a manufacturing method of a semiconductor chip package according to the prior art. Figure 2 is a process diagram showing a method of fabricating a semiconductor chip package in accordance with the prior art. Figure 3 is a process diagram showing a method of fabricating a semiconductor chip package in accordance with the prior art. Figure 4 is a process diagram showing a method of fabricating a semiconductor chip package in accordance with the prior art. Fig. 5 is a flow chart showing a method of manufacturing a package substrate in accordance with an embodiment of the present invention. Fig. 6 is a process diagram showing a method of manufacturing a package substrate in accordance with an embodiment of the present invention. Fig. 7 m / is a process diagram showing a method of manufacturing a package substrate in accordance with an embodiment of the present invention. The eighth embodiment is a process diagram showing a method of manufacturing a package substrate in accordance with an embodiment of the present invention. Figure 9 is a process diagram showing a method of manufacturing a package substrate in accordance with an embodiment of the present invention. 16 201001576 The first diagram shows the 撼★π. A state of use of the shape of a solder bump according to an embodiment of the present invention. Fig. 11 is a view showing a state of use of the shape of the solder bump according to another embodiment of the present invention. Fig. 12 is a view showing a state of use of a shape of a solder bump according to another embodiment of the present invention. Fig. 13 is a view showing a state of use of a shape of a solder bump according to another embodiment of the present invention. Fig. 14 is a view showing the form of a jig for forming a solder bump according to an embodiment of the present invention. Fig. 15 is a view showing a state in which the clothing is not used to form a jig of a solder bump according to another embodiment of the present invention. Fig. 16 is a view showing a state in which the garment is not formed from a jig for forming a solder bump according to another embodiment of the present invention. Fig. 17 is a view similar to the form in which the jig of the solder bump according to another embodiment of the present invention is not used. Figure 18 is a process diagram showing a method of fabricating a semiconductor package in accordance with another embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a process diagram showing a method of fabricating a semiconductor package in accordance with another embodiment of the present invention. 17 201001576 [Description of main component symbols] 12 : Circuit board 14 : 16 : Electrode 塾 18 : 20 : Dome groove 22 : 24 : Column bump 26 : 28 : Needle bump 30 : 32 : Conical projection 34 : 36 : semiconductor wafer 102 104 : circuit pattern 106 108 : fresh tin bump 110 112 : semiconductor wafer 114 circuit pattern fresh tin bump fixture semiconductor wafer scratch fire spout convex: circuit substrate: electrode pad: pressurization Board: bumps 18 of the semiconductor wafer

Claims (1)

201001576 七、申請專利範圍： 1 · 一種封裝基板的製造方法，其係製造封裝基板（要被構 裝已形成有晶片凸塊之半導體晶片）的方法，包含： 提供已形成有電極墊之電路基板的階段； 在上述電極墊上形成鲜錫凸塊（s〇lder bump )的階段； 對應上述晶片凸塊的形狀，使已形成有凸部或凹部之 治具（jig)的上述凸部或上述凹部，面對上述銲錫凸塊， (' 而將上述治具熱加壓於上述電路基板上的階段；以及 使上述治具脫模的階段。 2. 如申請專利範圍第1項所述之封裝基板的製造方法， 其中在使上述治具脫模的階段以前，更包含使上述銲錫凸 塊硬化的階段。 3. 如申明專利範圍第1項所述之封裝基板的製造方法， 其中形成上述鲜錫凸塊的階段，係包含： 將遮罩（已形成有對應上述銲錫凸塊之開口部），载置 G 於上述電路基板上的階段； 擠壓錫膏而將其壓入上述開口部的階段； 迴焊（reflow)上述錫膏的階段；以及 除去上述遮罩的階段。201001576 VII. Patent application scope: 1 . A method for manufacturing a package substrate, which is a method for manufacturing a package substrate (a semiconductor wafer to be formed with a wafer bump), comprising: providing a circuit substrate on which an electrode pad has been formed a stage of forming a tin bump on the electrode pad; corresponding to the shape of the wafer bump, the protrusion or the recess of the jig in which the protrusion or the recess has been formed Facing the above-mentioned solder bumps, ('the stage of thermally pressing the above-mentioned jig on the above-mentioned circuit substrate; and the stage of demolding the above-mentioned jig. 2. The package substrate as described in claim 1 And a method of manufacturing the packaged substrate according to the first aspect of the invention, wherein the above-mentioned fresh tin is formed. The stage of the bump includes: a step of forming a mask (an opening portion corresponding to the solder bump) is formed on the circuit board; and pressing the solder paste Into the opening portion of the stage; reflow (reflow) stage of the above-described solder paste; and removing the mask stage above. 圓頂狀的溝。 5 . 如申請專利範圍第 1項所述之封裝基板的製造方法， 19 201001576 其中上述晶片凸塊，係前 +垣的柱狀凸塊：上述凹部伤 刮痕（scratch )狀的溝。 < w 4係 6·如申請專利範圍第1項所.+、 甘士 .、 所34之封裝基板的製造方法， 八中上述晶片凸塊’係在前 ^ %已形成有圓錐狀突起之針枣 凸塊，上述凸部係對應上述φ I 成大起的圓錐狀凸部。 1如申請專利範圍第1項所述之封裝基板的製造方法， 八中上述晶片凸塊’係前端平坦的柱㈣；上 ， 係中央部凹陷的噴火口狀的凸部。 8. -種半導體封裝的製造方法，其係將已形成有晶片凸 塊之半導體W ’構裝於封裝基板上來實行封裝的 包含： 提供已形成有電極墊之電路基板的階段； 在上述電極墊上形成銲錫凸塊的階段； 對應上述晶片凸塊的形狀，使已形成有凸部或凹部之 治具的上述凸部或上述凹部，面對上述銲錫凸塊，而將上 述治具熱加壓於上述電路基板上的階段； 使上述治具脫模的階段； 使上述晶片凸塊與上述銲錫凸塊對應，而將上述半導 體晶片構裝於上述電路基板上的階段；以及 迴焊上述銲錫凸塊，來接合上述晶片凸塊與上述鲜锡 凸塊的階段。 9_ 如申請專利範圍第8項所述之半導體封裝的製造方 法’其中在使上述治具脫模的階段以前’更包含使上述薛 錫凸塊硬化的階段。 20 201001576 10·如申請專利範圍第8項所述之半導體封裝的製造方 法’其中形成上述銲錫凸塊的階段，係包含： 將遮罩（已形成有對應上述銲錫凸塊之開口部），載置 於上述電路基板上的階段； 擠麼錫膏而將其壓入上述開口部的階段； 迴焊上述錫膏的階段；以及 除去上述遮罩的階段。 11. 如申請專利範圍第8項所述之半導體封裝的製造方 法，其中上述晶片凸塊，係前端平坦的柱狀凸塊；上述凹 部係圓頂狀的溝。 8項所述之半導體封裝的製造方 ’係前端平坦的柱狀凸塊；上述凹 12. 如申請專利範圍第 法，其中上述晶片凸塊 部係刮痕狀的溝。 13·如申請專利範圍帛8項所述之半導體封裝的製造方 法，其中上述晶片&塊，係在前端已形成有圓錐狀突起之 針型凸塊；上述凸部係對應上述突起的圓錐狀凸部。 如中請專利範㈣8項所述之半㈣封裝的製造方 A其中上述晶片凸塊，係前端平坦的柱狀凸塊；上述凸 #，係中央部凹陷的喷火口狀的凸部。 21Dome-shaped groove. 5. The method of manufacturing a package substrate according to claim 1, wherein the wafer bump is a front bump + a columnar bump: the recess is a scratch-like groove. < w 4 series 6 · The method of manufacturing the package substrate of No. 1 of the patent application of the first item, +, Gans, and 34, wherein the above-mentioned wafer bumps are formed with the conical protrusions In the jujube bump, the convex portion corresponds to the conical convex portion in which the φ I is enlarged. 1. The method of manufacturing a package substrate according to the first aspect of the invention, wherein the wafer bumps are a column (four) having a flat front end, and a firing port-shaped convex portion having a central portion recessed. 8. A method of manufacturing a semiconductor package, comprising: mounting a semiconductor wafer W having a wafer bump formed on a package substrate to perform packaging: providing a circuit substrate on which an electrode pad has been formed; on the electrode pad Forming a solder bump; corresponding to the shape of the wafer bump, the convex portion or the concave portion of the jig having the convex portion or the concave portion formed thereon, facing the solder bump, and thermally pressing the fixture a stage on the circuit board; a stage of demolding the fixture; a stage of bonding the semiconductor bump to the solder bump, and mounting the semiconductor wafer on the circuit board; and reflowing the solder bump And bonding the above-mentioned wafer bumps to the above-mentioned fresh tin bumps. 9_ The method of manufacturing a semiconductor package as described in claim 8, wherein the step of demolding the above-mentioned jig further includes a stage of hardening the above-mentioned Xuexi bump. The method of manufacturing the semiconductor package described in the eighth aspect of the invention, wherein the step of forming the solder bump comprises: forming a mask (an opening portion corresponding to the solder bump is formed), a stage of being placed on the circuit board; a stage of pressing the solder paste to press it into the opening; a stage of reflowing the solder paste; and a stage of removing the mask. 11. The method of fabricating a semiconductor package according to claim 8, wherein the wafer bump is a columnar bump having a flat front end; and the recess is a dome-shaped groove. The manufacturing method of the semiconductor package of the eighth aspect is a columnar bump having a flat front end; the recess 12. The method of claim 12, wherein the wafer bump portion is a scratch-like groove. The method of manufacturing a semiconductor package according to claim 8, wherein the wafer & block is a pin-shaped bump having a conical protrusion formed at a front end thereof; and the convex portion corresponds to a conical shape of the protrusion Convex. For example, in the manufacturing method of the half (four) package described in the above paragraph (4), wherein the wafer bump is a columnar bump having a flat front end, and the convex portion is a fire-jet-shaped convex portion recessed at the center portion. twenty one
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