JPH06232205A - Packaging semiconductor device and semiconductor device - Google Patents

Packaging semiconductor device and semiconductor device

Info

Publication number
JPH06232205A
JPH06232205A JP5283794A JP28379493A JPH06232205A JP H06232205 A JPH06232205 A JP H06232205A JP 5283794 A JP5283794 A JP 5283794A JP 28379493 A JP28379493 A JP 28379493A JP H06232205 A JPH06232205 A JP H06232205A
Authority
JP
Japan
Prior art keywords
bump
semiconductor device
mounting
adhesive
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP5283794A
Other languages
Japanese (ja)
Inventor
Hiromichi Watanabe
広道 渡邊
Seiji Sudou
盛司 須藤
Takashi Yuda
孝 湯田
Toshiaki Suketa
俊明 助田
Toshio Sakata
敏夫 坂田
Shinichi Kasahara
愼一 笠原
Akifumi Matsunaga
朗史 松永
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5283794A priority Critical patent/JPH06232205A/en
Publication of JPH06232205A publication Critical patent/JPH06232205A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13012Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13018Shape in side view comprising protrusions or indentations
    • H01L2224/13019Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item

Abstract

PURPOSE:To reduce the strain of a semiconductor device due to the shrinkage stress of an adhesive and to improve the reliability of an electrical connection in packaging. CONSTITUTION:A metal bump 2 is formed on a semiconductor device 1, a conductive terminal 4 is formed on a substrate 3 which packages the semiconductor device 1, and, when the bump 2 is connected to the terminal 4, the periphery of a connection is buried. An adhesive 5-1 sufficient to fill a gap between the semiconductor device 1 and the packaging substrate 3 is applied to the semiconductor device 1 or the substrate 3. In a condition of the bump 2 pressed to the terminal 4, the adhesive 5-1 is hardened. Further, as a bump 2-1 to replace the bump 2, a groove 12 is formed on the surface, or as a bump 2-5 a recessed part 18-1 which retains the surface contour is formed and used.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置(チップ)の
実装方法、特に、半導体装置とその実装基板との接続を
接着剤で維持させる実装方法において、半導体装置の実
装歪による特性変動および、バンプを使用することによ
る電気的接続の不均一を抑制したものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a semiconductor device (chip), and more particularly to a mounting method for maintaining the connection between the semiconductor device and its mounting substrate with an adhesive. This is to prevent uneven electrical connection due to the use of bumps.

【0002】[0002]

【従来の技術】例えば液晶表示パネルにおいて、表示パ
ネルに駆動用の半導体チップを実装する主な方法には、
COG(Chip on Glass) 技術を利用する方法と、TAB
(TapeAutomatid Bonding)技術を利用する方法があり、
COG技術を利用する方法では、金属バンプと導体端子
との接続維持に接着剤の収縮応力を利用する。
2. Description of the Related Art For example, in a liquid crystal display panel, a main method of mounting a driving semiconductor chip on the display panel is as follows.
How to use COG (Chip on Glass) technology and TAB
There is a method to use (TapeAutomatid Bonding) technology,
In the method using the COG technique, the contraction stress of the adhesive is used to maintain the connection between the metal bump and the conductor terminal.

【0003】図17はCOG実装した従来の半導体チップ
の説明図、図18は液晶表示パネルにおける従来の半導体
チップ実装方法の説明図である。図17において、液晶表
示パネル駆動用半導体チップ1には、例えば金にてなる
多数の金属バンプ2を設け、半導体チップ1を実装する
液晶表示パネル用ガラス基板3には、ガラス基板3に形
成した透明電極(図示せず)に連通する導体端子4と、
外部接続用導体端子41を形成し、導体端子4と41には、
半導体チップ1の所定のバンプ2を接続 (当接) せし
め、その接続の維持と半導体チップ1の固定には、ガラ
ス基板3に塗付し,半導体チップ1とガラス基板3との
間に充填し硬化せしめた樹脂接着剤5の収縮応力と接着
力を利用する。
FIG. 17 is an explanatory view of a conventional semiconductor chip mounted by COG, and FIG. 18 is an explanatory view of a conventional semiconductor chip mounting method in a liquid crystal display panel. In FIG. 17, a large number of metal bumps 2 made of, for example, gold are provided on a semiconductor chip 1 for driving a liquid crystal display panel, and a glass substrate 3 for a liquid crystal display panel on which the semiconductor chip 1 is mounted is formed on the glass substrate 3. A conductor terminal 4 communicating with a transparent electrode (not shown),
The conductor terminal 41 for external connection is formed, and the conductor terminals 4 and 41 are
The predetermined bumps 2 of the semiconductor chip 1 are connected (abutted), and in order to maintain the connection and fix the semiconductor chip 1, a glass substrate 3 is coated and a space between the semiconductor chip 1 and the glass substrate 3 is filled. The shrinkage stress and adhesive force of the cured resin adhesive 5 are used.

【0004】図18において、(イ),(ロ),(ハ),(ニ),(ホ) は半
導体チップ実装工程の説明図、(ヘ)は半導体チップ実装
時における接着剤の拡がりの説明図である。図18(イ) に
おいて、液晶表示パネル21は、表示用透明電極等が形成
された一対のガラス基板3と22が所定間隙で対向し、シ
ール材23で気密封止したその対向間隙に液晶を充填して
なり、ガラス基板3の表呈部には、表示電極に接続する
導体端子4と外部接続用導体端子41が露呈する。
In FIG. 18, (a), (b), (c), (d) and (e) are explanatory views of the semiconductor chip mounting process, and (f) is a description of the spread of the adhesive when the semiconductor chip is mounted. It is a figure. In FIG. 18 (a), a liquid crystal display panel 21 has a pair of glass substrates 3 and 22 on which transparent electrodes for display and the like are opposed to each other with a predetermined gap, and a liquid crystal is placed in the facing gap hermetically sealed with a sealing material 23. The conductor terminal 4 connected to the display electrode and the conductor terminal 41 for external connection are exposed in the exposed portion of the glass substrate 3 which is filled.

【0005】そこで図18(ロ) に示す如く、ディスペンサ
24を使用してガラス基板3に、適量の半導体チップ実装
用接着剤5を滴下したのち、半導体チップ1は、図18
(ハ) に示す如くボンディングツール25の下面に吸着され
接着剤5の上方に搬送され、導体端子4,41に対し位置決
めされるようになる。
Therefore, as shown in FIG.
After dropping an appropriate amount of the semiconductor chip mounting adhesive 5 onto the glass substrate 3 using 24, the semiconductor chip 1 is
As shown in (c), it is adsorbed on the lower surface of the bonding tool 25, conveyed above the adhesive 5, and positioned with respect to the conductor terminals 4 and 41.

【0006】次いで、ボンディングツール25が降下する
またはガラス基板3が上昇して図18(ニ) に示す如く、半
導体チップ1に形成したバンプ2を端子4と41に当接せ
しめたのち、接着剤5の硬化処理を行うと図18(ホ) に示
すように、半導体チップ1の実装が完了する。
Next, the bonding tool 25 is lowered or the glass substrate 3 is raised so that the bumps 2 formed on the semiconductor chip 1 are brought into contact with the terminals 4 and 41 as shown in FIG. When the curing treatment of 5 is performed, the mounting of the semiconductor chip 1 is completed as shown in FIG.

【0007】このような従来方法において、ガラス基板
3に滴下し半導体チップ1によって押し拡げられたのち
硬化処理された接着剤5は、図18(ヘ) に示す如く、一般
に長方形である半導体チップ1とガラス基板3の間隙を
埋めた楕円形に拡がる。
In such a conventional method, the adhesive 5 which is dropped on the glass substrate 3 and spread by the semiconductor chip 1 and then cured is a generally rectangular semiconductor chip 1 as shown in FIG. And the glass substrate 3 is expanded into an elliptical shape.

【0008】[0008]

【発明が解決しようとする課題】以上説明したように、
接着剤を利用した従来の半導体チップ搭載方法は、バン
プ2が接着剤5を押し退けて導体端子4,41に接続し、半
導体チップ1とガラス基板3との間に充填された接着剤
5が、バンプ2と導体端子4,41の電気的接続を維持する
構成であり、かかる半導体チップ1の実装方法には、下
記のような問題点があった。
As described above,
In the conventional semiconductor chip mounting method using an adhesive, the bump 2 pushes the adhesive 5 away and connects to the conductor terminals 4 and 41, and the adhesive 5 filled between the semiconductor chip 1 and the glass substrate 3 is The structure for maintaining the electrical connection between the bump 2 and the conductor terminals 4 and 41 has the following problems in the mounting method of the semiconductor chip 1.

【0009】半導体チップ1とガラス基板3との間に
充填せしめ硬化させた接着剤5の収縮応力によって、半
導体チップ1は凹状に歪むようになる。その結果、半導
体チップ1の電気特性が変化する。
The shrinkage stress of the adhesive 5 filled between the semiconductor chip 1 and the glass substrate 3 and hardened causes the semiconductor chip 1 to be distorted into a concave shape. As a result, the electrical characteristics of the semiconductor chip 1 change.

【0010】半導体チップ1に設けられた多数個(例
えば数10個) のバンプ2の高さは、一般に2μm 程度で
あり、管理の難しいバンプ2の高さのばらつきによっ
て、接続不良(接触抵抗の過大)を生じることがある。
The height of a large number (for example, several tens) of bumps 2 provided on the semiconductor chip 1 is generally about 2 μm, and due to variations in the height of the bumps 2 which are difficult to manage, a connection failure (contact resistance Excessive) may occur.

【0011】バンプと導体端子との間に接着剤5が残
り易く、そのことによって接続不良(接触抵抗の過大)
を生じることがある。 ガラス基板3の寸法には接着剤5の拡がりを考慮する
必要であり、そのことによってガラス基板3が大形化さ
れる。
The adhesive 5 is likely to remain between the bump and the conductor terminal, which results in poor connection (excessive contact resistance).
May occur. It is necessary to consider the spread of the adhesive 5 in the dimension of the glass substrate 3, and thus the glass substrate 3 is upsized.

【0012】[0012]

【課題を解決するための手段】図1は本発明の基本構成
の説明図である。図1(イ) に示す如く半導体チップ(半
導体装置)1の所定部にはバンプ2を設け、図1(ロ) に
示す如く半導体チップ1を実装するガラス基板3には、
従来と同じ導体端子4と41を配設する。
FIG. 1 is an explanatory diagram of the basic configuration of the present invention. As shown in FIG. 1 (a), bumps 2 are provided on predetermined portions of a semiconductor chip (semiconductor device) 1, and as shown in FIG. 1 (b), a glass substrate 3 on which the semiconductor chip 1 is mounted is
The same conductor terminals 4 and 41 as the conventional one are arranged.

【0013】そして、図1(ハ) に示す如くガラス基板3
に半導体チップ1を実装するが、接着剤5-1はバンプ2
と導体端子4,41との接続部を覆い、かつ、半導体チップ
1とガラス基板3との間隙に充填しないようにする。
Then, as shown in FIG. 1C, the glass substrate 3
The semiconductor chip 1 is mounted on, but the adhesive 5 -1 is the bump 2
And the connecting portions of the conductor terminals 4 and 41 are covered, and the gap between the semiconductor chip 1 and the glass substrate 3 is not filled.

【0014】かかる接着剤5-1は、流動性のものを適量
だけバンプ2または導体端子4,41のバンプ2との接触部
に塗付するまたは、シート状のものを例えばバンプ列に
沿った短冊形状に切ってガラス基板3または半導体チッ
プ1に貼着して使用し、バンプ2を導体端子4,41に押圧
させた状態で加熱または紫外線照射等により硬化させ
る。
A suitable amount of such an adhesive 5 -1 is applied to the bumps 2 or the contact portions of the conductor terminals 4 and 41 with the bumps 2, or a sheet-like adhesive is applied along the bump row, for example. It is cut into strips and used by adhering it to the glass substrate 3 or the semiconductor chip 1, and the bumps 2 are cured by heating or irradiation with ultraviolet rays while being pressed against the conductor terminals 4 and 41.

【0015】さらに、例えば図1(ニ),(ホ) に示す如く本
発明における半導体装置のバンプ2 -1,2-5は、接続相手
の導体端子に当接する表面に横断溝12または、表面輪郭
を残した凹部18-1を形成し、バンプ先端部の塑性変形お
よびバンプと端子との間に挟まれた接着剤を押し退け易
くする、電気的接続用バンプと電気的接続に利用しない
ダミーバンプとを併用し、電気的接続用バンプと導体端
子の間に接着剤を挟まないようにすることを提案するも
のである。
Further, for example, as shown in FIGS.
Bump 2 of semiconductor device in invention -1, 2-FiveIs the connection partner
Crossing groove 12 or surface contour on the surface that abuts the conductor terminal of
Recessed part 18-1To prevent plastic deformation of the bump tip.
And the adhesive sandwiched between the bump and the terminal can be easily pushed out.
Do not use for electrical connection bumps and electrical connection
Used together with dummy bumps, electrical connection bumps and conductor ends
I suggest not to put an adhesive between the children
Of.

【0016】[0016]

【作用】上記手段において、ガラス基板3に半導体チッ
プ1を実装する接着剤5-1は、バンプ2と端子4,41との
接続部のみに被着し、その収縮応力によってバンプ2と
端子4,41との接続を従来のそれと同様に維持するように
作用すると共に、その接着力によって半導体チップ1を
ガラス基板3に固定させるようになる。しかし、接着剤
-1は半導体チップ1とガラス基板3との間隙に充填さ
れないため、その収縮応力はバンプ2と端子4,41との接
続部とその周辺に限定され、従来の接着剤による半導体
チップ1の歪が発生しないようになる。
In the above means, the adhesive 5 -1 for mounting the semiconductor chip 1 on the glass substrate 3 is applied only to the connecting portions between the bumps 2 and the terminals 4 and 41, and the contracting stress thereof causes the bumps 2 and the terminals 4 to be bonded. The semiconductor chip 1 is fixed to the glass substrate 3 by its adhesive force, while acting to maintain the connection with the terminals 41 and 41 as in the conventional case. However, since the adhesive 5 -1 is not filled in a gap between the semiconductor chip 1 and the glass substrate 3, the shrinkage stress is limited to the peripheral connection portion between the bump 2 and the terminal 4 and 41, by conventional adhesive The distortion of the semiconductor chip 1 will not occur.

【0017】かかる半導体チップ1の実装に際し、シー
ト状接着剤を使用するまたはダミーバンプを使用すれ
ば、バンプ2と端子4,41の間に接着剤を被着させないこ
とが可能であり、バンプ2と端子4,41の電気的接続は一
層確実なものとなる。
When the semiconductor chip 1 is mounted, if a sheet-like adhesive is used or dummy bumps are used, it is possible to prevent the adhesive from being applied between the bump 2 and the terminals 4 and 41. The electrical connection between the terminals 4 and 41 becomes more reliable.

【0018】また、上記手段においてバンプ表面に溝や
凹部を設けることは、バンプ先端部の塑性変形を容易、
かつ、バンプ2と端子4,41との間に挟まれた接着剤を押
し出しが容易となり、バンプと端子との接触抵抗を低減
可能とする。
Further, in the above means, providing the groove or recess on the bump surface facilitates plastic deformation of the tip of the bump.
In addition, the adhesive sandwiched between the bump 2 and the terminals 4 and 41 can be easily pushed out, and the contact resistance between the bump and the terminal can be reduced.

【0019】[0019]

【実施例】図2は本発明方法の第1の実施例の説明図、
図3は本発明方法の第2の実施例の説明図、図4は本発
明方法の第3の実施例の説明図、図5は本発明方法の第
4の実施例の説明図、図6は本発明方法の第5の実施例
の説明図、図7は本発明方法の第6の実施例の説明図、
図8は本発明方法の第7の実施例の説明図、図9は本発
明方法の第8の実施例の説明図、図10は本発明方法の第
9の実施例に使用するバンプ整形ツールの構成例の説明
図、図11は本発明方法の第9の実施例におけるバンプ整
形とバンプ接続方法の説明図、図12は本発明方法の第10
の実施例の説明図、図13は本発明方法の第11の実施例の
説明図、図14は本発明方法の第12の実施例の説明図、図
15は本発明方法の第13の実施例の説明図、図16は本発明
方法の第14の実施例に使用するバンプの説明図である。
FIG. 2 is an explanatory view of the first embodiment of the method of the present invention,
3 is an explanatory view of a second embodiment of the method of the present invention, FIG. 4 is an explanatory view of a third embodiment of the method of the present invention, FIG. 5 is an explanatory view of a fourth embodiment of the method of the present invention, and FIG. Is an explanatory view of a fifth embodiment of the method of the present invention, FIG. 7 is an explanatory view of a sixth embodiment of the method of the present invention,
8 is an explanatory view of a seventh embodiment of the present invention method, FIG. 9 is an explanatory view of an eighth embodiment of the present invention method, and FIG. 10 is a bump shaping tool used in the ninth embodiment of the present invention method. 11 is an explanatory view of a bump shaping and bump connecting method in the ninth embodiment of the present invention method, and FIG. 12 is a tenth embodiment of the present invention method.
13 is an explanatory view of an eleventh embodiment of the method of the present invention, FIG. 14 is an explanatory view of a twelfth embodiment of the method of the present invention, and FIG.
15 is an explanatory view of the 13th embodiment of the method of the present invention, and FIG. 16 is an explanatory view of bumps used in the 14th embodiment of the method of the present invention.

【0020】図2において、半導体チップ1には図2
(イ) に示す如く多数のバンプ2を配設し、ガラス基板3
には図2(ロ) に示す如く従来と同じ導体端子4と41を形
成し、さらに半導体チップ1には図2(ハ) に示す如く、
バンプ2を覆ってなるべく食み出さないように接着剤5
-1を塗付する。
The semiconductor chip 1 shown in FIG.
As shown in (a), a large number of bumps 2 are arranged and the glass substrate 3
As shown in FIG. 2B, the same conductor terminals 4 and 41 as the conventional one are formed on the semiconductor chip 1, and further, on the semiconductor chip 1, as shown in FIG.
Adhesive 5 that covers the bumps 2 so that it does not leak out
Apply -1 .

【0021】次いで、バンプ2が所定の導体端子4,41と
対向するように位置決めした半導体チップ1をガラス基
板3に向けて押圧し、加熱または紫外線照射等によって
接着剤5-1を硬化させると、図2(ニ) に示すように接着
剤5-1は、半導体チップ1とガラス基板3との対向間隙
に充填することなく、バンプ2と導体端子4,41との接続
部を覆うようになり、接着剤5-1の硬化に伴う収縮応力
は、バンプ2と導体端子4,41との電気的接続を維持する
と共に、半導体チップ1をガラス基板3の上に固定させ
るようになる。
Next, the semiconductor chip 1 positioned so that the bumps 2 face the predetermined conductor terminals 4 and 41 is pressed against the glass substrate 3 and the adhesive 5 -1 is cured by heating or ultraviolet irradiation. the adhesive 5 -1 as shown in FIG. 2 (d), without filling the opposing gap between the semiconductor chip 1 and the glass substrate 3, so as to cover the connection portions between the bump 2 and the conductor terminal 4, 41 The shrinkage stress associated with the curing of the adhesive 5 -1 maintains the electrical connection between the bump 2 and the conductor terminals 4 and 41 and fixes the semiconductor chip 1 on the glass substrate 3.

【0022】かかる半導体チップ1の実装方法において
接着剤5-1は、バンプ接続部のみに接着し、半導体チッ
プ1とガラス基板3との対向間隙に充填しないため、実
装に伴う半導体チップ1の変形(歪)が殆ど発生せず、
半導体チップ1の実装前の特性を変動させない。
The adhesive 5-1 is the mounting method of the semiconductor chip 1, adhered only to the bump connection portion without filling the opposing gap between the semiconductor chip 1 and the glass substrate 3, the deformation of the semiconductor chip 1 due to the mounting (Distortion) hardly occurs,
The characteristics of the semiconductor chip 1 before mounting are not changed.

【0023】図3において、表面に複数の溝状凹部12を
設けた多数のバンプ2-1は図3(イ)に示す如く、半導体
チップ1の外部接続用導体パッド11の上に配設する。凹
部12は、バンプ2-1をパッド11に接合させたのち、例え
ば型押し(スタンピング)によって形成する。
[0023] In FIG. 3, a large number of bumps 2 -1 having a plurality of groove-like recess 12 in the surface as shown in FIG. 3 (b), is disposed on the external connection conductor pads 11 of the semiconductor chip 1 . The recess 12 is formed by, for example, embossing (stamping) after the bump 2 -1 is bonded to the pad 11.

【0024】次いで、図3(ロ) に示す如く、バンプ2-1
を覆ってなるべく食み出さないように接着剤5-1を塗付
したのち、導体端子4,41が形成されたガラス基板3に半
導体チップ1を搭載し、半導体チップ1をガラス基板3
に向けて押圧しながら接着剤5-1を硬化させると、図3
(ハ) に示す如く、バンプ2-1を所定の導体端子4,41に接
続させた半導体チップ1の実装が完了する。
Next, as shown in FIG. 3B, the bump 2 -1
After given coating an adhesive 5 -1 to not protrude as much as possible over the, the semiconductor chip 1 is mounted on a glass substrate 3 that conductor terminal 4, 41 are formed, a glass substrate 3 of the semiconductor chip 1
When the adhesive 5-1 is cured while pressing it toward
As shown in (c), mounting of the semiconductor chip 1 is completed in which to connect the bump 2 -1 in a predetermined conductor terminal 4 and 41.

【0025】かかる半導体チップ1の実装方法において
接着剤5-1は、一部がバンプ2-1の凹部12を埋めてバン
プ接続部のみに接着し、半導体チップ1とガラス基板3
との対向間隙に充填しないため、実装に伴う半導体チッ
プ1の変形(歪)が殆ど発生せず、かつ、表面が平坦な
バンプ2を使用したときよりバンプ2-1と接着剤5-1
の接合面積が拡大するため、半導体チップ1をガラス基
板3に固定する固定力が増大する。
In the method of mounting the semiconductor chip 1, the adhesive 5 -1 partially fills the concave portion 12 of the bump 2 -1 , and adheres only to the bump connecting portion, so that the semiconductor chip 1 and the glass substrate 3 are bonded together.
Since the gaps facing each other are not filled, the semiconductor chip 1 is hardly deformed (distorted) due to mounting, and the bump 2 -1 and the adhesive 5 -1 are formed more than when the bump 2 having a flat surface is used. Since the bonding area of is increased, the fixing force for fixing the semiconductor chip 1 to the glass substrate 3 is increased.

【0026】図4において、半導体チップ1に形成した
多数の外部接続用導体パッド11の上に、金等にてなるバ
ンプ2-1を設ける。バンプ2-1の表面には図4(イ) に示
すように、複数の凹部12を例えば型押しによって形成し
たのち、図4(ロ) に示す如くバンプ2-1を覆い、かつ、
バンプ2-1からなるべく食み出さないように、接着剤5
-1を塗付する。
[0026] In FIG. 4, on the number of external connection conductor pads 11 formed on the semiconductor chip 1 is provided with a bump 2 -1 composed by gold or the like. As shown in FIG. 4 (a), a plurality of recesses 12 are formed on the surface of the bump 2 -1 , for example, by embossing, and then the bump 2 -1 is covered as shown in FIG. 4 (b), and
Adhesive 5 to prevent it from protruding from bump 2 -1 as much as possible
Apply -1 .

【0027】図4(ハ) において、透明電極(図示せず)
が形成されたガラス基板3には、透明電極に連通する導
体端子4-1と、外部接続用である導体端子41-1を形成
し、導体端子4-1, 41-1には、バンプ2-1に対向する複
数の突起(凹凸)13を、例えばエッチング法によって形
成する。
In FIG. 4C, a transparent electrode (not shown)
A conductor terminal 4 -1 communicating with the transparent electrode and a conductor terminal 41 -1 for external connection are formed on the glass substrate 3 on which the bumps 2 are formed on the conductor terminals 4 -1 , 41 -1. A plurality of protrusions (irregularities) 13 facing -1 are formed by, for example, an etching method.

【0028】そこで、凹部12の形成によるバンプ2-1
凸部と端子4-1, 41-1の突起13とが当接するように、半
導体チップ1を位置決めしたのち、半導体チップ1をガ
ラス基板3に向けて押圧し、加熱または紫外線照射等に
よって接着剤5-1を硬化させる。
Therefore, the semiconductor chip 1 is positioned so that the convex portion of the bump 2 -1 formed by forming the concave portion 12 and the protrusion 13 of the terminals 4 -1 , 41 -1 are brought into contact with each other, and then the semiconductor chip 1 is attached to the glass substrate. It is pressed toward 3, and the adhesive 5-1 is cured by heating, irradiation of ultraviolet rays, or the like.

【0029】すると、図4(ニ) に示す如く接着剤5
-1は、半導体チップ1とガラス基板3との対向間隙に充
填することなく、バンプ2-1と端子4-1およびバンプ2
-1と端子41-1との接続部を覆うように硬化し、バンプ2
-1と端子4-1, 41-1の電気的接続を接着剤5-1の収縮応
力で維持すると共に、半導体チップ1はガラス基板3の
上に固定させるようになる。
Then, as shown in FIG. 4D, the adhesive 5
-1 indicates the bump 2 -1 , the terminal 4 -1, and the bump 2 without filling the facing gap between the semiconductor chip 1 and the glass substrate 3.
-1 and the terminal 41 -1.
-1 and the terminals 4 -1 , 41 -1 are electrically connected by the contracting stress of the adhesive 5 -1 , and the semiconductor chip 1 is fixed on the glass substrate 3.

【0030】かかる半導体チップ1の実装方法において
接着剤5-1は、一部がバンプ2-1の凹部12および端子4
-1, 41-1の突起13形成に伴う凹所を埋めてバンプ接続部
のみに接着し、半導体チップ1とガラス基板3との対向
間隙に充填しないため、実装に伴う半導体チップ1の変
形(歪)が殆ど発生せず、かつ、表面に凹凸を設けない
バンプ2および導体子4を使用したときより半導体チッ
プ1の固定力が増大する。
In the method of mounting the semiconductor chip 1 as described above, the adhesive 5 -1 has a part of the recess 12 of the bump 2 -1 and the terminal 4.
−1 , 41 −1 fills the recesses due to the formation of the protrusions 13 and adheres only to the bump connection portions, and does not fill the facing gap between the semiconductor chip 1 and the glass substrate 3, so that the semiconductor chip 1 is deformed during mounting ( The fixing force of the semiconductor chip 1 is increased as compared with the case where the bump 2 and the conductor 4 in which the distortion is hardly generated and the surface is not provided with unevenness are used.

【0031】図5(イ) において、半導体チップ1には、
チップ内素子に連通する導体パッド11の上に位置するバ
ンプ2と、チップ内素子に連通しないダミーバンプ14と
を設ける。
In FIG. 5A, the semiconductor chip 1 has
The bumps 2 located on the conductor pads 11 communicating with the in-chip elements and the dummy bumps 14 not communicating with the in-chip elements are provided.

【0032】ダミーバンプ14は、バンプ2のそれぞれに
1対1で対応し、かつ、バンプ2の外側に位置してお
り、その表面は型押し等によって凹部13を形成すること
によって凸凹面とする。
The dummy bumps 14 correspond to the bumps 2 in a one-to-one manner and are located outside the bumps 2. The surface of the dummy bumps 14 is made uneven by forming depressions 13 by embossing or the like.

【0033】次いで、図5(ロ) に示す如くダミーバンプ
14を覆い、かつ、バンプ14からなるべく食み出さないよ
うに、特にバンプ2に被着しないように、接着剤5-1
塗付する。
Then, as shown in FIG. 5B, dummy bumps are formed.
An adhesive 5 -1 is applied so as to cover the bumps 14 and prevent the bumps 14 from protruding as much as possible, and in particular not to adhere to the bumps 2.

【0034】図5(ハ) において、透明電極(図示せず)
が形成されたガラス基板3には、該透明電極に連通し所
定のバンプ2および14に対向する導体端子4,41を設け
る。ただし、導体端子4はガラス基板3の透明電極に連
通し、導体端子41は外部接続用である。
In FIG. 5C, a transparent electrode (not shown)
The glass substrate 3 on which is formed is provided with conductor terminals 4 and 41 which communicate with the transparent electrode and face predetermined bumps 2 and 14. However, the conductor terminal 4 communicates with the transparent electrode of the glass substrate 3, and the conductor terminal 41 is for external connection.

【0035】そこで、接着剤5-1を下向きとした半導体
チップ1の所定のバンプ2,14が、ガラス基板3の所定の
導体端子4,41と対向するように、半導体チップ1を位置
決めしたのち、半導体チップ1をガラス基板3に向けて
押圧し、バンプ2が導体端子4,41に当接した状態で、加
熱または紫外線照射等によって接着剤5-1を硬化させ
る。
[0035] Therefore, given the bumps 2, 14 of the semiconductor chip 1 in which the adhesive 5 -1 and downward so as to face the predetermined conductor terminals 4 and 41 of the glass substrate 3, after positioning the semiconductor chip 1 , The semiconductor chip 1 is pressed toward the glass substrate 3, and the adhesive 5 -1 is cured by heating or ultraviolet irradiation while the bumps 2 are in contact with the conductor terminals 4 and 41.

【0036】すると、図5(ニ) に示す如く接着剤5
-1は、半導体チップ1とガラス基板3との対向間隙に充
填することなく、バンプ14と導体端子4,41との接続部を
覆うように硬化し、バンプ2と導体端子4,41の電気的接
続および半導体チップ1とガラス基板3との接合は、硬
化させた接着剤5-1の収縮応力と接着力で維持されるよ
うになる。
Then, as shown in FIG. 5D, the adhesive 5
-1 is cured so as to cover the connecting portion between the bump 14 and the conductor terminals 4 and 41 without filling the facing gap between the semiconductor chip 1 and the glass substrate 3, and the electrical conductivity of the bump 2 and the conductor terminals 4 and 41 is increased. The physical connection and the bonding between the semiconductor chip 1 and the glass substrate 3 are maintained by the shrinkage stress and the adhesive force of the cured adhesive 5 -1 .

【0037】かかる半導体チップ1の実装方法におい
て、ダミーバンプ14の先端部は凹部13の形成により塑性
変形し易くしてあり、パッド11を含むバンプ2の高さを
h,バンプ14の高さをh-1としたとき h<h-1 とし、かつ、バンプ高さhとh-1との差をバンプ14の先
端部の塑性変形容易幅内とすれば、バンプ2と導体端子
4,41との接続は、接続間に接着剤5-1の膜が形成される
心配をなくし容易,確実になると共に、接着剤5-1を半
導体チップ1とガラス基板3との対向間隙に充填しない
ため、実装に伴う半導体チップ1の変形(歪)が殆ど発
生しないようになる。
In the method of mounting the semiconductor chip 1, the tip of the dummy bump 14 is easily plastically deformed by forming the recess 13, and the height of the bump 2 including the pad 11 is h and the height of the bump 14 is h. −1 , h <h −1 , and if the difference between the bump heights h and h −1 is within the plastic deformation easy width of the tip of the bump 14, the bump 2 and the conductor terminal
Connection with the 4 and 41 are readily eliminate fear of film of adhesive 5 -1 is formed between the connection, it becomes ensured, an adhesive 5 -1 opposing gap between the semiconductor chip 1 and the glass substrate 3 Since the filling is not performed, the deformation (distortion) of the semiconductor chip 1 due to the mounting hardly occurs.

【0038】図6(イ) において、半導体チップ1には、
各導体パッド11の上に複数個の小型金属バンプ2-2、例
えば前出のバンプ2,2-1の表面が 100μm × 100μm で
あるとき、例えば表面が 100μm ×30μm または30μm
×30μm である複数個のバンプ2-2を設ける。
In FIG. 6 (a), the semiconductor chip 1 has
When a plurality of small metal bumps 2-2 over each contact pad 11, for example, bumps 2,2 -1 surface of supra is 100 [mu] m × 100 [mu] m, for example surface 100 [mu] m × 30 [mu] m or 30 [mu] m
A plurality of bumps 2 -2 having a size of 30 μm are provided.

【0039】そこで、同一のパッド11に設けた複数個の
バンプ2-2を覆い、かつ、パッド11からなるべく食み出
さないように、特にパッド11の内側に被着しないよう
に、接着剤5-1を塗付し、前記実施例の半導体チップ1
と同様に、導体端子4,41が形成されたガラス基板3に半
導体チップ1を搭載する。
Therefore, the adhesive 5 is provided so as to cover the plurality of bumps 2 -2 provided on the same pad 11 and to prevent the bumps 2 -2 from protruding as much as possible, and in particular not to adhere to the inside of the pad 11. -1 is applied to the semiconductor chip 1 of the above embodiment
Similarly, the semiconductor chip 1 is mounted on the glass substrate 3 on which the conductor terminals 4 and 41 are formed.

【0040】次いで、加熱または紫外線照射等によって
接着剤5-1を硬化させると図6(ロ)に示す如く、半導体
チップ1とガラス基板3との対向間隙に充填されること
なく、バンプ2-2と導体端子4,41とは電気的に接続し、
半導体チップ1がガラス基板3に固定され、その電気的
接続と固定は接着剤5-1の収縮応力と接着力によって維
持されるようになる。
[0040] Then, when the adhesive is cured 5 -1 by heating or ultraviolet irradiation, or the like as shown in FIG. 6 (b), without being filled in the opposing gap between the semiconductor chip 1 and the glass substrate 3, the bump 2 - 2 and the conductor terminals 4 and 41 are electrically connected,
The semiconductor chip 1 is fixed to the glass substrate 3, fixed and their electrical connection will be maintained by the adhesive force and contraction stress of adhesive 5-1.

【0041】かかる半導体チップ1の実装方法、即ち複
数個の小型バンプ2-2を使用した半導体チップ1の実装
方法は、バンプ2-2がバンプ2のそれより塑性変形容易
であるため、同一チップ1に設けた多数のバンプ2の高
さにばらつきがあったとしても、半導体チップ実装時の
電気的接続不良をなくすことができる。
The mounting method of the semiconductor chip 1, that is, the mounting method of the semiconductor chip 1 using a plurality of small bumps 2 -2 is the same chip because the bump 2 -2 is more easily plastically deformed than that of the bump 2. Even if there are variations in the height of the large number of bumps 2 provided on the semiconductor device 1, it is possible to eliminate the electrical connection failure when mounting the semiconductor chip.

【0042】図7(イ) において、半導体チップ1には、
導体パッド11の上に金属バンプ2-1を設けると共に、各
バンプ2-1の内側にはチップ内素子に接続されないダミ
ーバンプ14を設け、ダミーバンプ14には、バンプ2-1
凹所13と同様な凹所15を設ける。
In FIG. 7A, the semiconductor chip 1 has
A metal bump 2 -1 is provided on the conductor pad 11, and a dummy bump 14 that is not connected to an in-chip element is provided inside each bump 2 -1 . The dummy bump 14 has the same shape as the recess 13 of the bump 2 -1. A recess 15 is provided.

【0043】そこで、バンプ14を覆ってバンプ14の内側
および外側になるべく食み出さないように、バンプ14に
接着剤5-1を塗付し、前記実施例の半導体チップ1と同
様に、導体端子4,41が形成されたガラス基板3に半導体
チップ1を搭載する。
[0043] Therefore, so as not possible protrude inside and outside of the bump 14 covering the bumps 14 are denoted by coating an adhesive 5 -1 bump 14, as in the semiconductor chip 1 of the embodiment, the conductor The semiconductor chip 1 is mounted on the glass substrate 3 on which the terminals 4 and 41 are formed.

【0044】次いで、加熱または紫外線照射等によって
接着剤5-1を硬化させると図7(ロ)に示す如く、半導体
チップ1とガラス基板3との対向間隙に充填されること
なく、バンプ2-1と導体端子4,41とは電気的に接続し、
半導体チップ1がガラス基板3に固定されるようにな
る。
[0044] Then, when the adhesive is cured 5 -1 by heating or ultraviolet irradiation, or the like as shown in FIG. 7 (b), without being filled in the opposing gap between the semiconductor chip 1 and the glass substrate 3, the bump 2 - 1 and the conductor terminals 4 and 41 are electrically connected,
The semiconductor chip 1 is fixed to the glass substrate 3.

【0045】かかる半導体チップ1の実装方法におい
て、パッド11を含むバンプ2-1の高さをh,バンプ14の
高さをh-1としたとき h<h-1 とし、かつ、バンプ高さhとh-1との差をバンプ14の先
端部の塑性変形容易幅内とすれば、バンプ2-1と端子4,
41との接続は、接続間に接着剤5-1の膜が形成される心
配をなくし容易,確実になると共に、接着剤5-1を半導
体チップ1とガラス基板3との対向間隙に充填しないた
め、実装に伴う半導体チップ1の変形(歪)が殆ど発生
しないようになる。
In the mounting method of the semiconductor chip 1, when the height of the bump 2 -1 including the pad 11 is h and the height of the bump 14 is h -1 , h <h -1 and the bump height is Assuming that the difference between h and h −1 is within the plastic deformation easy width of the tip of the bump 14, the bump 2 −1 and the terminal 4,
The connection with 41 is easy and reliable without the concern that a film of the adhesive 5 -1 is formed between the connections, and the adhesive 5 -1 is not filled in the facing gap between the semiconductor chip 1 and the glass substrate 3. Therefore, the deformation (distortion) of the semiconductor chip 1 due to the mounting hardly occurs.

【0046】図8(イ) において、半導体チップ1の導体
パッド11の上には、金属基体18, 金属基体18の上に形成
し硬化させた樹脂体16, 金属基体18の露呈面および樹脂
体16を覆うはんだ層17にてなるバンプ2-3を形成する。
In FIG. 8A, on the conductor pad 11 of the semiconductor chip 1, a metal base 18, a resin body 16 formed on the metal base 18 and cured, an exposed surface of the metal base 18, and a resin body A bump 2 -3 made of a solder layer 17 covering 16 is formed.

【0047】そこで、バンプ2-3を覆い、かつ、バンプ
-3からなるべく食み出さないように、バンプ2-3に接
着剤5-1を塗付し、前記実施例の半導体チップ1と同様
に、導体端子4(および41) が形成されたガラス基板3
に半導体チップ1を搭載する。
[0047] Therefore, to cover the bump 2 -3, and so as not possible protrude from the bump 2 -3, denoted coating the adhesive 5 -1 the bump 2 -3, and the semiconductor chip 1 of the embodiment Similarly, the glass substrate 3 on which the conductor terminals 4 (and 41) are formed
The semiconductor chip 1 is mounted on.

【0048】次いで、樹脂体16が適当に押し潰されて広
がる押圧力で、半導体チップ1をガラス基板3に押圧
し、加熱または紫外線照射等によって接着剤5-1を硬化
させると図8(ロ) に示す如く、半導体チップ1とガラス
基板3との対向間隙に充填されることなく、バンプ2-3
と導体端子4 (および41) との電気的接続および、半導
体チップ1とガラス基板3との機械的接続は、接着剤5
-1により維持されるようになる。
Then, the semiconductor chip 1 is pressed against the glass substrate 3 with a pressing force that the resin body 16 is appropriately crushed and spread, and the adhesive 5-1 is cured by heating or ultraviolet irradiation, as shown in FIG. ), The bump 2-3 is not filled in the facing gap between the semiconductor chip 1 and the glass substrate 3.
And the conductor terminal 4 (and 41) and the semiconductor chip 1 and the glass substrate 3 are mechanically connected by the adhesive 5
It will be maintained by -1 .

【0049】図9(イ) において、半導体チップ1の導体
パッド11の上には、一対の樹脂体16 -1, 樹脂体16-1を覆
うはんだ層17にてなるバンプ2-4を形成する。そこで、
バンプ2-4を覆い、かつ、バンプ2-4からなるべく食み
出さないように、バンプ2-4に接着剤5-1を塗付し、前
記実施例の半導体チップ1と同様に、導体端子4 (およ
び41) が形成されたガラス基板3に半導体チップ1を搭
載する。
In FIG. 9A, the conductor of the semiconductor chip 1
On the pad 11, a pair of resin bodies 16 -1, Resin body 16-1Cover
Bump 2 consisting of solder layer 17-FourTo form. Therefore,
Bump 2-FourAnd bump 2-FourEat as much as possible
Bump 2 so that it does not come out-FourTo the adhesive 5-1And apply
Like the semiconductor chip 1 of the above-described embodiment, the conductor terminals 4 (and
The semiconductor chip 1 is mounted on the glass substrate 3 on which
List.

【0050】次いで、樹脂体16-1が適当に押し潰されて
広がる押圧力で、半導体チップ1をガラス基板3に押圧
し、加熱または紫外線照射等によって接着剤5-1を硬化
させると図9(ロ) に示す如く、半導体チップ1とガラス
基板3との対向間隙に充填されることなく、バンプ2-4
と導体端子4 (および41) との電気的接続および、半導
体チップ1とガラス基板3との機械的接続は、接着剤5
-1により維持されるようになる。
Next, when the semiconductor chip 1 is pressed against the glass substrate 3 with a pressing force that the resin body 16 -1 is appropriately crushed and spreads, and the adhesive 5 -1 is cured by heating or ultraviolet irradiation, the result is shown in FIG. as shown in (b), without being filled in the opposing gap between the semiconductor chip 1 and the glass substrate 3, the bump 2 -4
And the conductor terminal 4 (and 41) and the semiconductor chip 1 and the glass substrate 3 are mechanically connected by the adhesive 5
It will be maintained by -1 .

【0051】図10において、(イ),(ロ),(ハ),(ニ) は本発明
に係わる金属バンプの斜視図、(ホ)は(イ) に示す金属バ
ンプ表面の凹部整形ツールの側面図、(ヘ) は(ホ) に示す
ツールの先端面の平面図である。
In FIG. 10, (a), (b), (c) and (d) are perspective views of the metal bump according to the present invention, and (e) is a tool for shaping the concave portion of the metal bump surface shown in (a). A side view, (f) is a plan view of the tip surface of the tool shown in (e).

【0052】図10(イ) において、金等にてなる金属バン
プ2-5は、接続相手の導体端子に当接する表面に、表面
輪郭を残した円環状凹部18-1を形成してなり、凹部18-1
は図10(ホ),(ヘ) に示す整形ツール31の先端面32、即ち、
凹部18-1に対応する円環状の凹部33を形成した先端面32
をバンプ2-5の表面に押圧して形成する。
[0052] In FIG. 10 (b), the metal bumps 2 -5 consisting by gold or the like, in contact with the surface conductor terminal is connected are made to form an annular recess 18 -1 leaving a surface profile, Recess 18 -1
Is the tip surface 32 of the shaping tool 31 shown in FIGS.
Tip surface 32 having an annular recess 33 corresponding to the recess 18 -1
Are formed by pressing on the surface of the bump 2 -5 .

【0053】図10(ロ) において、金等にてなる金属バン
プ2-6は、接続相手の導体端子に当接する表面に、表面
輪郭を残した角形凹部18-2を形成してなる。凹部18-2
ツール31と同様な押圧ツール、即ち凹部18-2に対応する
凹部を先端面に形成るしたツールによって形成する。
[0053] In FIG. 10 (b), the metal bumps 2 -6 made by gold and the like, in contact with the surface conductor terminal is connected are obtained by forming a rectangular recess 18 -2 leaving a surface profile. The recess 18 -2 is formed by a pressing tool similar to the tool 31, that is, a tool in which a recess corresponding to the recess 18 -2 is formed on the tip surface.

【0054】図10(ハ) において、金等にてなる金属バン
プ2-7は、接続相手の導体端子に当接する表面に、表面
輪郭を残した十字形凹部18-3を形成してなる。凹部18-3
はツール31と同様な押圧ツール、即ち凹部18-3に対応す
る凹部を先端面に形成したツールによって形成する。
[0054] In FIG. 10 (c), the metal bumps 2 -7 made by gold and the like, in contact with the surface conductor terminal is connected are obtained by forming a cross-shaped recess 18 -3 leaving a surface profile. Recess 18 -3
Is formed by a pressing tool similar to the tool 31, that is, a tool in which a concave portion corresponding to the concave portion 18 -3 is formed on the tip surface.

【0055】図10(ニ) において、金等にてなる金属バン
プ2-8は、接続相手の導体端子に当接する表面に、表面
輪郭を残したV字形凹部18-4を形成してなる。凹部18-4
はツール31と同様な押圧ツール、即ち凹部18-4に対応す
る凹部を先端面に形成したツールによって形成する。
In FIG. 10 (d), a metal bump 2-8 made of gold or the like has a V-shaped recess 18-4 having a surface contour left on the surface which contacts the conductor terminal of the connection partner. Recess 18 -4
Is formed by a pressing tool similar to the tool 31, that is, a tool in which a concave portion corresponding to the concave portion 18 -4 is formed on the tip surface.

【0056】以下に、図11を用いて金属バンプ2-5の整
形方法と金属バンプ2-5を導体端子4(または41) に接
続する方法を説明する。図11(イ) において、半導体チッ
プ1の所定部に金属バンプ2を形成したのち、図11(ロ)
に示す如く金属バンプ2の表面にツール31の先端面32を
押圧すると、図11(ハ) の平面図に示す如く、表面に円環
状凹部18-1が形成されたバンプ2-5が完成する。
[0056] In the following, the shaping method and the metal bumps 2 -5 metal bumps 2 -5 explaining how to connect to a conductor terminal 4 (or 41) with reference to FIG. 11. In FIG. 11 (a), after the metal bumps 2 are formed on the predetermined portions of the semiconductor chip 1, FIG.
When the tip surface 32 of the tool 31 is pressed against the surface of the metal bump 2 as shown in Fig. 11, the bump 2-5 having the annular recess 18 -1 formed on the surface is completed as shown in the plan view of Fig. 11C. .

【0057】そこで、図11(ニ) に示す如くガラス基板3
の導体端子4(および41) の上に接着剤5-1を塗付した
のち、図11(ホ) に示す如く導体端子4に対して半導体チ
ップ1を位置決めしたのち、図11(ヘ) に示す如くバンプ
-5を導体端子4に当接せしめ、接着剤5-1の硬化処理
を施して半導体チップ1の実装が完了する。
Therefore, as shown in FIG. 11D, the glass substrate 3
After given coating an adhesive 5 -1 over the conductor terminal 4 (and 41), then positioning the semiconductor chip 1 to the conductor terminal 4 as shown in FIG. 11 (e), 11 (f) As shown, the bumps 2 -5 are brought into contact with the conductor terminals 4, and the adhesive 5 -1 is cured to complete the mounting of the semiconductor chip 1.

【0058】かかる半導体チップ1の実装方法は、バン
プ2-5の先端面が接着剤5-1を押し退けて導体端子4に
当接し、該先端面と導体端子4との間に挟まれた接着剤
-1は、一部がバンプ先端面の外側に押し出されると共
に、他の一部は凹部18-1内に押し出され、バンプ2-5
導体端子4の電気的接続が確実になる。
In the method of mounting the semiconductor chip 1, the tip surface of the bump 2 -5 pushes the adhesive 5 -1 to contact the conductor terminal 4, and the adhesive sandwiched between the tip surface and the conductor terminal 4 is applied. A part of the agent 5 -1 is extruded to the outside of the tip end surface of the bump and the other part is extruded into the recess 18 -1 , so that the electrical connection between the bump 2 -5 and the conductor terminal 4 is ensured.

【0059】そして、バンプ2-6,2-7,2-8に形成した凹
部18-2または18-3または18-4は、凹部18-1と同じ役割を
果たし、バンプ2-6,2-7,2-8の電気的接続の確実性を寄
与する。
The recesses 18 -2 or 18 -3 or 18 -4 formed in the bumps 2 -6 , 2 -7 , 2 -8 play the same role as the recesses 18 -1 and the bumps 2 -6 , 2 -7, contributes to the reliability of electrical connection 2 -8.

【0060】図12に示す実施例は、バンプ2-5を導体端
子4(および41) に接続する接着剤の他の被着方法に関
するものである。図12(イ) において、接着剤転写板36の
表面に接着剤37を均一に塗付、例えばスクリーン印刷,
スキージを使用する均し方法によって塗付する。
The embodiment shown in FIG. 12 relates to another method of applying an adhesive which connects the bumps 2-5 to the conductor terminals 4 (and 41). In FIG. 12 (a), the adhesive 37 is evenly applied to the surface of the adhesive transfer plate 36, for example, by screen printing,
Apply by a leveling method using a squeegee.

【0061】次いで、図12(ロ) に示す如く接着剤転写ツ
ール38、即ち、バンプ2-5の凹部18 -1に対応する突起が
形成されたツール38の先端面を接着剤37に当接せしめ、
図12(ハ) に示す如く接着剤37の一部37-1をツール38の先
端面に被着させる。
Next, as shown in FIG. 12B, an adhesive transfer tool is prepared.
38, that is, bump 2-FiveThe recess of 18 -1The protrusion corresponding to
Abut the tip surface of the formed tool 38 with the adhesive 37,
As shown in Fig. 12 (c), part of the adhesive 37-1The tool 38 tip
Apply to the end face.

【0062】次いで、図12(ニ) に示す如く、ツール38の
接着剤37-1をバンプ2-5の凹部18-1に転写させたのち、
図12(ホ) に示す如くバンプ2-5の先端面を導体端子4
(および41) に当接せしめ、接着剤37-1の硬化処理を行
い、しかるのち、バンプ2-5の周囲に接着剤39を被着さ
せてその硬化処理を行うと図12(ヘ) に示す如く、半導体
チップ1の実装が完了する。
Next, as shown in FIG. 12D, after the adhesive 37 -1 of the tool 38 is transferred to the recesses 18 -1 of the bumps 2 -5 ,
As shown in Fig. 12 (e), attach the tip of the bump 2 -5 to the conductor terminal 4
(And 41), the adhesive 37 -1 is cured, and then the adhesive 39 is applied to the periphery of the bump 2 -5 and the curing is performed. As shown, the mounting of the semiconductor chip 1 is completed.

【0063】かかる半導体チップ1の実装方法は、バン
プ2-5の先端面と導体端子4との間に接着剤37-1および
39が被着しない。そのため、バンプ2-5と導体端子4と
の電気的接続の確実性が増すようになる。
The mounting method of the semiconductor chip 1 is such that the adhesive 37 -1 and the adhesive 37 -1 are provided between the tip surface of the bump 2 -5 and the conductor terminal 4.
39 does not wear. Therefore, the reliability of the electrical connection between the bump 2-5 and the conductor terminal 4 is increased.

【0064】図13において、(イ) は半導体チップ搭載用
接着剤シート51の斜視図、(ロ) は接着剤シート51をガラ
ス基板3に接着した側面図、(ハ) はガラス基板3に半導
体チップ1を搭載した側面図、(ニ) は搭載した半導体チ
ップ1の一部を破断除去した平面図である。
In FIG. 13, (a) is a perspective view of the semiconductor chip mounting adhesive sheet 51, (b) is a side view of the adhesive sheet 51 bonded to the glass substrate 3, and (c) is a semiconductor substrate on the glass substrate 3. FIG. 3 is a side view of the chip 1 mounted, and (d) is a plan view in which a part of the mounted semiconductor chip 1 is broken and removed.

【0065】図13(イ) において、接着剤シート51は半導
体チップ1の四辺に設けられた多数のバンプ2に対向す
るロ字形であり、接着剤フィルム51-1を保護膜51-2と51
-3とで挟んだサンドイッチ構成である。
In FIG. 13 (a), the adhesive sheet 51 has a square shape that faces a large number of bumps 2 provided on the four sides of the semiconductor chip 1, and the adhesive film 51 -1 and the protective films 51-2 and 51-2.
-3 is sandwiched between.

【0066】そこで、まず保護膜51-2を剥離して図13
(ロ) に示す如く、接着剤フィルム51-1をガラス基板3に
接着する。その接着剤51-1は、ガラス基板3に形成した
導体端子4および41のバンプ接続部を覆うようにする。
Therefore, first, the protective film 51-2 is peeled off, and the structure shown in FIG.
As shown in (b), the adhesive film 51 -1 is adhered to the glass substrate 3. The adhesive 51 -1 covers the bump connecting portions of the conductor terminals 4 and 41 formed on the glass substrate 3.

【0067】次いで、保護膜51-3を剥離したのち、位置
決めした半導体チップ1をガラス基板3に向けて押圧
し、バンプ2を導体端子4,41に当接 (接続) せしめ接着
剤フィルム51-1の硬化処理を施すと、図13(ハ) に示す如
く半導体チップ1の搭載が完了する。
[0067] Then, the protective film 51 -3 After peeled, the semiconductor chip 1 is positioned and pressed against the glass substrate 3, contact bumps 2 to the conductor terminal 4, 41 (connection) allowed the adhesive film 51 - When the hardening process 1 is performed, the mounting of the semiconductor chip 1 is completed as shown in FIG.

【0068】かかる半導体チップ1の搭載において、バ
ンプ2に替えてバンプ2-1または2 -2または2-3または
-4または2-5を形成した半導体チップ1の搭載が可能
であり、半導体チップ1とガラス基板3との間には図13
(ハ),(ニ) に示す如く、空洞52が形成され、そのことによ
って半導体チップ1には、実装に伴う歪 (特性の変動)
が生じないようになる。
In mounting the semiconductor chip 1 as described above,
Bump 2 instead of bump 2-1Or 2 -2Or 2-3Or
Two-FourOr 2-FiveIt is possible to mount semiconductor chip 1 with
In addition, between the semiconductor chip 1 and the glass substrate 3 is shown in FIG.
As shown in (c) and (d), a cavity 52 is formed, which
Therefore, the semiconductor chip 1 is distorted due to mounting (variation of characteristics).
Will not occur.

【0069】図14において、(イ) は半導体チップ搭載用
接着剤シート56の斜視図、(ロ) は接着剤シート56の接着
剤フィルム56-1をガラス基板3に接着した平面図、(ハ)
は接着剤シート56の保護膜56-3を剥離した平面図であ
る。
In FIG. 14, (a) is a perspective view of the semiconductor chip mounting adhesive sheet 56, (b) is a plan view in which the adhesive film 56 -1 of the adhesive sheet 56 is bonded to the glass substrate 3, (c) )
FIG. 6 is a plan view of the adhesive sheet 56 with the protective film 56 -3 removed.

【0070】図14(イ) において、接着剤シート56は半導
体チップ1の多数のバンプ2に対向するロ字形、かつ、
一辺に切り欠き57を有する形状、即ち接着剤シート56に
欠き溝57を形成した形状であり、接着剤フィルム56-1
保護膜56-2と56-3とで挟んだサンドイッチ構成である。
In FIG. 14 (a), the adhesive sheet 56 has a square shape facing the many bumps 2 of the semiconductor chip 1 and
It has a notch 57 on one side, that is, a shape in which a groove 57 is formed in an adhesive sheet 56, and has a sandwich structure in which an adhesive film 56 -1 is sandwiched between protective films 56 -2 and 56 -3 .

【0071】かかる接着剤シート56は、接着剤シート51
と同様に使用し半導体チップ1の実装に使用する。即
ち、図14(ロ) 示す如く保護膜56-2を剥離して接着剤フィ
ルム56 -1をガラス基板3に接着したのち、図14(ハ) に示
す如く保護膜56-3を剥離して接着剤フィルム56-1の上に
一点鎖線で示す半導体チップ1を載せ、その半導体チッ
プ1をガラス基板3に向けて押圧した状態で接着剤56-1
の硬化処理を行って、半導体チップ1の搭載が完了す
る。
The adhesive sheet 56 is the adhesive sheet 51.
It is used in the same manner as described above and used for mounting the semiconductor chip 1. Immediately
Then, as shown in FIG.-2Peel off the adhesive
Rum 56 -1After bonding to the glass substrate 3, it is shown in Fig. 14 (c).
As protective film 56-3Peel off the adhesive film 56-1On top of the
Place the semiconductor chip 1 indicated by the one-dot chain line, and
Adhesive 56 with the tape 1 pressed against the glass substrate 3-1
The semiconductor chip 1 is completely mounted by carrying out the hardening process of
It

【0072】かかる半導体チップ1の搭載において、バ
ンプ2に替えてバンプ2-1または2 -2または2-3または
-4または2-5を形成した半導体チップ1の搭載が可能
であり、半導体チップ1とガラス基板3との間には、接
着剤シート51を使用したときと同様な空洞が形成され
る。
When mounting the semiconductor chip 1 as described above,
Bump 2 instead of bump 2-1Or 2 -2Or 2-3Or
Two-FourOr 2-FiveIt is possible to mount semiconductor chip 1 with
Therefore, there is no contact between the semiconductor chip 1 and the glass substrate 3.
A cavity similar to that when using the adhesive sheet 51 is formed.
It

【0073】そのような空洞は、実装に伴う半導体チッ
プ1の歪 (特性の変動) を防止し、切り欠き57は、半導
体チップ実装における空洞内空気を外部に逃がす (空洞
内空気圧を大気と同じにする) 。従って、本実施例によ
る半導体チップ1の実装歪は、図13を用いて説明した実
施例よりさらに減少することになる。
Such a cavity prevents distortion (variation in characteristics) of the semiconductor chip 1 due to mounting, and the notch 57 allows air inside the cavity in mounting the semiconductor chip to escape to the outside (air pressure inside the cavity is the same as atmospheric air). To). Therefore, the mounting distortion of the semiconductor chip 1 according to this embodiment is further reduced as compared with the embodiment described with reference to FIG.

【0074】図15において、(イ) は半導体チップ搭載用
短冊形接着剤フィルム58の説明図、(ロ) は半導体チップ
搭載用コ字形接着剤フィルム59の説明図、(ハ) は半導体
チップ搭載用の窓明きコ字形接着剤フィルム60の説明図
である。
In FIG. 15, (a) is an explanatory view of a strip-shaped adhesive film 58 for mounting a semiconductor chip, (b) is an explanatory view of a U-shaped adhesive film 59 for mounting a semiconductor chip, and (c) is a semiconductor chip mounting. FIG. 6 is an explanatory view of a window opening U-shaped adhesive film 60 for use in a computer.

【0075】図15(イ) において、一点鎖線で示す一対の
短冊形接着剤フィルム58は、下面に貼着された保護膜
(図示せず)を剥離して、導体端子4,41が二列に形成さ
れたガラス基板3に貼着したのち、上面に貼着した保護
膜(図示せず)を剥離し、導体端子4,41の先端のバンプ
当接部は、図15(イ) において、一点鎖線で示す一対の短
冊形接着剤フィルム58は、下面に貼着された保護膜を剥
離してガラス基板3に貼着したのち、上面に貼着した保
護膜を剥離し、導体端子4,41の先端のバンプ当接部を覆
うようにする。
In FIG. 15 (a), a pair of strip-shaped adhesive films 58 indicated by alternate long and short dash lines are formed by removing a protective film (not shown) attached to the lower surface of the adhesive film 58 so that the conductor terminals 4 and 41 are arranged in two rows. After being adhered to the glass substrate 3 formed in step 1, the protective film (not shown) adhered to the upper surface is peeled off, and the bump contact portions at the tips of the conductor terminals 4 and 41 are as shown in FIG. The pair of strip-shaped adhesive films 58 shown by the one-dot chain line peels off the protective film stuck on the lower surface and sticks it on the glass substrate 3, and then peels off the protective film stuck on the upper surface, Cover the bump contact part at the tip of 41.

【0076】かかる接着剤フィルム58は、前記接着剤フ
ィルム56-1と同様に半導体チップ1の実装に利用、即
ち、接着剤フィルム58の上に載せた半導体チップ1をガ
ラス基板3に向けて押圧し、その状態で硬化処理するよ
うになる。
[0076] The adhesive film 58, the available adhesive film 56 -1 similarly to the mounting semiconductor chip 1, i.e., a semiconductor chip 1 placed on the adhesive film 58 toward the glass substrate 3 presses Then, the curing process is performed in that state.

【0077】図15(ロ) において、一点鎖線で示すコ字形
接着剤フィルム59は、下面に貼着された保護膜を剥離し
てガラス基板3に貼着したのち、上面に貼着した保護膜
を剥離し、導体端子4,41の先端のバンプ当接部を覆うよ
うにする。
In FIG. 15B, the U-shaped adhesive film 59 indicated by the alternate long and short dash line is the protective film adhered on the upper surface after the protective film adhered on the lower surface is peeled off and adhered on the glass substrate 3. Is peeled off to cover the bump contact portions at the tips of the conductor terminals 4, 41.

【0078】かかる接着剤フィルム59は、前記接着剤フ
ィルム56-1および58と同様に半導体チップ1の実装に利
用、即ち、接着剤フィルム59の上に載せた半導体チップ
1をガラス基板3に向けて押圧し、その状態で硬化処理
するようになる。
The adhesive film 59 is used for mounting the semiconductor chip 1 similarly to the adhesive films 56-1 and 58, that is, the semiconductor chip 1 placed on the adhesive film 59 is directed to the glass substrate 3. And press, and the curing process is performed in that state.

【0079】図15(ハ) において、コ字形接着剤フィルム
60はコ字形の三辺に透孔60-1と60-2と60-3を形成してな
り、下面に貼着された保護膜を剥離してガラス基板3に
貼着したのち、上面に貼着した保護膜を剥離した接着剤
フィルム60の透孔60-1, 60-2, 60-3内には、導体端子4
および41の先端のバンプ当接部が露呈するようにする。
In FIG. 15C, a U-shaped adhesive film
The 60 is formed by forming through holes 60 -1 , 60 -2 and 60 -3 on three sides of the U-shape. After peeling off the protective film attached to the lower surface and attaching it to the glass substrate 3, it is attached to the upper surface. The conductor terminal 4 is placed in the through holes 60 -1 , 60 -2 , 60 -3 of the adhesive film 60 from which the attached protective film has been peeled off.
And the bump contact portions at the tips of 41 are exposed.

【0080】かかる接着剤フィルム60は、前記接着剤フ
ィルム56-1および58および59と同様に半導体チップ1の
実装に利用、即ち、接着剤フィルム60の上に載せた半導
体チップ1をガラス基板3に向けて押圧し、その状態で
硬化処理するようになる。そして、透孔60-1, 60-2, 60
-3を設け、導体端子4または41の先端バンプ当接部に重
ならないため、バンプの電気的接続に対する信頼性は、
接着剤フィルム56-1または58または59を使用したものよ
り高くなる。
The adhesive film 60 is used for mounting the semiconductor chip 1 similarly to the adhesive films 56-1, 58 and 59, that is, the semiconductor chip 1 placed on the adhesive film 60 is attached to the glass substrate 3. It is pressed toward, and the curing process is performed in that state. And through holes 60 -1 , 60 -2 , 60
-3 is provided and does not overlap the tip bump contact portion of the conductor terminal 4 or 41, the reliability of the electrical connection of the bump is
Higher than with adhesive film 56 -1 or 58 or 59.

【0081】図15(ニ) において、接着剤フィルム61は透
孔61-1と61-2とを形成してなり、下面に貼着された保護
膜を剥離したのち、上面に貼着した保護膜を剥離した接
着剤フィルム61の透孔61-1, 61-2内には、導体端子4お
よび41の先端のバンプ当接部が露呈するようになる。
[0081] In FIG. 15 (d), the adhesive film 61 is made by forming a through hole 61 -1 and 61 -2, then peeling the protective film adhered to the lower surface, protection adhered to the upper surface The bump contact portions at the tips of the conductor terminals 4 and 41 are exposed in the through holes 61 -1 , 61 -2 of the adhesive film 61 from which the film has been peeled off.

【0082】かかる接着剤フィルム61は、前記接着剤フ
ィルム56-1および58および59および60と同様に半導体チ
ップ1の実装に利用、即ち、接着剤フィルム61の上に載
せた半導体チップ1をガラス基板3に向けて押圧し、そ
の状態で硬化処理するようになる。そして、接着剤フィ
ルム60の透孔60-1, 60-2, 60-3と同様な透孔61-1と61 -2
を設けたことによって、バンプの電気的接続に対する信
頼性が向上する。
The adhesive film 61 is made of the adhesive film described above.
Film 56-1And semiconductor chips as well as 58 and 59 and 60.
It is used for mounting the chip, that is, mounted on the adhesive film 61.
The semiconductor chip 1 is pressed toward the glass substrate 3,
In this state, the curing process is started. And the adhesive fi
Rum 60 through hole 60-1, 60-2, 60-3Through hole similar to 61-1And 61 -2
By providing the
Reliability is improved.

【0083】ただし、硬化処理した接着剤フィルム61
は、搭載した半導体チップ1の下面の全面に被着する。
そのため、接着剤フィルム61を使用して搭載する半導体
チップ1は、例えばチップ内の素子構成または小形であ
ることによって、接着剤フィルム61の収縮応力によって
特性が変化しないものには好適である。
However, the cured adhesive film 61
Adheres to the entire lower surface of the mounted semiconductor chip 1.
Therefore, the semiconductor chip 1 mounted by using the adhesive film 61 is suitable for those whose characteristics do not change due to the shrinkage stress of the adhesive film 61 due to, for example, the element configuration in the chip or the small size.

【0084】なお、上記実施例では接着剤フィルム60を
ガラス基板3上に先に設置しているが、接着剤フィルム
60を半導体チップ1に先に貼付したのち、その半導体チ
ップ1をガラス基板3に実装することも可能である。そ
の時、当然のことながら接着剤フィルム60は、半導体チ
ップ1より小形のもとする。
Although the adhesive film 60 is first placed on the glass substrate 3 in the above embodiment, the adhesive film 60
It is also possible to first attach 60 to the semiconductor chip 1 and then mount the semiconductor chip 1 on the glass substrate 3. At that time, the adhesive film 60 is naturally smaller than the semiconductor chip 1.

【0085】図16(イ),(ロ),(ハ),(ニ) は、前出の導体端子
4,41に接続させたとき電気的接続を確実にするバンプ2
-9,2-10,2-11,2-12 の斜視図であり、バンプ2-9の上
面 (接続端子接続面) には円錐台状突起19-1が突出し、
バンプ2-10 の上面には角錐台状突起19-2が突出し、バ
ンプ2-11 の上面には十字形突起19-3が突出し、バンプ
-12 の上面にはV字形突起19-4が突出する。
16 (a), (b), (c) and (d) are the conductor terminals described above.
Bump 2 that ensures electrical connection when connected to 4,41
-9, 2 -10, 2 -11 2 -12 is a perspective view of a bump 2 -9 upper surface (the connection terminal connecting surface) frustoconical projection 19 -1 protrudes,
Truncated pyramid projections 19 -2 on the upper surface of the bump 2 -10 protrudes, cross projection 19 -3 on the upper surface of the bump 2 -11 protrudes is V-shaped projection 19 -4 on the upper surface of the bump 2 -12 Project.

【0086】突起19-1,19-2,19-3,19-4は、例えば凹
部18-1,18-2,18-3,18-4と同様なツール、即ち、先端
面には突起19-1,19-2,19-3,19-4に対応する凹部が形
成された押圧ツール (図示せず) により形成する。
The projections 19 -1 , 19 -2 , 19 -3 , 19 -4 are, for example, tools similar to the recesses 18 -1 , 18 -2 , 18 -3 , 18 -4 , that is, projections on the tip surface. It is formed by a pressing tool (not shown) in which concave portions corresponding to 19 -1 , 19 -2 , 19 -3 , 19 -4 are formed.

【0087】かかるバンプ2-9,2-10,2-11,2-12 は、
溝12を形成した前出のバンプ2-1と同様な効果、即ち、
塑性変形し易い突起19-1,19-2,19-3,19-4を設けたこ
とによって、接続相手の導体端子に当接せしめたとき、
電気的接続の信頼性が増大するという効果がある。
The bumps 2 -9 , 2 -10 , 2 -11 , 2 -12 are
The same effect as the above-mentioned bump 2 -1 in which the groove 12 is formed, that is,
By providing the protrusions 19 -1 , 19 -2 , 19 -3 , 19 -4 which are easily plastically deformed, when they are brought into contact with the conductor terminal of the connection partner,
This has the effect of increasing the reliability of the electrical connection.

【0088】[0088]

【発明の効果】以上説明したように本発明方法によれ
ば、接着剤を硬化させた収縮応力を利用する半導体チッ
プの実装方法において、半導体チップに実装歪が発生し
ないようになり、そのことで半導体チップの実装前の特
性が確保されるようにした効果がある。
As described above, according to the method of the present invention, the mounting distortion of the semiconductor chip does not occur in the mounting method of the semiconductor chip which utilizes the shrinkage stress obtained by curing the adhesive. This has the effect of ensuring the characteristics before mounting the semiconductor chip.

【0089】さらに、バンプ表面に凹凸を設けること,
バンプ表面に溝や凹部を設けることで、バンプ先端部の
塑性変形を容易とし,バンプと端子との接触抵抗を低減
せし,半導体チップの固定力の増大を可能とし、電気的
接続用バンプと共にダミーバンプを利用するまたは、バ
ンプと導体端子との間に被着しない接着剤フィルムを使
用することで、電気的接続用バンプと端子との接触抵抗
を低減,安定化せしめた効果がある。
Further, providing bumps on the bump surface,
By providing grooves or recesses on the bump surface, the plastic deformation of the tip of the bump can be facilitated, the contact resistance between the bump and the terminal can be reduced, and the fixing force of the semiconductor chip can be increased. The use of the dummy bumps or the use of an adhesive film that does not adhere between the bumps and the conductor terminals has the effect of reducing and stabilizing the contact resistance between the electrical connection bumps and the terminals.

【図面の簡単な説明】[Brief description of drawings]

【図1】 本発明による半導体装置実装方法の基本構成
の説明図
FIG. 1 is an explanatory diagram of a basic configuration of a semiconductor device mounting method according to the present invention.

【図2】 本発明方法の第1の実施例の説明図FIG. 2 is an explanatory view of the first embodiment of the method of the present invention.

【図3】 本発明方法の第2の実施例の説明図FIG. 3 is an explanatory diagram of a second embodiment of the method of the present invention.

【図4】 本発明方法の第3の実施例の説明図FIG. 4 is an explanatory diagram of a third embodiment of the method of the present invention.

【図5】 本発明方法の第4の実施例の説明図FIG. 5 is an explanatory view of a fourth embodiment of the method of the present invention.

【図6】 本発明方法の第5の実施例の説明図FIG. 6 is an explanatory view of a fifth embodiment of the method of the present invention.

【図7】 本発明方法の第6の実施例の説明図FIG. 7 is an explanatory view of a sixth embodiment of the method of the present invention.

【図8】 本発明方法の第7の実施例の説明図FIG. 8 is an explanatory diagram of a seventh embodiment of the method of the present invention.

【図9】 本発明方法の第8の実施例の説明図FIG. 9 is an explanatory diagram of an eighth embodiment of the method of the present invention.

【図10】 本発明方法の第9の実施例に使用するバンプ
整形ツールの構成例の説明図
FIG. 10 is an explanatory diagram of a configuration example of a bump shaping tool used in a ninth embodiment of the method of the present invention.

【図11】 本発明方法の第9の実施例の説明図FIG. 11 is an explanatory diagram of a ninth embodiment of the method of the present invention.

【図12】 本発明方法の第10の実施例の説明図FIG. 12 is an explanatory diagram of a tenth embodiment of the method of the present invention.

【図13】 本発明方法の第11の実施例の説明図FIG. 13 is an explanatory diagram of an eleventh embodiment of the method of the present invention.

【図14】 本発明方法の第12の実施例の説明図FIG. 14 is an explanatory diagram of a twelfth embodiment of the method of the present invention.

【図15】 本発明方法の第13の実施例の説明図FIG. 15 is an explanatory diagram of a thirteenth embodiment of the method of the present invention.

【図16】 本発明方法の第14の実施例に使用するバンプ
の説明図
FIG. 16 is an explanatory view of a bump used in a fourteenth embodiment of the method of the present invention.

【図17】 COG実装した従来の半導体チップの説明図FIG. 17 is an explanatory diagram of a conventional semiconductor chip mounted with COG.

【図18】 液晶表示パネルにおける従来の半導体チップ
実装方法の説明図
FIG. 18 is an explanatory diagram of a conventional semiconductor chip mounting method for a liquid crystal display panel.

【符号の説明】[Explanation of symbols]

1 半導体チップ(半導体装置) 2,2-1,2-2,2-3,2-4,2-5,2-6,2-7,2-8,2-9,2-10,2-11,
-12 金属バンプ 3 ガラス基板(実装基板) 4,41 導体端子 5-1 接着剤 14 ダミーバンプ 16, 16-1 樹脂体 17 はんだ層 51-1, 56-1,58,59,60,61 接着剤フィルム 57 接着剤フィルムの切り欠き 60-1, 60-2, 60-3, 61-1, 61-2 接着剤フィルムの切り
抜き
1 semiconductor chip (semiconductor device) 2,2 -1 , 2,2 -2 , 2 -3 , 2 -4 , 2 -5 , 2 -6 , 2 -7 , 2 -8 , 2 -9 , 2 -10 , 2 -11 ,
2 -12 metallic bumps 3 glass substrate (mounting substrate) 4, 41 conductive terminal 25-1 adhesive 14 dummy bumps 16, 16 1 resin member 17 solder layer 51 -1, 56 -1, 58, 59, 60, 61 bonded Adhesive film 57 Notch of adhesive film 60 -1 , 60 -2 , 60 -3 , 61 -1 , 61 -2 Cutout of adhesive film

───────────────────────────────────────────────────── フロントページの続き (72)発明者 助田 俊明 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 坂田 敏夫 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 笠原 愼一 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 (72)発明者 松永 朗史 神奈川県川崎市中原区上小田中1015番地 富士通株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Toshiaki Sukeda 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Toshio Sakata 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited ( 72) Inventor Shinichi Kasahara, 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, within Fujitsu Limited (72) Inventor Akira Matsunaga 1015, Uedota, Nakahara-ku, Kawasaki, Kanagawa within Fujitsu Limited

Claims (13)

【特許請求の範囲】[Claims] 【請求項1】 半導体装置(1) とその実装基板(3) の一
方には金属バンプ(2,2-1,2-2,2-3,2-4,2-5,2-6,2-7,
2-8,2-9,2-10,2-11,2-12)を,他方には該バンプを電
気的に接続させる導体端子(4,41)を形成し、該バンプと
導体端子とを接続させたときその接続部の周囲を埋め,
該半導体装置(1) と実装基板(3) との対向間に隙間がで
きる量の接着剤(5-1) を、該バンプまたは該導体端子に
被着し、該バンプを該導体端子に当接せしめて該接着剤
を硬化させることを特徴とする半導体装置の実装方法。
1. The semiconductor device (1) and its mounting substrate (3) are provided on one side with metal bumps (2,2 -1 , 2, -2 , 2 -3 , 2 -4 , 2 -5 , 2 -6 , 2 -7 ,
2 -8 , 2 -9 , 2 -10 , 2 -11 , 2 -12 ), and a conductor terminal (4,41) for electrically connecting the bump is formed on the other side of the bump and the conductor terminal. When you connect, fill the area around the connection,
An amount of adhesive (5 -1 ) that forms a gap between the semiconductor device (1) and the mounting substrate (3) is applied to the bump or the conductor terminal, and the bump is applied to the conductor terminal. A method for mounting a semiconductor device, comprising contacting and curing the adhesive.
【請求項2】 請求項1記載の半導体装置の実装方法に
おいて、前記金属バンプ(2-1,2-5,2-6,2-7,2-8,2-9,2
-10,2-11,2-12)の表面に凹凸を設けることを特徴とす
る半導体装置の実装方法。
2. The method for mounting a semiconductor device according to claim 1, wherein the metal bumps (2 -1 , 2 -5 , 2 -6 , 2 -7 , 2 -8 , 2 -9 , 2
-10 , 2 -11 , 2 -12 ). A method of mounting a semiconductor device, characterized in that unevenness is provided on the surface.
【請求項3】 請求項2記載の半導体装置の実装方法に
おいて、前記金属バンプ(2-1,2-5,2-6,2-7,2-8,2-9,2
-10,2-11,2-12)の表面の凹凸を、該金属バンプのプレ
ス加工により形成することを特徴とする半導体装置の実
装方法。
3. The method for mounting a semiconductor device according to claim 2, wherein the metal bumps (2 -1 , 2 -5 , 2 -6 , 2 -7 , 2 -8 , 2 -9 , 2
-10 , 2 -11 , 2 -12 ). Surface unevenness is formed by pressing the metal bumps.
【請求項4】 請求項3記載の半導体装置の実装方法に
おいて、前記金属バンプ(2-5,2-6,2-7,2-8) の表面の凹
凸の凹部を、該表面の輪郭に掛かることなく形成するこ
とを特徴とする半導体装置の実装方法。
4. The method for mounting a semiconductor device according to claim 3, wherein the concave and convex portions on the surface of the metal bumps (2 −5 , 2 −6 , 2 −7 , 2 −8 ) are formed on the contour of the surface. A method for mounting a semiconductor device, which is characterized by being formed without hanging.
【請求項5】 請求項2記載の半導体装置の実装方法に
おいて、前記金属バンプ(2-1,2-5,2-6,2-7,2-8) の表面
に設けた凹凸の凹部には、該金属バンプを請求項1記載
の導体端子(4,41)に接続させる前に、前記接着剤(5-1)
の一部を被着させることを特徴とする半導体装置の実装
方法。
5. The method for mounting a semiconductor device according to claim 2, wherein the concave and convex portions provided on the surface of the metal bumps (2 -1 , 2 -5 , 2 -6 , 2 -7 , 2 -8 ) are provided. The adhesive (5 -1 ) before connecting the metal bump to the conductor terminal (4, 41) according to claim 1 .
A method for mounting a semiconductor device, characterized in that a part of the above is adhered.
【請求項6】 請求項1記載の半導体装置の実装方法に
おいて、前記金属バンプ(2-3,2-4) が硬化させた樹脂体
(16,16-1) にはんだ層(17)を被覆した構成とし、該樹脂
体が変形するように該バンプを前記導体端子(4,41)に押
圧し、該はんだ層と該導体端子とを接続させることを特
徴とする半導体装置の実装方法。
6. The method for mounting a semiconductor device according to claim 1, wherein the metal bumps (2 −3 , 2 −4 ) are cured.
(16,16 -1 ) with a solder layer (17) coated, the bump is pressed against the conductor terminal (4,41) so that the resin body is deformed, and the solder layer and the conductor terminal A method for mounting a semiconductor device, comprising:
【請求項7】 半導体装置(1) とその実装基板(3) の一
方には金属バンプ(2) を,他方には該バンプを電気的に
接続させる導体端子(4,41)を形成し、該バンプと端子と
を接続させたときその接続部の周囲を埋め,該半導体装
置と実装基板(3) との対向間に隙間ができる形状の接着
剤フィルム (51-1, 56-1,58,59,60,61) を、該実装基板
または該半導体装置に被着し、該バンプを該導体端子に
押圧せしめて該接着剤フィルムを硬化させることを特徴
とする半導体装置の実装方法。
7. The semiconductor device (1) and its mounting substrate (3) are provided with metal bumps (2) on one side and conductor terminals (4, 41) on the other side for electrically connecting the bumps, An adhesive film (51 -1 , 56 -1 , 58) having a shape that fills the periphery of the connection portion when the bump and the terminal are connected and forms a gap between the semiconductor device and the mounting substrate (3) facing each other. , 59, 60, 61) is adhered to the mounting substrate or the semiconductor device, and the bumps are pressed against the conductor terminals to cure the adhesive film.
【請求項8】 請求項7記載の半導体装置の実装方法に
おいて、前記接着剤フィルム (51-1, 56-1) として、前
記導体端子(4,41)の配列に対応しほぼロ字形状のものを
使用することを特徴とする半導体装置の実装方法。
8. The method of mounting a semiconductor device according to claim 7, wherein the adhesive film (51 −1 , 56 −1 ) has a substantially square shape corresponding to the arrangement of the conductor terminals (4, 41). What is claimed is: 1. A semiconductor device mounting method, comprising:
【請求項9】 請求項8記載の半導体装置の実装方法に
おいて、前記ロ字形状の接着剤フィルム (56-1) の少な
くとも1ヶ所には、前記バンプ(2) と端子(4,41)とを接
続せしめた状態における該接着剤フィルムの硬化処理で
塞がれる切り欠き(57)を設けることを特徴とする半導体
装置の実装方法。
9. The method for mounting a semiconductor device according to claim 8, wherein the bump (2) and the terminals (4, 41) are provided at least at one location of the square-shaped adhesive film (56 −1 ). A method for mounting a semiconductor device, comprising: providing a notch (57) that is closed by a curing process of the adhesive film in a state where the above are connected.
【請求項10】 請求項7記載の半導体装置の実装方法
において、前記接着剤フィルム(60,61) には前記金属バ
ンプ(2) を前記導体端子(4,41)との接続部が露呈する切
り抜き (60-1, 60-2, 60-3, 61-1, 61-2) を設けたこと
を特徴とする半導体装置の実装方法。
10. The method of mounting a semiconductor device according to claim 7, wherein the adhesive film (60, 61) exposes the metal bump (2) at a connection portion with the conductor terminal (4, 41). A method for mounting a semiconductor device, wherein cutouts (60 -1 , 60 -2 , 60 -3 , 61 -1 , 61 -2 ) are provided.
【請求項11】 半導体装置(1) とその実装基板(3) の
一方には電気回路的に接続された金属バンプ(2,2-1) と
電気回路的に接続されないダミーバンプ(14)とを,他方
には該金属バンプとダミーバンプとを接続させる導体端
子(4,41)を形成し、該金属バンプおよびダミーバンプを
該導体端子に接続させたとき該ダミーバンプと導体端子
との接続部の周囲を埋め,該半導体装置と実装基板との
対向間に隙間ができる量の接着剤(5-1) を該ダミーバン
プに被着し、該金属バンプとダミーバンプとを該導体端
子に押圧し該接着剤を硬化させることを特徴とする半導
体装置の実装方法。
11. A semiconductor device (1) and one of its mounting substrate (3) are provided with metal bumps (2,2 −1 ) electrically connected in an electric circuit and dummy bumps (14) not electrically connected in a circuit. , On the other side, a conductor terminal (4, 41) for connecting the metal bump and the dummy bump is formed, and when the metal bump and the dummy bump are connected to the conductor terminal, the periphery of the connection portion between the dummy bump and the conductor terminal is formed. The dummy bump is coated with an adhesive (5 -1 ) in an amount such that there is a gap between the semiconductor device and the mounting substrate, and the metal bump and the dummy bump are pressed against the conductor terminals to remove the adhesive. A method for mounting a semiconductor device, which comprises curing.
【請求項12】 請求項11記載の半導体装置の実装方
法において、前記ダミーバンプ(14)を前記金属バンプ
(2,2-1) より硬質かつ低背に形成することを特徴とする
半導体装置の実装方法。
12. The method of mounting a semiconductor device according to claim 11, wherein the dummy bump (14) is replaced with the metal bump.
(2,2 -1 ) A method of mounting a semiconductor device, which is characterized by being formed to be harder and have a lower height.
【請求項13】 半導体装置実装基板(3) の導体端子
(4,41)に接続する金属バンプ(2-5,2-6,2-7,2-8) が形成
された半導体装置において、 表面が該導体端子に当接する該バンプには、該表面の輪
郭を残した凹部 (18-1, 18-2, 18-3, 18-4) が形成され
てなることを特徴とする半導体装置。
13. A conductor terminal of a semiconductor device mounting board (3)
In a semiconductor device in which metal bumps (2 -5 , 2 -6 , 2 -7 , 2 -8 ) connected to (4, 41) are formed, the bumps whose surface abuts the conductor terminal The semiconductor device is characterized in that concave portions (18 -1 , 18 -2 , 18 -3 , 18 -4 ) having the contours of the above are formed.
JP5283794A 1992-12-11 1993-11-15 Packaging semiconductor device and semiconductor device Withdrawn JPH06232205A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5283794A JPH06232205A (en) 1992-12-11 1993-11-15 Packaging semiconductor device and semiconductor device

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP33081992 1992-12-11
JP4-330819 1992-12-11
JP5283794A JPH06232205A (en) 1992-12-11 1993-11-15 Packaging semiconductor device and semiconductor device

Publications (1)

Publication Number Publication Date
JPH06232205A true JPH06232205A (en) 1994-08-19

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JP5283794A Withdrawn JPH06232205A (en) 1992-12-11 1993-11-15 Packaging semiconductor device and semiconductor device

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000026215A (en) * 1998-10-19 2000-05-15 김영환 Bottom lead package of semiconductor and manufacturing method thereof
JP2001175829A (en) * 1999-10-08 2001-06-29 Dainippon Printing Co Ltd Noncontact data carrier and ic chip
JP2007043065A (en) * 2005-06-28 2007-02-15 Fujitsu Ltd Semiconductor device
JP2009212492A (en) * 2008-03-03 2009-09-17 Samsung Electro-Mechanics Co Ltd Method of manufacturing package substrate, and method of manufacturing semiconductor package
JP2012209596A (en) * 2012-07-20 2012-10-25 Mitsumasa Koyanagi Method of manufacturing integrated circuit device having three-dimensional lamination structure
WO2017179152A1 (en) * 2016-04-13 2017-10-19 オリンパス株式会社 Semiconductor device and method for manufacturing semiconductor device

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20000026215A (en) * 1998-10-19 2000-05-15 김영환 Bottom lead package of semiconductor and manufacturing method thereof
JP2001175829A (en) * 1999-10-08 2001-06-29 Dainippon Printing Co Ltd Noncontact data carrier and ic chip
JP2007043065A (en) * 2005-06-28 2007-02-15 Fujitsu Ltd Semiconductor device
JP2009212492A (en) * 2008-03-03 2009-09-17 Samsung Electro-Mechanics Co Ltd Method of manufacturing package substrate, and method of manufacturing semiconductor package
JP2012209596A (en) * 2012-07-20 2012-10-25 Mitsumasa Koyanagi Method of manufacturing integrated circuit device having three-dimensional lamination structure
WO2017179152A1 (en) * 2016-04-13 2017-10-19 オリンパス株式会社 Semiconductor device and method for manufacturing semiconductor device
US10607942B2 (en) 2016-04-13 2020-03-31 Olympus Corporation Semiconductor device and method for manufacturing semiconductor device

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