JP3746719B2 - Flip chip mounting method - Google Patents

Flip chip mounting method Download PDF

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Publication number
JP3746719B2
JP3746719B2 JP2002075863A JP2002075863A JP3746719B2 JP 3746719 B2 JP3746719 B2 JP 3746719B2 JP 2002075863 A JP2002075863 A JP 2002075863A JP 2002075863 A JP2002075863 A JP 2002075863A JP 3746719 B2 JP3746719 B2 JP 3746719B2
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Japan
Prior art keywords
bump
gold
circuit board
chip mounting
semiconductor element
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Expired - Fee Related
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JP2002075863A
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Japanese (ja)
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JP2003273148A (en
JP2003273148A5 (en
Inventor
智之 畠山
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Olympus Corp
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Olympus Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body

Description

【０００１】
【発明の属する技術分野】
本発明は、フリップチップ実装方法に関し、詳しくは、半導体素子と回路基板とを、多段バンプを用いて電気的に接続するフリップチップ実装方法に関するものである。
【０００２】
【従来の技術】
従来、半導体素子を回路基板上に実装するフリップチップ実装方法としては、特開平８−１７８６号公報に開示されたものが知られている。
【０００３】
同公報に開示されたフリップチップ実装方法により得られる実装形態は、図８に示すように、半導体素子を含むパッケージ１０１、そのパッケージ１０１上の電極１０２、はんだバンプ１０３ａ、はんだバンプ１０３ｂ、樹脂１０４、回路基板１０５、回路基板１０５上の電極１０６から構成されている．
【０００４】
このようなフリップチップ実装方法では、パッケージ１０１上の電極１０２上にはんだバンプ１０３ａを接合した後、はんだバンプ１０３ａの上面を除く側面を覆うように樹脂１０４を付着させ硬化する。次に、はんだバンプ１０３ａの上面にはんだバンプ１０３ｂを接合し、多段バンプを形成する。
【０００５】
その後、回路基板１０５上の電極１０６と、はんだバンプ１０３ｂとを接合しフリップチップ実装が完了する。
【０００６】
図８に示す従来例では、はんだバンプ１０３ａの側面を樹脂１０４で覆うことにより、はんだバンプ１０３ａとはんだバンプ１０３ｂとを溶融接合する際に、はんだバンプ１０３ａが表面張力による横方向の膨らみを発生しないため、安定した形状を有する多段バンプを形成可能であるというものである。
【０００７】
【発明が解決しようとする課題】
しかしながら、図８に示す従来例の場合、（１）熱で溶融するはんだバンプであるために、隣接するはんだバンプ間でブリッジする危険性が高く、狭バンプピッチで多段バンプを形成することが困難である。（２）樹脂１０４を付着硬化するための作業時間が必要であり、バンプ形成時間が長くなる。という問題があった。
【０００８】
本発明は、上記事情に鑑みてなされたものであり、狭バンプピッチを有する多段バンプを短時間で形成し、回路基板上に半導体素子を能率よく実装できるフリップチップ実装方法を提供することを目的とする。
【０００９】
【課題を解決するための手段】
請求項１記載の発明は、半導体素子と回路基板とを、バンプを用いて電気的に接続するフリップチップ実装方法において、前記回路基板の電極上に第１の金バンプを形成し、この第１の金バンプよりバンプ径が小さい複数の第２の金バンプを、その間に隙間が生じるようにして前記第１の金バンプ上に形成し、前記半導体素子の電極上に、第３の金バンプを形成し、この第３の金バンプの一部が、前記複数の第２の金バンプの間の隙間に嵌合するようにして接触させ、前記回路基板上に前記半導体素子を実装することを特徴とするものである。
【００１０】
この発明では、半導体素子と回路基板とをバンプを用いて電気的に接続するフリップチップ実装方法において、回路基板の電極上に形成した第１の金バンプ上に、バンプ径が第１の金バンプより小さい複数の第２の金バンプをその間に隙間が生じるように形成し、半導体素子の電極上には第３の金バンプを形成し、この第３の金バンプの一部を前記複数の第２の金バンプの間の隙間に嵌合するようにして接触するものであるから、半導体素子と回路基板の間隔を大きくすることができ、かつ、実装強度を高めることができるとともに、実装時に多少の位置ずれが生じても接触不良になりにくく歩留まりの高いフリップチップ実装品を得ることができる。
【００１１】
請求項２記載の発明は、請求項１に記載のフリップチップ実装方法であって、前記金バンプがボールボンディング法により形成されることを特徴とするものである。
【００１２】
この発明では、請求項１に記載の発明と同様な効果を奏するとともに、金バンプの形成に際して、基部を形成したところでワイヤを切断し、この基部をバンプとして用いるボールボンディング法を採用するので、短時間で多段バンプを形成し、フリップチップ実装能率を向上することが可能である。
【００１９】
【発明の実施の形態】
以下に本発明の実施の形態について詳細に説明する。尚、以下の各実施の形態１乃至４においては、金の３段バンプを用いてフリップチップを実装する例で説明している。
【００２０】
（実施の形態１）
（構成）
図１乃至図３は本発明の実施の形態１を示すものであり、図１は実施の形態１のフリップチップ実装方法により半導体素子が実装された回路基板の断面図、図２は、実施の形態１の３段バンプの形成過程を示す断面図、図３は実施の形態１のフリップチップ実装方法の工程を示す断面図である。
【００２１】
図１に示すように、本実施の形態１により得られる電子機器は、半導体素子１、半導体素子１上の電極２、電極２上に形成された第１の金バンプ３ａ、第２の金バンプ３ｂ、第３の金バンプ３ｃ、回路基板４、回路基板４上の電極５、半導体素子１と回路基板４の間を接着固定した異方性導電接着剤６から構成されている。
【００２２】
（作用）
図２（ａ）に示すように、３段バンプは、まず半導体素子１の電極２上に、ボールボンディング法により金属接合で第１の金バンプ３ａを形成する。このボールボンディング法は、半導体素子１を組み立てる際に用いられるワイヤボンディング装置がペアチップの電極と外部に接続する電極との間にワイヤを形成するのに対して、基部を形成したところでワイヤを切断し、この基部（ボール）をバンプとして用いるものである。
【００２３】
第１の金バンプ３ａの先端には、引きちぎり痕７ａが存在する。ここでは引きちぎり痕７ａをそのままにしているが、場合によっては平面プレート（図示せず）を押し当て先端をレベリングしてもよい。
【００２４】
次に、図２（ｂ）に示すように、第１の金バンプ３ａ上に前記ボールボンディング法で第２の金バンプ３ｂを形成する。さらに、図２（ｃ）に示すように、第２の金バンプ３ｂ上に前記ボールボンデイング法で第３の金バンプ３ｃを形成する。
【００２５】
ここで、図２（ｂ）、（ｃ）における７ｂ及び７ｃは、前記引きちぎり痕７ａと同様に金バンプ形成時に発生する引きちぎり痕である。ここでは、半導体素子１の電極２上に３段バンプを形成したが、回路基板４の電極５上に形成してもよい。
【００２６】
図３（ａ）に示すように、３段バンプが形成された半導体素子を、回路基板４の電極５と相対するように位置合わせした後、異方性導電接着剤６を回路基板４上に塗布する。場合によっては、異方性導電接着剤６を回路基板４に塗布した後、位置合わせしてもよい。
【００２７】
次に、図３（ｂ）に示すように、半導体素子１の上面から熱と圧力を加え、金バンプ３ｃと電極５を接触し、３段バンプを塑性変形させた後、異方性導電接着剤６を硬化収縮させて、金バンプ３ｃと電極５との電気的接続をとる。こうして、フリップチップを実装した回路基板４を製造する。
【００２８】
このように異方性導電接着剤６を塗布するに際して、特に電極５をよける必要もなく金バンプ３ｃと電極５を圧接すれば電気的接続が得られる。
【００２９】
ここでは、３段バンプとしたが形成するバンプの段数を替えることにより半導体素子１と回路基板４との間の距離を調整できる。
【００３０】
なお、異方性導電接着剤６に対して熱を効率的に伝えるために、回路基板４を加熱してもよい。
【００３１】
（効果）
上述したフリップチップ実装方法によれば、バンプを溶融せずに接続しているので、バンプ間のブリッジが発生しない。また、金バンプ３ａ、３ｂ、３ｃを同一形状にしているとともに、半導体素子１か又は回路基板４の一方にのみ金バンプ３ａ、３ｂ、３ｃを形成することにより、バンプ製造工程が簡略で少工程数で済み、加工費を最小にできる利点がある。
【００３２】
（実施の形態２）
（構成）
図４及び図５を参照して、本発明の実施の形態２を説明する。図４は、実施の形態２のフリップチップ実装方法により半導体素子１が実装された回路基板４を示す断面図である。図５は、実施の形態２の３段バンプの形成過程を示す断面図である。
【００３３】
本実施の形態２は、実施の形態１と以下の点で異なる。即ち、図４に示すように、金バンプ３ｄ、金バンプ３ｅ、金バンプ３ｆの順にバンプ径が小さい３段バンプ構成としている。
【００３４】
（作用）
図５（ａ）に示すように、本実施の形態２の３段バンプを形成するには、まず半導体素子１の電極２上に、バンプ径が最大の金バンプ３ｄを形成する。次に、図５（ｂ）に示すように金バンプ３ｄ上にバンプ径の小さい金バンプ３ｅを形成する。さらに、図５（ｃ）に示すように金バンプ３ｅ上にバンプ径が最小の金バンプ３ｆを形成し、３段バンプが完成する。これ以降の工程は実施の形態１の場合と同様である。
【００３５】
（効果） 上述したフリップチップ実装方法によれば、実施の形態１の効果を発揮することに加えて、多段バンプ形成工程において、バンプ形成中心位置が多少ずれてもバンプ構造が不安定にならないのでバンプ倒れが発生しにくく、バンプ形成工程の歩留まりが高くなるという効果を奏する。
【００３６】
（実施の形態３）
（構成）
図６を参照して、本発明の実施の形態３について説明する。図６は、本実施の形態３のフリップチップ実装方法の工程を示す断面図である。
【００３７】
本実施の形態３は、異方性導電接着剤を用いていない点で実施の形態１の場合と異なり、これ以外の工程は実施の形態１と同様である。
【００３８】
（作用）
図６（ａ）に示すように、半導体素子１の電極２上に金バンプ３ａ、３ｂ、の２段ダンプを形成し、一方で回路基板４の電極５上に金バンプ３ｇを形成する。
【００３９】
次に、図６（ｂ）に示すように、２段バンプが形成された半導体素子１を、回路基板４の電極５と相対するように位置合わせした後、半導体素子１の上面から熱と圧力を加え、金バンプ３ｂと金バンプ３ｇを接触させ、金属接合させて金バンプ３ｂと金バンプ３ｇとの電気的接続をとる。こうしてフリップチップを実装した回路基板４を製造する。
【００４０】
尚、金バンプ３ｂと金バンプ３ｇとの接合部の信頼性を向上させるためこれら金バンプ３ｂと金バンプ３ｇとを接続した後に半導体素子１と回路基板４との間に絶縁性接着剤を注入、硬化してもよい。
【００４１】
（効果）
上述した本実施の形態３のフリップチップ実装方法によれば、実施の形態１の場合と同様な効果を発揮することに加えて、金バンプ３ｂと金バンプ３ｇとを接合する金−金接合のフリップッチップ実装方法であるため、金バンプと電極とを接触させる実施の形態１、２の実装方法に比べて、多段バンプを有する回路基板４を製造することが容易であるという利点がある。
【００４２】
（実施の形態４）
（構成）
図７を参照して、本発明の実施の形態４について説明する。図７は、本実施の形態４のフリップチップ実装方法の工程を示す断面図である。
【００４３】
本実施の形態４は、実施の形態３と比べ、回路基板４の電極５に形成した金バンプ３ｈと、この金バンプ３ｈ上に形成した金バンプ３ｉを備え、金バンプ３ｉのバンプ径を金バンプ３ｈよりも小径とした点が異なるものである。
【００４４】
（作用）
図７（ａ）に示すように、半導体素子１の電極２上に金バンプ３ａを形成し、一方で回路基板４の電極５上に金バンプ３ｈを形成する。さらに、金バンプ３ｈ上に複数の小径の金バンプ３ｉを形成する。
【００４５】
次に、図７（ｂ）に示すように、金バンプ３ａが形成された半導体素子１を、回路基板４の電極５と相対するように位置合わせした後、半導体素子１の上面から熱と圧力を加え、金バンプ３ａと小径の金バンプ３ｉとを引きちぎり痕７ａが金バンプ３ｉの間の隙間に嵌合するようにして接触させ、かつ、金属接合させて金バンプ３ａと金バンプ３ｉとの電気的接続をとる。こうしてフリップチップを実装した回路基板４を製造する。
【００４６】
（効果）
本実施の形態４のフリップチップ実装方法によれば、実施の形態１乃至３の場合と同様な効果を発揮することに加え、金バンプ３ａと金バンプ３ｉが嵌合する状態で接触しかつ金属接合するために、接合強度が強い金−金接合の多段バンプを備えた回路基板４を製造できるという効果も奏する。
【００４７】
【発明の効果】
本発明によれば、フリップチップ実装を行う場合に、半導体素子と回路基板の間隔を大きくすることができ、かつ、実装強度を高めることができるとともに、実装時に多少の位置ずれが生じても接触不良になりにくく歩留まりの高いフリップチップ実装品を得ることができるフリップチップ実装方法を提供することができる。
【図面の簡単な説明】
【図１】本発明の実施の形態１のフリップチップ実装方法により半導体素子が実装された回路基板を示す断面図である。
【図２】実施の形態１の３段バンプの形成過程を示す断面図である。
【図３】実施の形態１のフリップチップ実装方法の工程を示す断面図である。
【図４】実施の形態２のフリップチップ実装方法により半導体素子が実装された回路基板を示す断面図である。
【図５】実施の形態２の３段バンプの形成過程を示す断面図である
【図６】実施の形態３のフリップチップ実装方法の工程を示す断面図である．
【図７】実施の形態４のフリップチップ実装方法の工程を示す断面図である。
【図８】従来のフリップチップ実装方法により半導体素子が実装された回路基板を示す断面図である。
【符号の説明】
１ 半導体素子
２ 電極
３ａ 金バンプ
３ｂ 金バンプ
３ｃ 金バンプ
３ｄ 金バンプ
３ｅ 金バンプ
３ｆ 金バンプ
３ｇ 金バンプ
３ｈ 金バンプ
３ｉ 金バンプ
４ 回路基板
５ 電極
６ 異方性導電接着剤
７ａ 引きちぎり痕
７ｂ 引きちぎり痕
７ｃ 引きちぎり痕
７ｄ 引きちぎり痕
７ｅ 引きちぎり痕
７ｆ 引きちぎり痕[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a flip chip mounting method, and more particularly to a flip chip mounting method in which a semiconductor element and a circuit board are electrically connected using multi-stage bumps.
[0002]
[Prior art]
Conventionally, as a flip chip mounting method for mounting a semiconductor element on a circuit board, one disclosed in Japanese Patent Laid-Open No. 8-1786 is known.
[0003]
As shown in FIG. 8, a mounting form obtained by the flip chip mounting method disclosed in the publication includes a package 101 including a semiconductor element, an electrode 102 on the package 101, a solder bump 103a, a solder bump 103b, a resin 104, The circuit board 105 includes an electrode 106 on the circuit board 105.
[0004]
In such a flip-chip mounting method, the solder bump 103a is bonded onto the electrode 102 on the package 101, and then the resin 104 is attached and cured so as to cover the side surface except the upper surface of the solder bump 103a. Next, the solder bump 103b is joined to the upper surface of the solder bump 103a to form a multistage bump.
[0005]
Thereafter, the electrode 106 on the circuit board 105 and the solder bump 103b are joined to complete the flip chip mounting.
[0006]
In the conventional example shown in FIG. 8, when the solder bump 103a and the solder bump 103b are melt-bonded by covering the side surface of the solder bump 103a with the resin 104, the solder bump 103a does not bulge in the lateral direction due to surface tension. Therefore, it is possible to form a multistage bump having a stable shape.
[0007]
[Problems to be solved by the invention]
However, in the case of the conventional example shown in FIG. 8, since (1) the solder bumps are melted by heat, there is a high risk of bridging between adjacent solder bumps, and it is difficult to form multi-stage bumps with a narrow bump pitch. It is. (2) An operation time for adhering and curing the resin 104 is required, and the bump formation time becomes long. There was a problem.
[0008]
The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a flip chip mounting method capable of forming multi-stage bumps having a narrow bump pitch in a short time and efficiently mounting semiconductor elements on a circuit board. And
[0009]
[Means for Solving the Problems]
According to a first aspect of the present invention, in a flip chip mounting method in which a semiconductor element and a circuit board are electrically connected using bumps, a first gold bump is formed on an electrode of the circuit board. A plurality of second gold bumps having a bump diameter smaller than that of the gold bumps are formed on the first gold bumps so that a gap is formed therebetween, and a third gold bump is formed on the electrode of the semiconductor element. Forming and contacting a part of the third gold bump so as to fit into a gap between the plurality of second gold bumps, and mounting the semiconductor element on the circuit board. It is what.
[0010]
According to the present invention, in a flip-chip mounting method in which a semiconductor element and a circuit board are electrically connected using bumps, the bump diameter is the first gold bump on the first gold bump formed on the electrode of the circuit board. A plurality of smaller second gold bumps are formed so as to create a gap between them, a third gold bump is formed on the electrode of the semiconductor element, and a part of the third gold bump is placed on the plurality of second gold bumps. Since the contact is made so as to fit in the gap between the two gold bumps, the distance between the semiconductor element and the circuit board can be increased , the mounting strength can be increased , and a little during mounting. Even if the positional deviation occurs, it is possible to obtain a flip-chip mounted product that does not cause poor contact and has a high yield.
[0011]
A second aspect of the present invention is the flip chip mounting method according to the first aspect, wherein the gold bump is formed by a ball bonding method.
[0012]
According to the present invention, the same effect as that of the invention described in claim 1 can be obtained, and when forming the gold bump, the wire is cut when the base is formed, and the ball bonding method using the base as the bump is adopted. It is possible to form multi-stage bumps in a time and improve flip chip mounting efficiency.
[0019]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail. In the following first to fourth embodiments, an example in which a flip chip is mounted using a gold three-stage bump is described.
[0020]
(Embodiment 1)
(Constitution)
1 to 3 show a first embodiment of the present invention. FIG. 1 is a cross-sectional view of a circuit board on which a semiconductor element is mounted by the flip-chip mounting method of the first embodiment, and FIG. FIG. 3 is a cross-sectional view showing the steps of the flip-chip mounting method according to the first embodiment.
[0021]
As shown in FIG. 1, the electronic device obtained by the first embodiment includes a semiconductor element 1, an electrode 2 on the semiconductor element 1, a first gold bump 3a formed on the electrode 2, and a second gold bump. 3b, the third gold bump 3c, the circuit board 4, the electrode 5 on the circuit board 4, and the anisotropic conductive adhesive 6 that bonds and fixes the semiconductor element 1 and the circuit board 4 together.
[0022]
(Function)
As shown in FIG. 2A, in the three-step bump, first, a first gold bump 3a is formed on the electrode 2 of the semiconductor element 1 by metal bonding by a ball bonding method. In this ball bonding method, the wire bonding apparatus used when assembling the semiconductor element 1 forms a wire between the electrode of the pair chip and the electrode connected to the outside, whereas the wire is cut when the base is formed. The base (ball) is used as a bump.
[0023]
A tear mark 7a is present at the tip of the first gold bump 3a. Here, the tear mark 7a is left as it is, but in some cases, a flat plate (not shown) may be pressed to level the tip.
[0024]
Next, as shown in FIG. 2B, the second gold bump 3b is formed on the first gold bump 3a by the ball bonding method. Further, as shown in FIG. 2C, a third gold bump 3c is formed on the second gold bump 3b by the ball bonding method.
[0025]
Here, 7b and 7c in FIGS. 2 (b) and 2 (c) are tear marks generated at the time of gold bump formation, similar to the tear marks 7a. Here, the three-step bump is formed on the electrode 2 of the semiconductor element 1, but it may be formed on the electrode 5 of the circuit board 4.
[0026]
As shown in FIG. 3A, after the semiconductor element on which the three-step bumps are formed is aligned so as to face the electrode 5 of the circuit board 4, the anisotropic conductive adhesive 6 is placed on the circuit board 4. Apply. In some cases, the anisotropic conductive adhesive 6 may be applied to the circuit board 4 and then aligned.
[0027]
Next, as shown in FIG. 3 (b), heat and pressure are applied from the upper surface of the semiconductor element 1, the gold bump 3c and the electrode 5 are brought into contact, and the three-stage bump is plastically deformed. The agent 6 is cured and contracted to establish electrical connection between the gold bump 3 c and the electrode 5. Thus, the circuit board 4 on which the flip chip is mounted is manufactured.
[0028]
Thus, when applying the anisotropic conductive adhesive 6, it is not particularly necessary to avoid the electrode 5, and electrical connection can be obtained if the gold bump 3 c and the electrode 5 are pressed.
[0029]
Although the three-stage bump is used here, the distance between the semiconductor element 1 and the circuit board 4 can be adjusted by changing the number of bumps to be formed.
[0030]
The circuit board 4 may be heated in order to efficiently transfer heat to the anisotropic conductive adhesive 6.
[0031]
(effect)
According to the flip chip mounting method described above, since the bumps are connected without melting, a bridge between the bumps does not occur. In addition, the gold bumps 3a, 3b, and 3c are formed in the same shape, and the bump manufacturing process is simplified and reduced by forming the gold bumps 3a, 3b, and 3c only on one of the semiconductor element 1 and the circuit board 4. There is an advantage that the processing cost can be minimized.
[0032]
(Embodiment 2)
(Constitution)
A second embodiment of the present invention will be described with reference to FIGS. FIG. 4 is a cross-sectional view showing the circuit board 4 on which the semiconductor element 1 is mounted by the flip chip mounting method of the second embodiment. FIG. 5 is a cross-sectional view showing the formation process of the three-step bump according to the second embodiment.
[0033]
The second embodiment is different from the first embodiment in the following points. That is, as shown in FIG. 4, a three-step bump configuration is employed in which the bump diameter is smaller in the order of the gold bump 3d, the gold bump 3e, and the gold bump 3f.
[0034]
(Function)
As shown in FIG. 5A, in order to form the three-step bump of the second embodiment, first, the gold bump 3d having the largest bump diameter is formed on the electrode 2 of the semiconductor element 1. Next, as shown in FIG. 5B, a gold bump 3e having a small bump diameter is formed on the gold bump 3d. Further, as shown in FIG. 5C, the gold bump 3f having the smallest bump diameter is formed on the gold bump 3e to complete the three-step bump. The subsequent steps are the same as in the first embodiment.
[0035]
(Effect) According to the flip chip mounting method described above, in addition to exhibiting the effects of the first embodiment, the bump structure does not become unstable even if the bump formation center position is slightly shifted in the multi-stage bump formation process. Bump collapse is unlikely to occur, and the yield of the bump forming process is increased.
[0036]
(Embodiment 3)
(Constitution)
A third embodiment of the present invention will be described with reference to FIG. FIG. 6 is a cross-sectional view showing the steps of the flip chip mounting method of the third embodiment.
[0037]
The third embodiment is different from the first embodiment in that an anisotropic conductive adhesive is not used, and the other steps are the same as those in the first embodiment.
[0038]
(Function)
As shown in FIG. 6A, a two-stage dump of gold bumps 3 a and 3 b is formed on the electrode 2 of the semiconductor element 1, while a gold bump 3 g is formed on the electrode 5 of the circuit board 4.
[0039]
Next, as shown in FIG. 6B, the semiconductor element 1 on which the two-step bumps are formed is aligned so as to face the electrode 5 of the circuit board 4, and then heat and pressure are applied from the upper surface of the semiconductor element 1. In addition, the gold bump 3b and the gold bump 3g are brought into contact with each other and metal-bonded to establish electrical connection between the gold bump 3b and the gold bump 3g. Thus, the circuit board 4 on which the flip chip is mounted is manufactured.
[0040]
In order to improve the reliability of the joint between the gold bump 3b and the gold bump 3g, an insulating adhesive is injected between the semiconductor element 1 and the circuit board 4 after the gold bump 3b and the gold bump 3g are connected. It may be cured.
[0041]
(effect)
According to the flip-chip mounting method of the third embodiment described above, in addition to exhibiting the same effect as that of the first embodiment, the gold-gold bonding for bonding the gold bump 3b and the gold bump 3g is performed. Since this is a flip-chip mounting method, there is an advantage that it is easier to manufacture the circuit board 4 having multi-stage bumps than the mounting methods of the first and second embodiments in which the gold bump and the electrode are brought into contact with each other.
[0042]
(Embodiment 4)
(Constitution)
A fourth embodiment of the present invention will be described with reference to FIG. FIG. 7 is a cross-sectional view showing the steps of the flip chip mounting method according to the fourth embodiment.
[0043]
Compared with the third embodiment, the fourth embodiment includes a gold bump 3h formed on the electrode 5 of the circuit board 4 and a gold bump 3i formed on the gold bump 3h. The difference is that the diameter is smaller than that of the bump 3h.
[0044]
(Function)
As shown in FIG. 7A, gold bumps 3 a are formed on the electrodes 2 of the semiconductor element 1, while gold bumps 3 h are formed on the electrodes 5 of the circuit board 4. Further, a plurality of small-diameter gold bumps 3i are formed on the gold bump 3h.
[0045]
Next, as shown in FIG. 7B, the semiconductor element 1 on which the gold bump 3 a is formed is aligned so as to face the electrode 5 of the circuit board 4, and then heat and pressure are applied from the upper surface of the semiconductor element 1. In addition, the gold bump 3a and the small-diameter gold bump 3i are torn and brought into contact with each other so that the trace 7a fits into the gap between the gold bumps 3i. Make electrical connections. Thus, the circuit board 4 on which the flip chip is mounted is manufactured.
[0046]
(effect)
According to the flip chip mounting method of the fourth embodiment, in addition to exhibiting the same effects as those of the first to third embodiments, the gold bump 3a and the gold bump 3i are in contact with each other and are in contact with the metal. In order to join, the effect that the circuit board 4 provided with the multi-step bump | vamp of gold-gold joining with strong joining strength is also show | played.
[0047]
【The invention's effect】
According to the present invention, when flip chip mounting is performed, the distance between the semiconductor element and the circuit board can be increased, and the mounting strength can be increased. It is possible to provide a flip chip mounting method capable of obtaining a flip chip mounting product which is less likely to become defective and has a high yield .
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a circuit board on which a semiconductor element is mounted by a flip chip mounting method according to a first embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a process of forming a three-step bump according to the first embodiment.
FIG. 3 is a cross-sectional view showing a process of the flip chip mounting method of the first embodiment.
4 is a cross-sectional view showing a circuit board on which a semiconductor element is mounted by the flip-chip mounting method of Embodiment 2. FIG.
5 is a cross-sectional view showing a process of forming a three-step bump according to the second embodiment. FIG. 6 is a cross-sectional view showing a process of the flip chip mounting method according to the third embodiment.
7 is a cross-sectional view showing a process of the flip chip mounting method of Embodiment 4. FIG.
FIG. 8 is a cross-sectional view showing a circuit board on which a semiconductor element is mounted by a conventional flip chip mounting method.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Electrode 3a Gold bump 3b Gold bump 3c Gold bump 3d Gold bump 3e Gold bump 3f Gold bump 3g Gold bump 3h Gold bump 3i Gold bump 4 Circuit board 5 Electrode 6 Anisotropic conductive adhesive 7a Tear mark 7b Pull Tear marks 7c tear marks 7d tear marks 7e tear marks 7f tear marks

Claims (2)

半導体素子と回路基板とを、バンプを用いて電気的に接続するフリップチップ実装方法において、
前記回路基板の電極上に第１の金バンプを形成し、
この第１の金バンプよりバンプ径が小さい複数の第２の金バンプを、その間に隙間が生じるようにして前記第１の金バンプ上に形成し、
前記半導体素子の電極上に、第３の金バンプを形成し、
この第３の金バンプの一部が、前記複数の第２の金バンプの間の隙間に嵌合するようにして接触させ、前記回路基板上に前記半導体素子を実装することを特徴とするフリップチップ実装方法。In a flip chip mounting method in which a semiconductor element and a circuit board are electrically connected using bumps,
Forming a first gold bump on the electrode of the circuit board;
A plurality of second gold bumps having a smaller bump diameter than the first gold bumps are formed on the first gold bumps so that gaps are formed therebetween,
Forming a third gold bump on the electrode of the semiconductor element;
Flip characterized in that a part of the third gold bump is brought into contact with a gap between the plurality of second gold bumps and the semiconductor element is mounted on the circuit board. Chip mounting method. 前記金バンプがボールボンディング法により形成されることを特徴とする請求項１に記載のフリップチップ実装方法。The flip chip mounting method according to claim 1, wherein the gold bump is formed by a ball bonding method.
JP2002075863A 2002-03-19 2002-03-19 Flip chip mounting method Expired - Fee Related JP3746719B2 (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354967B2 (en) 2016-09-29 2019-07-16 Samsung Electronics Co., Ltd. Metal pillar in a film-type semiconductor package

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006318974A (en) * 2005-05-10 2006-11-24 Toshiba Components Co Ltd Semiconductor device using bump structure and its manufacturing method
WO2019150825A1 (en) * 2018-02-01 2019-08-08 パナソニックＩｐマネジメント株式会社 Semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10354967B2 (en) 2016-09-29 2019-07-16 Samsung Electronics Co., Ltd. Metal pillar in a film-type semiconductor package
US10867948B2 (en) 2016-09-29 2020-12-15 Samsung Electronics Co., Ltd. Metal pillar in a film-type seconductor package

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