JP2001210676A - Semiconductor device and manufacturing method - Google Patents
Semiconductor device and manufacturing methodInfo
- Publication number
- JP2001210676A JP2001210676A JP2000016492A JP2000016492A JP2001210676A JP 2001210676 A JP2001210676 A JP 2001210676A JP 2000016492 A JP2000016492 A JP 2000016492A JP 2000016492 A JP2000016492 A JP 2000016492A JP 2001210676 A JP2001210676 A JP 2001210676A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- film substrate
- semiconductor device
- manufacturing
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は半導体装置および
その製造方法に関する。The present invention relates to a semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】図５は従来の半導体装置の一例の一部の
断面図を示したものである。この半導体装置は、ＴＡＢ
(tape automated bonding)と呼ばれるもので、フィルム
基板１を備えている。この場合、フィルム基板１は厚さ
７５μｍ〜１５０μｍ程度のポリイミドフィルムからな
っている。フィルム基板１の下面には接着剤２を介して
銅箔をパターニングしてなる配線３が設けられている。
配線３の表面には錫、半田等の低融点金属からなるメッ
キ層（図示せず）が設けられている。配線３の一部は、
フィルム基板１に設けられたデバイスホール４内に突出
され、インナーリード３ａとなっている。2. Description of the Related Art FIG. 5 is a partial sectional view of an example of a conventional semiconductor device. This semiconductor device is TAB
This is called (tape automated bonding) and has a film substrate 1. In this case, the film substrate 1 is made of a polyimide film having a thickness of about 75 μm to 150 μm. On the lower surface of the film substrate 1, a wiring 3 formed by patterning a copper foil via an adhesive 2 is provided.
On the surface of the wiring 3, a plating layer (not shown) made of a low melting point metal such as tin or solder is provided. Part of the wiring 3
It protrudes into a device hole 4 provided in the film substrate 1 and forms an inner lead 3a.
【０００３】そして、半導体チップ５の上面の周辺部に
設けられた金からなるバンプ電極６がフィルム基板１上
に形成された、銅箔表面に錫、半田等の低融点金属がメ
ッキされたインナーリード３ａの下面に共晶合金により
接合されていることにより、フィルム基板１のデバイス
ホール４の部分に半導体チップ５が搭載されている。A bump electrode 6 made of gold is provided on the periphery of the upper surface of the semiconductor chip 5 and is formed on the film substrate 1. An inner surface is formed by plating a copper foil surface with a low melting point metal such as tin or solder. The semiconductor chip 5 is mounted on the device hole 4 of the film substrate 1 by being joined to the lower surface of the lead 3a by a eutectic alloy.
【０００４】ところで、バンプ電極６とインナーリード
３ａとを共晶合金により接合するとき、図示していない
が、半導体チップ５をステージ上に配置し、インナーリ
ード３ａの上側からボンディングツールで直接加熱加圧
する関係から、フィルム基板１にデバイスホール４を設
けている。デバイスホール４を設ける理由は、フィルム
基板１の厚さが７５μｍ〜１５０μｍ程度と比較的厚い
ので、デバイスホール４を設けずに、フィルム基板１の
上側からボンディングツールで加熱加圧すると、バンプ
電極６とインナーリード３ａが接合温度に達する前にフ
ィルム基板１が溶融してしまうからである。When the bump electrode 6 and the inner lead 3a are joined by a eutectic alloy, the semiconductor chip 5 is placed on a stage (not shown), and is directly heated by a bonding tool from above the inner lead 3a. The device hole 4 is provided in the film substrate 1 because of the pressure. The reason for providing the device holes 4 is that the thickness of the film substrate 1 is relatively thick, about 75 μm to 150 μm. This is because the film substrate 1 melts before the inner leads 3a reach the bonding temperature.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、従来の
このような半導体装置では、フィルム基板１のデバイス
ホール４内にインナーリード３ａを突出させているの
で、この突出されたインナーリード３ａが変形して互い
にショートするおそれがあるという問題があった。特
に、最近では、半導体チップ５の高集積化に伴いバンプ
電極６のピッチが微細化し、そのため、インナーリード
３ａの幅およびその間隙が小さくなっているので、該イ
ンナーリード３ａが極めて変形しやすく、この変形に伴
う接合不良や短絡等に対する対応が重要な課題となって
いる。この発明の課題は、フィルム基板に設けられた接
続端子の変形を防止し、半導体チップのバンプ電極との
接合の信頼性を向上することである。However, in such a conventional semiconductor device, since the inner leads 3a protrude into the device holes 4 of the film substrate 1, the protruding inner leads 3a are deformed. There is a problem that they may be short-circuited to each other. In particular, recently, the pitch of the bump electrodes 6 has become finer with the increase in the degree of integration of the semiconductor chip 5, and the width and the gap of the inner leads 3a have been reduced. It is an important task to cope with defective bonding, short circuit, and the like due to the deformation. It is an object of the present invention to prevent deformation of connection terminals provided on a film substrate, and to improve reliability of bonding with a bump electrode of a semiconductor chip.
【０００６】[0006]
【課題を解決するための手段】請求項１に記載の発明
は、半導体チップの一面に設けられた金属からなる複数
のバンプ電極と、前記半導体チップ搭載領域の全体に亘
って前記半導体チップの一面に対応する一面および他面
を有するフィルム基板の、前記一面側に設けられた金属
からなる複数の接続端子とを接合する半導体装置の製造
方法であって、前記半導体チップを加熱した状態で前記
フィルム基板の他面にボンディングツールを接触し、前
記各バンプ電極と前記フィルム基板に設けられた各接続
端子とを加熱加圧して接合し前記フィルム基板に前記半
導体チップを搭載するようにしたものである。この発明
によれば、フィルム基板が半導体チップ搭載領域の全体
に亘って半導体チップの一面に対応する一面および他面
を有するものであっても、ある条件下で、半導体チップ
を加熱した状態でフィルム基板の他面にボンディングツ
ールを直接接触し加熱加圧すると、信頼性の高い接合が
得られ、しかもフィルム基板の半導体チップ搭載領域に
デバイスホールが無いので、フィルム基板に設けられた
接続端子の変形を防止することができる。According to a first aspect of the present invention, there is provided a semiconductor device comprising: a plurality of metal bump electrodes provided on one surface of a semiconductor chip; A method of manufacturing a semiconductor device in which a film substrate having one surface and the other surface corresponding to the above is joined to a plurality of connection terminals made of metal provided on the one surface side, wherein the film is heated while the semiconductor chip is heated. A bonding tool is brought into contact with the other surface of the substrate, and the bump electrodes and the connection terminals provided on the film substrate are joined by heating and pressing to mount the semiconductor chip on the film substrate. . According to the present invention, even if the film substrate has one surface corresponding to one surface of the semiconductor chip and the other surface over the entire semiconductor chip mounting area, the film is heated in a state where the semiconductor chip is heated under a certain condition. If a bonding tool is brought into direct contact with the other surface of the substrate and heated and pressed, highly reliable bonding can be obtained, and since there are no device holes in the semiconductor chip mounting area of the film substrate, deformation of the connection terminals provided on the film substrate Can be prevented.
【０００７】[0007]
【発明の実施の形態】図１はこの発明の第１実施形態に
おける半導体装置の要部の断面図を示したものである。
この半導体装置は、ＣＯＦ(chip on film)と呼ばれるも
ので、フィルム基板１１を備えている。この場合、フィ
ルム基板１１は厚さ１０〜５０μｍ程度のポリイミドフ
ィルムからなっている。フィルム基板１１の下面には厚
さ５〜１０μｍ程度の銅からなる配線１２が設けられて
いる。この場合、配線１２は、フィルム基板１１上に銅
を無電解メッキまたはスパッタ等で数千Å程度に形成し
た上、銅を電解メッキする等して、フィルム基板１１に
接着剤等他の絶縁材を介在することなく直接接合されて
いる。配線１２の表面には錫、半田等の低融点金属のメ
ッキ層（図示せず）が設けられている。配線１２の一端
部は接続端子１２ａとなっている。この場合、フィルム
基板１１の半導体チップ搭載領域にはデバイスホールは
設けられておらず、半導体チップ搭載領域の全体に亘っ
て半導体チップ１３に対向する下面および上面を有して
いる。FIG. 1 is a sectional view showing a main part of a semiconductor device according to a first embodiment of the present invention.
This semiconductor device is called COF (chip on film) and includes a film substrate 11. In this case, the film substrate 11 is made of a polyimide film having a thickness of about 10 to 50 μm. On the lower surface of the film substrate 11, a wiring 12 made of copper having a thickness of about 5 to 10 μm is provided. In this case, the wiring 12 is formed by forming copper on the film substrate 11 by electroless plating or sputtering to a thickness of about several thousand square meters, and then electroplating copper on the film substrate 11 to form another insulating material such as an adhesive. Are directly joined without interposition. On the surface of the wiring 12, a plating layer (not shown) of a low melting point metal such as tin or solder is provided. One end of the wiring 12 is a connection terminal 12a. In this case, no device hole is provided in the semiconductor chip mounting region of the film substrate 11, and the entire surface of the semiconductor chip mounting region has a lower surface and an upper surface facing the semiconductor chip 13.
【０００８】そして、半導体チップ１３の上面の周辺部
に設けられた金からなるバンプ電極１４がフィルム基板
１１の接続端子１２ａの下面に共晶合金により接合され
ていることにより、フィルム基板１の下面側の所定の箇
所に半導体チップ１３が搭載されている。Since the bump electrode 14 made of gold provided on the periphery of the upper surface of the semiconductor chip 13 is joined to the lower surface of the connection terminal 12a of the film substrate 11 by an eutectic alloy, the lower surface of the film substrate 1 The semiconductor chip 13 is mounted at a predetermined position on the side.
【０００９】次に、図１に示す半導体装置の製造方法の
一例について説明する。まず、図２（Ａ）に示すボンデ
ィング装置を用意する。このボンディング装置は、ヒー
ター（図示せず）が内蔵されたステージ２１の上方にボ
ンディングツール２２が上下動可能に配置された構造と
なっている。そして、半導体チップ１３を、バンプ電極
１４を上方に向けて、ステージ２１上に載置する。ま
た、上記した如く、半導体チップ搭載領域の全体に亘っ
て半導体チップ１３に対向する下面および上面をするフ
ィルム基板１１を半導体チップ１３の上方に、その下面
側を、換言すれば、配線１２が形成された面を半導体チ
ップ１３側に向けて配置する。次に、半導体チップ１３
の各バンプ電極１４とフィルム基板１１の各接続端子１
２ａとを位置合わせする。Next, an example of a method for manufacturing the semiconductor device shown in FIG. 1 will be described. First, a bonding apparatus shown in FIG. 2A is prepared. This bonding apparatus has a structure in which a bonding tool 22 is disposed above and below a stage 21 in which a heater (not shown) is built. Then, the semiconductor chip 13 is placed on the stage 21 with the bump electrodes 14 facing upward. Further, as described above, the film substrate 11 having the lower surface and the upper surface facing the semiconductor chip 13 over the entire semiconductor chip mounting area is formed above the semiconductor chip 13, and the lower surface side, in other words, the wiring 12 is formed. The arranged surface is arranged facing the semiconductor chip 13 side. Next, the semiconductor chip 13
Of each bump electrode 14 and each connection terminal 1 of the film substrate 11
2a is aligned.
【００１０】次に、図２（Ｂ）に示すように、例えばス
テージ２１を上昇させて、各バンプ電極１４と各接続端
子１２ａとを接触させ、またボンディングツール２２を
下降させる。この状態で、ステージ２１を３５０℃〜４
５０℃、特に好ましくは４００℃程度に加熱して、半導
体チップ１３を加熱するとともに、ボンディングツール
２２を２５０℃〜３５０℃、特に好ましくは３００℃程
度にして、ボンディングツール２２をフィルム基板の１
１の上面に直接接触させて押圧し、各バンプ電極１４と
フィルム基板１１に設けられた各接続端子１２ａとを１
〜３秒程度加熱加圧する。Next, as shown in FIG. 2B, for example, the stage 21 is raised to bring the bump electrodes 14 into contact with the connection terminals 12a, and the bonding tool 22 is lowered. In this state, the stage 21 is set at 350 ° C to 4 ° C.
The semiconductor chip 13 is heated by heating to 50 ° C., particularly preferably about 400 ° C., and the bonding tool 22 is set to 250 ° C. to 350 ° C., particularly preferably about 300 ° C., and the bonding tool 22
1 and is pressed in direct contact with the upper surface of each of the bump electrodes 14 to connect each of the connection terminals 12a provided on the film substrate 11 to each other.
Heat and press for about 3 seconds.
【００１１】このように、フィルム基板１１を１０〜５
０μｍと薄くし、半導体チップ１３を加熱するとともに
フィルム基板１１の上面にボンディングツール２２を直
接接触し加熱加圧するので、比較的低温の加熱温度でバ
ンプ電極１４と接続端子１２ａとが良好な接合温度に達
し、信頼性の高い接合が得られる。そして、このように
して接合された半導体装置では、フィルム基板１１の半
導体チップ搭載領域にデバイスホールが無いため、フィ
ルム基板１１に直に設けられた接続端子１２ａの変形が
防止され、接続端子１２ａが互いにショートしないよう
にすることができる上、ボンディング前後において、接
続端子１２ａが変形し難いので、半導体チップ１３のバ
ンプ電極１４との短絡等接合の不具合を解消し、また、
生産効率が向上するという効果を奏する。この場合、フ
ィルム基板１１と配線１２とを接着剤を介することなく
接合しているため、ボンディング時に接着剤が溶融し、
接続端子１２ａがずれることがないので、高精度な接合
が可能となっている。In this manner, the film substrate 11 is
Since the semiconductor chip 13 is heated and the bonding tool 22 is brought into direct contact with the upper surface of the film substrate 11 and heated and pressed, the bonding temperature between the bump electrode 14 and the connection terminal 12a is relatively low at a relatively low heating temperature. , And a highly reliable joint can be obtained. In the semiconductor device thus bonded, since there is no device hole in the semiconductor chip mounting area of the film substrate 11, the connection terminals 12a provided directly on the film substrate 11 are prevented from being deformed, and the connection terminals 12a Short-circuiting can be prevented, and the connection terminals 12a are not easily deformed before and after bonding. Therefore, problems such as short-circuiting with the bump electrodes 14 of the semiconductor chip 13 can be solved.
This has the effect of improving production efficiency. In this case, since the film substrate 11 and the wiring 12 are joined without the use of an adhesive, the adhesive melts during bonding,
Since the connection terminals 12a do not shift, highly accurate joining is possible.
【００１２】ところで、図１に示す半導体装置の場合、
フィルム基板１１を平坦状としたまま、半導体チップ１
３を接合しているが、このような場合、配線１２と半導
体チップ１４の上面側のエッジとの間隔が狭く、エッジ
に僅かなバリがあったり、ボンディング時にフィルム基
板１１が変形したりすると、半導体チップ１３の上面側
のエッジがフィルム基板１１の配線１２とショートする
おそれがある。By the way, in the case of the semiconductor device shown in FIG.
With the film substrate 11 kept flat, the semiconductor chip 1
In such a case, when the distance between the wiring 12 and the edge on the upper surface side of the semiconductor chip 14 is small, there is a slight burr on the edge, or when the film substrate 11 is deformed during bonding, The edge on the upper surface side of the semiconductor chip 13 may short-circuit with the wiring 12 of the film substrate 11.
【００１３】そこで、次に、半導体チップ１３の上面側
のエッジがフィルム基板１１の配線１２とショートしな
いようにすることができる、この発明の第２実施形態に
おける半導体装置について、図３を参照して説明する。
図３に示す半導体装置では、接続端子１２ａのバンプ電
極１４に接合された部分の近傍および該近傍に対応する
部分におけるフィルム基板１１が半導体チップ１３の上
面から離間するように変形されている。したがって、半
導体チップ１３の上面側のエッジがフィルム基板１１の
配線１２とショートしないようにすることができる。Therefore, next, a semiconductor device according to a second embodiment of the present invention, which can prevent the edge on the upper surface side of the semiconductor chip 13 from short-circuiting with the wiring 12 of the film substrate 11, will be described with reference to FIG. Will be explained.
In the semiconductor device shown in FIG. 3, the film substrate 11 in the vicinity of the portion of the connection terminal 12a joined to the bump electrode 14 and the portion corresponding to the vicinity is deformed so as to be separated from the upper surface of the semiconductor chip 13. Therefore, it is possible to prevent the edge on the upper surface side of the semiconductor chip 13 from being short-circuited with the wiring 12 of the film substrate 11.
【００１４】次に、図３に示す半導体装置の製造方法の
一例について、図４を参照して説明する。まず、図４
（Ａ）に示すボンディング装置を用意する。このボンデ
ィング装置は、ヒーター（図示せず）が内蔵されたステ
ージ２１の上方にボンディングツール２２が上下動可能
に配置され、ステージ２１の上方においてボンディング
ツール２２の周囲にクランプ２３が配置された構造とな
っている。そして、ステージ２１上に半導体チップ１３
を載置するとともに、フィルム基板１１の半導体チップ
１３が搭載される領域の周囲をクランプ２３に挟持させ
る。この状態では、接続端子１２ａとバンプ電極１４と
の間隔は一例として２００μｍ程度となっている。Next, an example of a method of manufacturing the semiconductor device shown in FIG. 3 will be described with reference to FIG. First, FIG.
A bonding apparatus shown in FIG. This bonding apparatus has a structure in which a bonding tool 22 is disposed above and below a stage 21 in which a heater (not shown) is built, and a clamp 23 is disposed around the bonding tool 22 above the stage 21. Has become. Then, the semiconductor chip 13 is placed on the stage 21.
And the clamp 23 clamps the periphery of the region of the film substrate 11 on which the semiconductor chip 13 is mounted. In this state, the distance between the connection terminal 12a and the bump electrode 14 is about 200 μm as an example.
【００１５】次に、図４（Ｂ）に示すように、ボンディ
ングツール２２を下降させ、ボンディングツール２２の
下面で、接続端子１２ａおよびその内側に対応する部分
におけるフィルム基板１１の上面を押圧する。すると、
接続端子１２ａのバンプ電極１４に接合される部分の近
傍および該近傍に対応する部分におけるフィルム基板１
１が下方に向かって適宜に変形され、この状態におい
て、バンプ電極１４と接続端子１２ａとが接合される。
この場合も、ボンディングツール２２の加熱温度を２５
０〜３５０℃、特に好ましくは３００℃程度とし、ステ
ージ２１の加熱温度をそれよりも高くて３５０〜４５０
℃、特に好ましくは４００℃程度とし、ボンディング時
間を１〜３秒程度とする。かくして、図３に示す半導体
装置が得られる。Next, as shown in FIG. 4B, the bonding tool 22 is lowered, and the lower surface of the bonding tool 22 presses the connection terminals 12a and the upper surface of the film substrate 11 at a portion corresponding to the inside thereof. Then
The film substrate 1 in the vicinity of a portion of the connection terminal 12a joined to the bump electrode 14 and a portion corresponding to the vicinity.
1 is appropriately deformed downward, and in this state, the bump electrode 14 and the connection terminal 12a are joined.
Also in this case, the heating temperature of the bonding tool 22 is set to 25.
0 to 350 ° C., particularly preferably about 300 ° C., and the heating temperature of the stage 21 is higher than 350 to 450 ° C.
° C, particularly preferably about 400 ° C, and the bonding time is about 1 to 3 seconds. Thus, the semiconductor device shown in FIG. 3 is obtained.
【００１６】このように、この製造方法では、フィルム
基板１１の下面に半導体チップ１３を搭載すると同時
に、接続端子１２ａのバンプ電極１４に接合される部分
の近傍および該近傍に対応する部分におけるフィルム基
板１１を半導体チップ１３の上面から離間するように変
形しているので、すなわち、接続端子１２ａを、フィル
ム基板と共１１にバンプ電極１４に接合された部分から
半導体チップ搭載領域の外部に向かって、漸次半導体チ
ップ１３から離間する傾斜領域を有するように成形して
いるので、製造工程数が増加しないようにすることがで
きる。As described above, according to this manufacturing method, the semiconductor chip 13 is mounted on the lower surface of the film substrate 11 and, at the same time, the film substrate in the vicinity of the portion of the connection terminal 12a joined to the bump electrode 14 and the portion corresponding to the vicinity. 11 is deformed so as to be separated from the upper surface of the semiconductor chip 13, that is, the connection terminal 12 a is moved from the portion joined to the bump electrode 14 together with the film substrate 11 to the outside of the semiconductor chip mounting region. Since the mold is formed so as to have an inclined region gradually separated from the semiconductor chip 13, the number of manufacturing steps can be prevented from increasing.
【００１７】次に、図３に示す半導体装置の製造方法の
他の例について説明する。この例では、まず、図２
（Ｂ）に示すように、フィルム基板１１の下面に半導体
チップ１３を搭載する。次に、図４に示すボンディング
装置を用い、フィルム基板１１の半導体チップ１が搭載
された領域の周囲をクランプ２３に挟持させ、ボンディ
ングツール２２を下降させ、接続端子１２ａのバンプ電
極１４に接合された部分の近傍および該近傍に対応する
部分におけるフィルム基板１１を半導体チップ１３の上
面から離間するように変形させる。Next, another example of the method for manufacturing the semiconductor device shown in FIG. 3 will be described. In this example, first, FIG.
As shown in (B), the semiconductor chip 13 is mounted on the lower surface of the film substrate 11. Next, using the bonding apparatus shown in FIG. 4, the periphery of the area of the film substrate 11 on which the semiconductor chip 1 is mounted is clamped by the clamp 23, the bonding tool 22 is lowered, and the film is bonded to the bump electrode 14 of the connection terminal 12a. The film substrate 11 is deformed so as to be separated from the upper surface of the semiconductor chip 13 in the vicinity of and in a portion corresponding to the vicinity.
【００１８】[0018]
【発明の効果】以上説明したように、この発明によれ
ば、フィルム基板が半導体チップ搭載領域の全体に亘っ
て半導体チップの一面に対応する一面および他面を有す
るものであっても、ある条件下で、半導体チップを加熱
した状態でフィルム基板の他面にボンディングツールを
直接接触し加熱加圧すると、信頼性の高い接合が得ら
れ、しかもフィルム基板の半導体チップ搭載領域にデバ
イスホールが無いので、フィルム基板に設けられた接続
端子の変形を防止することができる。。As described above, according to the present invention, even if the film substrate has one surface corresponding to one surface of the semiconductor chip and the other surface over the entire semiconductor chip mounting area, a certain condition can be obtained. When a semiconductor chip is heated and a bonding tool is brought into direct contact with the other surface of the film substrate while heating and pressing, a highly reliable bond can be obtained, and there are no device holes in the semiconductor chip mounting area of the film substrate. In addition, deformation of the connection terminals provided on the film substrate can be prevented. .
【図１】この発明の第１実施形態における半導体装置の
要部の断面図。FIG. 1 is a sectional view of a main part of a semiconductor device according to a first embodiment of the present invention.
【図２】（Ａ）および（Ｂ）は図１に示す半導体装置の
製造方法の一例を説明するために示す断面図。FIGS. 2A and 2B are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device illustrated in FIGS.
【図３】この発明の第２実施形態における半導体装置の
要部の断面図。FIG. 3 is a sectional view of a main part of a semiconductor device according to a second embodiment of the present invention.
【図４】（Ａ）および（Ｂ）は図３に示す半導体装置の
製造方法の一例を説明するために示す断面図。4A and 4B are cross-sectional views illustrating an example of a method for manufacturing the semiconductor device illustrated in FIG. 3;
【図５】従来の半導体装置の一例の一部の断面図。FIG. 5 is a partial cross-sectional view of an example of a conventional semiconductor device.
１１ フィルム基板 １２ａ 接続端子 １３ 半導体チップ １４ バンプ電極 ２１ ステージ ２２ ボンディングツール ２３ クランプ DESCRIPTION OF SYMBOLS 11 Film board 12a Connection terminal 13 Semiconductor chip 14 Bump electrode 21 Stage 22 Bonding tool 23 Clamp
Claims (10)
らなる複数のバンプ電極と、前記半導体チップ搭載領域
の全体に亘って前記半導体チップの一面に対応する一面
および他面を有するフィルム基板の、前記一面側に設け
られた金属からなる複数の接続端子とを接合する半導体
装置の製造方法であって、前記半導体チップを加熱した
状態で前記フィルム基板の他面にボンディングツールを
接触し、前記各バンプ電極と前記フィルム基板に設けら
れた各接続端子とを加熱加圧して接合し前記フィルム基
板に前記半導体チップを搭載することを特徴とする半導
体装置の製造方法。1. A semiconductor device comprising: a plurality of bump electrodes made of metal provided on one surface of a semiconductor chip; and a film substrate having one surface and another surface corresponding to one surface of the semiconductor chip over the entire semiconductor chip mounting area. A method for manufacturing a semiconductor device for bonding a plurality of connection terminals made of metal provided on the one surface side, wherein a bonding tool is brought into contact with the other surface of the film substrate while the semiconductor chip is heated, and A method of manufacturing a semiconductor device, comprising: bonding a bump electrode and each connection terminal provided on the film substrate by heating and pressing to mount the semiconductor chip on the film substrate.
ィルム基板の厚さは１０〜５０μｍであることを特徴と
する半導体装置の製造方法。2. The method according to claim 1, wherein said film substrate has a thickness of 10 to 50 μm.
て、前記ボンディングツールを温度２５０℃〜３５０℃
で加熱することを特徴とする半導体装置の製造方法。3. The bonding tool according to claim 1, wherein the bonding tool is set at a temperature of 250 ° C. to 350 ° C.
A method for manufacturing a semiconductor device.
おいて、前記半導体チップを温度３５０℃〜４５０℃で
加熱することを特徴とする半導体装置の製造方法。4. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip is heated at a temperature of 350 ° C. to 450 ° C.
おいて、前記ボンディングツールによる加熱加圧時に前
記フィルム基板の前記半導体チップが搭載される領域の
周囲を挟持して、前記フィルム基板に前記半導体チップ
を搭載することを特徴とする半導体装置の製造方法。5. The film substrate according to claim 1, wherein a periphery of a region of the film substrate on which the semiconductor chip is mounted is held when the bonding tool is heated and pressed. A method for manufacturing a semiconductor device, comprising mounting the semiconductor chip.
ィルム基板の他面に前記ボンディングツールが接触した
状態で、前記半導体チップの各バンプ電極と前記フィル
ム基板の各接続端子とが離間された位置とし、前記ボン
ディングツールを下降することにより前記フィルム基板
を変形させて前記各バンプ電極と前記フィルム基板に設
けられた各接続端子とを接合することを特徴とする半導
体装置の製造方法。6. The invention according to claim 5, wherein each bump electrode of the semiconductor chip is separated from each connection terminal of the film substrate in a state where the bonding tool is in contact with the other surface of the film substrate. A method of manufacturing the semiconductor device, wherein the bonding tool is lowered, and the film substrate is deformed by lowering the bonding tool to bond the bump electrodes to the connection terminals provided on the film substrate.
続端子は、前記フィルム基板と共に前記バンプ電極に接
合された部分から前記半導体チップ搭載領域の外部に向
かって、漸次前記半導体チップから離間する傾斜領域を
有するように成形されることを特徴とする半導体装置の
製造方法。7. The semiconductor device according to claim 6, wherein the connection terminal is gradually inclined away from the semiconductor chip from a portion joined to the bump electrode together with the film substrate to an outside of the semiconductor chip mounting region. A method for manufacturing a semiconductor device, characterized by being formed to have a region.
導体チップを前記ボンディングツールの加熱温度よりも
高い温度に加熱することを特徴とする半導体装置の製造
方法。8. The method according to claim 1, wherein the semiconductor chip is heated to a temperature higher than a heating temperature of the bonding tool.
た金属からなる複数のバンプ電極と、前記半導体チップ
搭載領域の全体に亘って前記半導体チップの一面に対応
する一面および他面を有する厚さ１０〜５０μｍ程度の
フィルム基板の、前記一面側に設けられた金属からなる
複数の接続端子とを接合する半導体装置の製造方法であ
って、前記フィルム基板の一面に前記半導体チップを搭
載し、前記フィルム基板の前記半導体チップが搭載され
た領域の周囲を挟持して、前記接続端子を、前記フィル
ム基板と共に前記バンプ電極に接合された部分から前記
半導体チップ搭載領域の外部に向かって、漸次前記半導
体チップから離間する傾斜領域を有するように成形する
ことを特徴とする半導体装置の製造方法。9. A plurality of bump electrodes made of metal provided on a peripheral portion of one surface of a semiconductor chip, and a thickness having one surface and another surface corresponding to one surface of the semiconductor chip over the entire semiconductor chip mounting area. A method for manufacturing a semiconductor device in which a film substrate of about 10 to 50 μm is joined to a plurality of connection terminals made of metal provided on the one surface side, wherein the semiconductor chip is mounted on one surface of the film substrate, Sandwiching the periphery of the region of the film substrate on which the semiconductor chip is mounted, and gradually connecting the connection terminals from the portion bonded to the bump electrode together with the film substrate to the outside of the semiconductor chip mounting region. A method for manufacturing a semiconductor device, comprising: forming a semiconductor device having an inclined region separated from a semiconductor chip.
からなる複数のバンプ電極とフィルム基板の前記半導体
チップとの対向面側の一面に設けられた金属からなる複
数の接続端子とが直接接合された半導体装置であって、
前記フィルム基板は前記半導体チップ搭載領域の全体に
亘って前記半導体チップの一面に対応する一面および他
面を有し、前記接続端子は、前記フィルム基板と共に前
記バンプ電極に接合された部分から前記半導体チップ搭
載領域の外部に向かって、漸次前記半導体チップから離
間する傾斜領域を有することを特徴とする半導体装置。10. A plurality of bump electrodes made of metal provided on one surface of a semiconductor chip and a plurality of connection terminals made of metal provided on one surface of the film substrate facing the semiconductor chip. Semiconductor device,
The film substrate has one surface and the other surface corresponding to one surface of the semiconductor chip over the entire semiconductor chip mounting area, and the connection terminal is connected to the semiconductor substrate from a portion bonded to the bump electrode together with the film substrate. A semiconductor device having an inclined region that is gradually separated from the semiconductor chip toward the outside of the chip mounting region.
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000016492A JP3456576B2 (en) | 2000-01-26 | 2000-01-26 | Semiconductor device and manufacturing method thereof |
| US09/766,269 US6433414B2 (en) | 2000-01-26 | 2001-01-19 | Method of manufacturing flexible wiring board |
| TW090101519A TW486922B (en) | 2000-01-26 | 2001-01-20 | Flexible wiring board, method of manufacturing flexible wiring board and display device equipped with flexible wiring board |
| KR10-2001-0003501A KR100401224B1 (en) | 2000-01-26 | 2001-01-22 | Method of manufacturing flexible wiring board |
| CNB011023139A CN1227956C (en) | 2000-01-26 | 2001-01-31 | Flexible wiring board and making method thereof and display device with flexible wiring board |
| HK02102541A HK1040879A1 (en) | 2000-01-26 | 2002-04-04 | Flexible wiring board, method of manufacturing flexible wiring board and display device equipped with flexible wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000016492A JP3456576B2 (en) | 2000-01-26 | 2000-01-26 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2001210676A true JP2001210676A (en) | 2001-08-03 |
| JP3456576B2 JP3456576B2 (en) | 2003-10-14 |
Family
ID=18543620
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000016492A Ceased JP3456576B2 (en) | 2000-01-26 | 2000-01-26 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3456576B2 (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7173322B2 (en) | 2002-03-13 | 2007-02-06 | Mitsui Mining & Smelting Co., Ltd. | COF flexible printed wiring board and method of producing the wiring board |
| US7255919B2 (en) | 2002-03-13 | 2007-08-14 | Mitsui Mining & Smelting Co., Ltd. | Mold release layer transferring film and laminate film |
| JP2007214601A (en) * | 2007-05-25 | 2007-08-23 | Seiko Epson Corp | Method for fabricating semiconductor device, and method for fabricating circuit board |
| JP2008053761A (en) * | 2002-03-13 | 2008-03-06 | Mitsui Mining & Smelting Co Ltd | Semiconductor device, and its manufacturing method |
| US7755183B2 (en) | 2004-09-14 | 2010-07-13 | Casio Micronics Co., Ltd. | Wiring board, method of manufacturing the same, and semiconductor device |
-
2000
- 2000-01-26 JP JP2000016492A patent/JP3456576B2/en not_active Ceased
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7173322B2 (en) | 2002-03-13 | 2007-02-06 | Mitsui Mining & Smelting Co., Ltd. | COF flexible printed wiring board and method of producing the wiring board |
| US7198989B2 (en) | 2002-03-13 | 2007-04-03 | Mitsui Mining & Smelting Co., Ltd. | Method of producing a COF flexible printed wiring board |
| US7255919B2 (en) | 2002-03-13 | 2007-08-14 | Mitsui Mining & Smelting Co., Ltd. | Mold release layer transferring film and laminate film |
| JP2008053761A (en) * | 2002-03-13 | 2008-03-06 | Mitsui Mining & Smelting Co Ltd | Semiconductor device, and its manufacturing method |
| US7755183B2 (en) | 2004-09-14 | 2010-07-13 | Casio Micronics Co., Ltd. | Wiring board, method of manufacturing the same, and semiconductor device |
| JP2007214601A (en) * | 2007-05-25 | 2007-08-23 | Seiko Epson Corp | Method for fabricating semiconductor device, and method for fabricating circuit board |
| JP4572348B2 (en) * | 2007-05-25 | 2010-11-04 | セイコーエプソン株式会社 | Semiconductor device manufacturing method and circuit board manufacturing method |
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| Publication number | Publication date |
|---|---|
| JP3456576B2 (en) | 2003-10-14 |
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