JP3947436B2 - Semiconductor device - Google Patents

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JP3947436B2
JP3947436B2 JP2002202070A JP2002202070A JP3947436B2 JP 3947436 B2 JP3947436 B2 JP 3947436B2 JP 2002202070 A JP2002202070 A JP 2002202070A JP 2002202070 A JP2002202070 A JP 2002202070A JP 3947436 B2 JP3947436 B2 JP 3947436B2
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semiconductor chip
wiring
bump
semiconductor
semiconductor device
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JP2003092307A (en
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和孝 柴田
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Rohm Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01024—Chromium [Cr]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01078—Platinum [Pt]
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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Description

【０００１】
【発明の属する技術分野】
本発明は、半導体チップとその半導体チップの周囲に設けられる電極パッドを半導体チップの面積内に分散させる絶縁性基板とが接続された半導体装置に関する。さらに詳しくは、半導体チップの温度をあまり上げないで、また、強い圧力で押し付けなくても、しかも隣接する電極パッド同士をショートさせないで確実に接続することができる構造の半導体装置に関する。
【０００２】
【従来の技術】
従来、ＩＣやＬＳＩのような半導体チップは、半導体層内に回路素子を回路が形成されるように形成し、外部回路と接続用の電極端子を半導体チップ周囲に電極パッドとして引き出し、ワイヤボンディングなどにより外部リードと接続できるようにすることにより形成されている。最近では、電子部品の小形化、組立の省力化などの点からワイヤボンディングを使用しないで、電極パッドにバンプを形成し、バンプを直接相手の端子またはリードなどと接続する構造が採られてきている。しかし、半導体チップの高集積化、複雑化に伴い、電極パッドの数が非常に増え、その間隙も非常に狭くなってきており、直接バンプや接着剤などにより接続しようとすると、隣接する電極パッド同士がショートしたり、接着時の温度上昇や圧力などにより、半導体チップに形成された素子に悪影響を及ぼすという問題がある。
【０００３】
一方、半導体チップを実装する場合、半導体チップの電極パッドが形成された外周部より中心側は空き空間になっている。そのため、その空き空間を有効に利用すべく、図３に示されるように、ポリイミドなどからなる絶縁性フィルム（基板）２の一方の面に半導体チップ１の電極パッド１１上のバンプ１２と位置合せした配線２１を形成し、絶縁性フィルム２の他方の面にその配線２１と接続して面内の全体に分散してハンダボール２２を形成するチップサイズパッケージ（ＣＳＰ）と呼ばれる半導体装置が実用化されてきている。
【０００４】
この半導体チップ１と絶縁性フィルム２との接続は、たとえば異方導電性接着剤（ＡＣＦ）８を絶縁性フィルム２の配線２１上に塗布し、半導体チップ１を押し付けることにより、バンプ１２により出っ張っている部分では、異方導電性樹脂８が横側に押し出され、バンプ１２部分では、配線２１との間に導電性粒子８１を挟み込み、導電性粒子８１を介して、バンプ１２と配線２１とを電気的に接続する。一方、横方向に関しては、導電性粒子８１と接着剤とが混ざった状態であるため、導電性は遮断され接続しない。そのため、狭い間隔の電極端子でも、隣接する電極端子同士をショートさせることなく、対向する配線との間のみで接続することができる。
【０００５】
【発明が解決しようとする課題】
前述のような半導体チップと絶縁性フィルムとを接続するＣＳＰタイプの半導体装置では、両者の接続が異方導電性接着剤により接着することにより行われれている。しかし、異方導電性接着剤による接着では、接着時に１バンプ当り２０〜５０ｇ程度の圧力で圧接しながら、２０秒程度の長時間加熱しなければならない。両者の接着時にこのような圧力を長時間印加すると、生産性が低下すると共に、電極パッド下の半導体層に直接その圧力が加わり、その半導体層に形成された回路素子（半導体素子）に異常を来すという問題もある。そのため、その電極パッドの下や周辺には素子を形成することができず、軽薄短小化で、高集積化される半導体チップという要請に応えられないという問題がある。
【０００６】
本発明はこのような状況に鑑みてなされたもので、ＣＳＰタイプの半導体装置において、半導体チップと絶縁性基板との接続時に、長時間大きな圧力を印加することなく接続することにより、生産性が向上し、かつ、電極パッドの下やその近傍まで回路素子を形成することができ、高集積化し得る構造の半導体装置を提供することを目的とする。
【０００７】
【課題を解決するための手段】
本発明による半導体装置は、回路素子が形成され周囲に外部と接続用の電極パッドが形成される半導体チップと、一面側に、前記半導体チップの電極パッドと接続される部分に一端部を有し、他端部が中央部側に導かれる配線が形成され、他面側に、該配線の他端部と接続して外部接続端子が形成される絶縁性基板とからなり、前記半導体チップの電極パッド上にＡｕからなるバンプが形成され、前記配線がＣｕ膜と表面に形成されるＡｕ膜とからなり、前記バンプの表面または前記配線の接続部のみにスポット的に設けられる０ . ５〜３μｍ厚のＳｎ被膜により、前記バンプと前記絶縁性基板の配線の一端部とが、Ａｕ-Ｓｎ合金層を介して接合されると共に、該接合される部分の面積の半分以上はＡｕが６５ｗｔ％以上のＡｕ - Ｓｎ合金層となるよう接合され、前記絶縁性基板の前記半導体チップが設けられた側のほぼ全面に、前記半導体チップを完全に被覆するように樹脂が設けられることによりパッケージが形成されている。
【０００８】
ここに回路素子とは、トランジスタ、ダイオード、キャパシタなどの半導体層や層間絶縁膜の間などに形成される集積回路を構成する半導体素子などの素子を意味する。また、絶縁性基板とは、撓みにくいハードな基板の他、ポリイミドなどの可撓性フィルムも含む意味である。
【０００９】
この構造にすることにより、半導体チップと絶縁性基板との接続が２８０〜３００℃程度の温度に上昇するだけで、Ｓｎが溶融しＡｕが拡散するため、Ａｕ-Ｓｎ共晶合金が形成され、１秒程度、すなわち従来のＡＣＦを用いる場合の１／２０程度の時間で融着することができる。その結果、生産性が非常に向上すると共に、回路素子に影響を及ぼすような高い圧力を長時間印加する必要がなく、圧力による回路素子への悪影響は生じない。しかも接合部以外の配線などは、融点の高いＡｕなどからなっているため、実装時のハンダ付け温度などでは全く支障を来すこともない。
【００１３】
【発明の実施の形態】
つぎに、図面を参照しながら本発明の半導体装置について説明をする。本発明による半導体装置は、図１にその一実施形態である断面説明図が示されるように、半導体チップ１に、回路素子（半導体素子）が形成され、表面の周囲に外部と接続用の電極パッドが形成されている。一方、絶縁性基板２の一面側に配線２１が形成され、他面側に配線２１と接続してハンダボールなどの外部接続端子２２が形成されている。この半導体チップ１の電極パッド１１と配線２１との接続部が、Ａｕ-Ｓｎ合金層３により接合されていることに特徴がある。
【００１４】
図１に示される例では、半導体チップ１の外部と接続する電極パッド１１の表面にバンプ１２がメッキなどにより１０〜３０μｍ程度の厚さに形成されている。バンプ１２自身は、従来と同様に形成され、たとえば図１（ｂ）に接合前の接合部の部分拡大図が示されるように、Ａｌなどからなる電極端子１１上に、中間金属層１４が２層または３層構造で形成され、中間金属層１４の第１層にはＴｉまたはＣｒが、第２層にはＷ、Ｐｔ、Ａｇ、Ｃｕ、Ｎｉなどが、第３層にはＡｕなどが用いられる。そして、その上にバンプ１２が、Ａｕ、Ｃｕなどにより形成される。中間金属層１４は、バンプ１２の下地とするもので、この例に限らず、第１層をＴｉ-Ｗ合金層などで構成し、第２層にＡｕ層などを用いることができる。なお、第３層または第２層のＡｕ層は、その上に設けられるＡｕバンプとの密着性を向上させるためのもので、Ａｕバンプが設けられた後では、Ａｕ層が単独で残存するものではない。１７は絶縁膜である。この回路素子（半導体素子）や半導体基板の表面に形成される配線、電極パッド、絶縁膜などは、通常の半導体装置の製造工程と同様に形成される。
【００１５】
絶縁性基板２は、たとえばポリイミドフィルムなどの可撓性フィルムからなっているが、ポリイミドフィルムでなくても、ガラスエポキシなどからなるプリント基板やセラミック基板などの誘電体基板でもよい。半導体装置の小形化の点からも絶縁性基板２はできるだけ薄い方が好ましい。この絶縁性基板２の表面（一方の面）には、通常のフィルム基板やプリント基板と同様に、基板表面に蒸着などにより全面に設けられたＣｕ膜などをパターニングし、さらにＡｕなどを電解メッキなどにより設けることにより、Ｃｕ膜２１ａおよびＡｕ膜２１ｂからなる配線２１が形成されている。配線２１の一端部は、半導体チップ１の電極パッド１１（バンプ１２）と接続するように形成され、他端部は絶縁性基板２の中央部側に導かれ、絶縁性基板２のスルーホールを介して絶縁性基板２の裏面に形成されている外部接続端子２２に接続されている。
【００１６】
配線２１のバンプ１２との接続部には、図１（ｂ）に拡大図が示されるように、さらに無電解メッキまたはスパッタリングなどによりＳｎ被膜３ａが０.５〜３μｍ程度の厚さに設けられている。このＳｎ被膜３ａは、バンプ１２との接続部のみに設けられる。Ｓｎ被膜３ａが、配線２１の接続部のみにスポット的に設けられることにより、金属拡散を制御することができるため好ましい。一方、接合部にＳｎ被膜３ａが設けられることにより、Ａｕの融点は、１０６４℃程度（Ａｕバンプ同士の接合の場合、同一金属同士であるため、加圧しながら加熱することにより、４５０℃程度で融着する）であるのに対して、Ｓｎの融点は、２３２℃程度であり、２３０℃程度になると溶融し、Ａｕと共晶を形成して合金化し、２８０℃程度でＡｕ-Ｓｎ合金からなる合金層３がその接合面に形成されて、バンプ１２と配線２１とが溶着する。すなわち、半導体基板に形成される回路素子などに対しては支障のない低い温度でバンプ１２と配線２１とを融着させることができる。
【００１７】
合金層３は、ＡｕとＳｎとの合金化により形成され、完全な共晶合金になっておれば、Ａｕ８０ｗｔ％、Ｓｎ２０ｗｔ％となるが、接合部全体が共晶合金になっていなくても、また、均一な合金層になっていなくてもよい。本発明者の鋭意検討の結果、Ａｕが６５ｗｔ％以上の合金層が接合部（接合面積）の半分以上あれば接合力に問題はなかった。
【００１８】
この半導体チップ１と絶縁性基板２との接続は、たとえば絶縁性基板２を加熱し得る基板ステージ上に載置し、マウンターにより半導体チップ１をそのバンプ１２と配線２１の一端部に設けられているＳｎ被膜３ａとが一致するように位置合せをして、加圧しながら３００℃程度に加熱することにより、Ｓｎ被膜３ａが溶融し、バンプ１２のＡｕと共晶を形成し、合金層３を形成する。この合金層３は３００℃程度で溶融状態にあるため、バンプ１２と配線２１の一端部とは合金層３の溶融状態で接触しており、加熱を解除することにより、固化して接着する。
【００１９】
半導体チップ１と絶縁性基板２との隙間には、エポキシ樹脂またはエラストマーなどからなる絶縁性樹脂７が充填され、しっかりと固着される。このままでも半導体装置として利用され得るが、図２に示されるように、通常の半導体装置の製造と同様に、絶縁性基板２の半導体チップ１側をエポキシ樹脂などによりモールドしてパッケージ４を形成することもできる。この形状にすることにより、通常の半導体装置と同様の形状で、プリント基板などとの接続部は半導体装置の裏面全面に分散された外部接続端子２２により直接回路基板などに、ハンダ付けにより実装することができる半導体装置が得られる。なお、図２において、図１と同じ部分には同じ符号を付してその説明を省略する。
【００２０】
本発明の半導体装置によれば、半導体チップのバンプと絶縁性基板の配線との接続が、Ａｕ-Ｓｎ合金層により接着されているため、Ａｕなどの融点の高い金属材料によりバンプを形成しながら、２８０〜３００℃程度の低い温度で、しかも１秒程度と従来のＡＣＦを用いる場合の１／２０程度の短時間で接合することができる。その結果、非常に生産性が向上すると共に、合金化により接合しているため、半導体装置を回路基板などにハンダ付けする場合などに２６０℃程度に温度が上昇しても、合金層が溶けて接着部が剥れることはない。しかも３００℃程度の低温度で短時間に接着されるため、半導体基板に形成される半導体素子（回路素子）に機械的または熱的ストレスが加わることはなく、素子特性に変動を来すことは全くない。そのため、非常に信頼性の高い半導体装置が得られる。
【００２１】
一方、半導体チップのバンプおよび配線の接合部以外の部分には、Ａｕ層がそのまま残存したり、合金化してもＳｎの割合が小さく、３００℃程度に温度を上昇させて外力を加えることにより、バンプや配線の機械的強度を充分に維持しながら、接合部のみが溶融して容易に剥離することができる。すなわち、ハンダリフローの温度では、溶融する部分があっても非常に薄い層であり、外力が加わらないため分離しないが、半導体チップを取り替えたい場合などには、３００℃程度に温度を上昇させて外力を加えることにより、容易に分離することができ、半導体チップを取り替えることができる。
【００２２】
図１に示される例は、配線２１の接続部にＳｎ被膜３ａが設けられていたが、このＳｎ被膜３ａは、半導体チップ１のバンプ１２の表面に形成されていてもよい。また、Ｓｎ被膜が設けられないで、直接Ａｕ-Ｓｎ合金層がいずれかに設けられ、その合金層を利用して接合してもよい。この場合、バンプや配線の表面にＡｕ層がなく、Ｃｕ層のままでもＡｕ-Ｓｎ合金が、Ｃｕ層などに拡散して金属間結合により接合することができる。さらに、半導体チップには、バンプ１２が形成されないで、電極パッド１１の表面にＡｕメッキなどを施して、直接配線２１などと接合する構造にしてもよい。要は、その接合部をＡｕ-Ｓｎ合金で接合することにより、低い温度で接合しながら、半導体装置の実装時などのハンダリフロー温度などに対しても強力な接合を得ることができる。
【００２３】
前述の各例では、１個の絶縁性基板に１個の半導体チップをボンディングするだけの構造の半導体装置であったが、２個以上の複数個の半導体チップを１個の絶縁性基板上にボンディングする場合でも同様である。
【００２４】
【発明の効果】
以上説明したように、本発明によれば、ＣＳＰタイプの半導体装置における、半導体チップと絶縁性基板（フィルム基板）とを接合する際に、非常に短時間で接合することができるため、生産性が大幅に向上すると共に、圧力を加える必要がないため、半導体チップに形成される回路素子に影響を及ぼす虞れはなく、回路素子の信頼性を非常に向上させることができる。さらに、電極パッドの下またはその近傍まで、回路素子を形成することができ、高集積化に寄与する。
【００２５】
また、３００℃以下で分離しやすい金属層を介して接合されているため、半導体チップを取り替える場合に、温度を上げすぎて半導体チップにダメージを与えることなく、非常に簡単に取替を行うことができる。しかも、接合後の実装時などにおけるハンダリフローなどによっては、全く分離することがなく、半導体チップおよびその接合の信頼性が非常に向上する。
【図面の簡単な説明】
【図１】本発明による半導体装置の一実施形態を示す断面説明図および接合前の両者の部分拡大説明図である。
【図２】図１に示される半導体装置にパッケージを形成した例の断面説明図である。
【図３】従来のＣＳＰタイプの半導体装置を示す断面説明図である。
【符号の説明】
１ 半導体チップ
２ 絶縁性基板
３ Ａｕ-Ｓｎ合金層
３ａ Ｓｎ被膜
１１ 電極パッド
１２ バンプ
２１ 配線
２２ 外部接続端子[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device in which a semiconductor chip and an insulating substrate that disperses electrode pads provided around the semiconductor chip within the area of the semiconductor chip are connected. More specifically, the present invention relates to a semiconductor device having a structure capable of reliably connecting adjacent electrode pads without short-circuiting without raising the temperature of the semiconductor chip so much and without pressing with a strong pressure.
[0002]
[Prior art]
Conventionally, a semiconductor chip such as an IC or LSI is formed so that a circuit element is formed in a semiconductor layer, and an electrode terminal for connection to an external circuit is drawn out as an electrode pad around the semiconductor chip, and wire bonding, etc. It is formed by enabling connection with an external lead. Recently, from the viewpoint of miniaturization of electronic parts and labor saving of assembly, a structure has been adopted in which bumps are formed on electrode pads and bumps are directly connected to counterpart terminals or leads without using wire bonding. Yes. However, as the integration and complexity of semiconductor chips increase, the number of electrode pads has increased greatly, and the gaps between them have become very narrow. There is a problem that the elements formed on the semiconductor chip are adversely affected due to short-circuiting or temperature rise or pressure during bonding.
[0003]
On the other hand, when a semiconductor chip is mounted, the center side is an empty space from the outer peripheral portion where the electrode pads of the semiconductor chip are formed. Therefore, in order to make effective use of the empty space, as shown in FIG. 3, the bump 12 on the electrode pad 11 of the semiconductor chip 1 is aligned with one surface of an insulating film (substrate) 2 made of polyimide or the like. A semiconductor device called a chip size package (CSP) in which a solder ball 22 is formed by connecting the wiring 21 to the other surface of the insulating film 2 to form the solder balls 22 is formed on the other surface of the insulating film 2. Has been.
[0004]
The semiconductor chip 1 and the insulating film 2 are connected to each other by, for example, applying anisotropic conductive adhesive (ACF) 8 on the wiring 21 of the insulating film 2 and pressing the semiconductor chip 1 so that the bumps 12 protrude. The anisotropic conductive resin 8 is pushed out to the lateral side in the portion where the bump 12 is located, and the conductive particles 81 are sandwiched between the bumps 12 and the wiring 21. Are electrically connected. On the other hand, since the conductive particles 81 and the adhesive are mixed in the lateral direction, the conductivity is blocked and the connection is not established. For this reason, even electrode terminals with a narrow interval can be connected only to the opposing wirings without shorting adjacent electrode terminals.
[0005]
[Problems to be solved by the invention]
In the CSP type semiconductor device that connects the semiconductor chip and the insulating film as described above, the connection between the two is performed by bonding with an anisotropic conductive adhesive. However, in bonding with an anisotropic conductive adhesive, it is necessary to heat for a long time of about 20 seconds while being pressed with a pressure of about 20 to 50 g per bump during bonding. If such a pressure is applied for a long time at the time of bonding between the two, the productivity is lowered and the pressure is directly applied to the semiconductor layer under the electrode pad, causing an abnormality in the circuit element (semiconductor element) formed in the semiconductor layer. There is also a problem of coming. Therefore, there is a problem that an element cannot be formed under or around the electrode pad, and it is difficult to meet the demand for a highly integrated semiconductor chip that is light and thin.
[0006]
The present invention has been made in view of such a situation, and in a CSP type semiconductor device, when a semiconductor chip and an insulating substrate are connected without connecting a large pressure for a long time, productivity is improved. An object of the present invention is to provide a semiconductor device having an improved structure, in which circuit elements can be formed under and near electrode pads, and can be highly integrated.
[0007]
[Means for Solving the Problems]
The semiconductor device according to the present invention has a semiconductor chip in which circuit elements are formed and electrode pads for connection to the outside are formed around the semiconductor chip, and one end portion is provided on one surface side of the semiconductor chip. The other end is formed with a wiring that is led to the center side, and the other surface is connected to the other end of the wiring and is formed with an insulating substrate on which an external connection terminal is formed. 0 bump made of Au is formed on the pad, the wiring consists of a Au film formed on Cu film and the surface, is provided so spot only to the connection portion of the surface or the wiring of the bump. 5～3Myuemu the thickness of the Sn coating, one end portion of the wiring of the bumps and the insulating substrate are bonded via the Au-Sn alloy layer Rutotomoni, more than half of the area of the portion engaged該接is Au or more 65 wt% of Au - Sn alloy layer So as joined, the almost entire surface of the semiconductor chip of the insulating substrate is provided side package by resin is provided so as to completely cover said semiconductor chip is formed.
[0008]
Here, the circuit element means an element such as a semiconductor element constituting an integrated circuit formed between a semiconductor layer such as a transistor, a diode, or a capacitor, or an interlayer insulating film. Moreover, an insulating board | substrate is a meaning also including flexible films, such as a polyimide, besides the hard board | substrate which is hard to bend.
[0009]
With this structure, the connection between the semiconductor chip and the insulating substrate only rises to a temperature of about 280 to 300 ° C., Sn melts and Au diffuses, so that an Au—Sn eutectic alloy is formed. It can be fused in about 1 second, that is, about 1/20 of the time when using a conventional ACF. As a result, the productivity is greatly improved, and it is not necessary to apply a high pressure that affects the circuit element for a long time, and the pressure does not adversely affect the circuit element. In addition, since the wiring other than the junction is made of Au having a high melting point, the soldering temperature during mounting does not cause any trouble.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Next, the semiconductor device of the present invention will be described with reference to the drawings. The semiconductor device according to the present invention has a circuit element (semiconductor element) formed on the semiconductor chip 1 and an electrode for connection with the outside around the surface, as shown in FIG. A pad is formed. On the other hand, a wiring 21 is formed on one surface side of the insulating substrate 2 and an external connection terminal 22 such as a solder ball is formed on the other surface side in connection with the wiring 21. The connection portion between the electrode pad 11 and the wiring 21 of the semiconductor chip 1 is characterized by being joined by the Au—Sn alloy layer 3.
[0014]
In the example shown in FIG. 1, bumps 12 are formed on the surface of electrode pads 11 connected to the outside of the semiconductor chip 1 to a thickness of about 10 to 30 μm by plating or the like. The bump 12 itself is formed in the same manner as in the prior art. For example, as shown in FIG. 1 (b), a partial enlarged view of the joint before joining is shown, the intermediate metal layer 14 is formed on the electrode terminal 11 made of Al or the like. The intermediate metal layer 14 is made of Ti or Cr, the second layer is made of W, Pt, Ag, Cu, Ni or the like, and the third layer is made of Au or the like. It is done. And bump 12 is formed on it by Au, Cu, etc. The intermediate metal layer 14 is used as a base of the bump 12, and is not limited to this example. The first layer can be composed of a Ti—W alloy layer or the like, and the second layer can be an Au layer or the like. The Au layer of the third layer or the second layer is for improving the adhesion with the Au bump provided thereon, and the Au layer remains alone after the Au bump is provided. is not. Reference numeral 17 denotes an insulating film. The circuit elements (semiconductor elements), wirings formed on the surface of the semiconductor substrate, electrode pads, insulating films, and the like are formed in the same manner as in a normal semiconductor device manufacturing process.
[0015]
The insulating substrate 2 is made of a flexible film such as a polyimide film, but may be a dielectric substrate such as a printed board made of glass epoxy or the like, or a ceramic substrate, instead of a polyimide film. From the viewpoint of miniaturization of the semiconductor device, the insulating substrate 2 is preferably as thin as possible. On the surface (one surface) of this insulating substrate 2, like a normal film substrate or printed circuit board, a Cu film or the like provided on the entire surface of the substrate surface by vapor deposition or the like is patterned, and Au or the like is electroplated. Thus, the wiring 21 composed of the Cu film 21a and the Au film 21b is formed. One end of the wiring 21 is formed so as to be connected to the electrode pad 11 (bump 12) of the semiconductor chip 1, and the other end is led to the central portion side of the insulating substrate 2. And connected to an external connection terminal 22 formed on the back surface of the insulating substrate 2.
[0016]
As shown in an enlarged view in FIG. 1B, an Sn coating 3a is further provided at a thickness of about 0.5 to 3 μm by electroless plating or sputtering at the connection portion of the wiring 21 with the bump 12. ing. This Sn coating 3 a is provided only at the connection portion with the bump 12. The Sn coating 3a is preferably provided in a spot manner only at the connection portion of the wiring 21, since metal diffusion can be controlled. On the other hand, the Sn coating 3a is provided at the joint, so that the melting point of Au is about 1064 ° C. (In the case of bonding between Au bumps, the same metal is used. On the other hand, the melting point of Sn is about 232 ° C., and when it reaches about 230 ° C., it melts, forms an eutectic with Au, and is alloyed at about 280 ° C. from the Au—Sn alloy. The alloy layer 3 to be formed is formed on the joint surface, and the bump 12 and the wiring 21 are welded. That is, the bump 12 and the wiring 21 can be fused at a low temperature that does not hinder circuit elements and the like formed on the semiconductor substrate.
[0017]
The alloy layer 3 is formed by alloying of Au and Sn, and if it is a complete eutectic alloy, it becomes Au 80 wt% and Sn 20 wt%, but even if the entire joint is not a eutectic alloy, Moreover, it does not need to be a uniform alloy layer. As a result of intensive studies by the inventor, there was no problem in the bonding force if the alloy layer with Au of 65 wt% or more was at least half of the bonded portion (bonded area).
[0018]
The semiconductor chip 1 and the insulating substrate 2 are connected to each other by, for example, placing the insulating substrate 2 on a substrate stage that can be heated and mounting the semiconductor chip 1 on one end of the bump 12 and the wiring 21 by a mounter. By aligning so that the Sn coating 3a matches, and heating to about 300 ° C. while applying pressure, the Sn coating 3a melts to form a eutectic with Au of the bumps 12, and the alloy layer 3 is formed. Form. Since the alloy layer 3 is in a molten state at about 300 ° C., the bump 12 and one end of the wiring 21 are in contact with each other in the molten state of the alloy layer 3, and are solidified and bonded by releasing the heating.
[0019]
The gap between the semiconductor chip 1 and the insulating substrate 2 is filled with an insulating resin 7 made of an epoxy resin or an elastomer and is firmly fixed. Although it can be used as it is as a semiconductor device, the package 4 is formed by molding the semiconductor chip 1 side of the insulating substrate 2 with an epoxy resin or the like, as shown in FIG. You can also. By adopting this shape, the connection portion with the printed circuit board or the like has the same shape as that of a normal semiconductor device, and is directly mounted on the circuit board or the like by the external connection terminals 22 distributed over the entire back surface of the semiconductor device by soldering. A semiconductor device that can be obtained is obtained. In FIG. 2, the same parts as those in FIG.
[0020]
According to the semiconductor device of the present invention, since the connection between the bump of the semiconductor chip and the wiring of the insulating substrate is bonded by the Au—Sn alloy layer, the bump is formed with a metal material having a high melting point such as Au. It is possible to perform bonding at a low temperature of about 280 to 300 ° C. and for about 1 second and in a short time of about 1/20 when using a conventional ACF. As a result, productivity is greatly improved and bonding is performed by alloying. Therefore, even when the temperature rises to about 260 ° C. when the semiconductor device is soldered to a circuit board or the like, the alloy layer is melted. The adhesive part will not peel off. In addition, since bonding is performed in a short time at a low temperature of about 300 ° C., mechanical or thermal stress is not applied to the semiconductor element (circuit element) formed on the semiconductor substrate, and fluctuations in element characteristics occur. Not at all. Therefore, a highly reliable semiconductor device can be obtained.
[0021]
On the other hand, the Au layer remains as it is in the portions other than the bumps and wiring joints of the semiconductor chip, or even if alloyed, the proportion of Sn is small, and by applying an external force by raising the temperature to about 300 ° C., While maintaining the mechanical strength of the bump and wiring sufficiently, only the joint can be melted and easily peeled off. In other words, the solder reflow temperature is a very thin layer even if there is a part to be melted, and it does not separate because no external force is applied, but if you want to replace the semiconductor chip, etc. By applying an external force, it can be easily separated and the semiconductor chip can be replaced.
[0022]
In the example shown in FIG. 1, the Sn coating 3 a is provided at the connection portion of the wiring 21, but this Sn coating 3 a may be formed on the surface of the bump 12 of the semiconductor chip 1. In addition, an Au—Sn alloy layer may be provided directly on either side without providing the Sn coating, and bonding may be performed using the alloy layer. In this case, there is no Au layer on the surface of the bump or wiring, and the Au—Sn alloy can be diffused into the Cu layer or the like and bonded by intermetallic bonding even if the Cu layer remains. Further, the bump 12 may not be formed on the semiconductor chip, and the surface of the electrode pad 11 may be subjected to Au plating or the like to be directly bonded to the wiring 21 or the like. In short, by joining the joints with an Au—Sn alloy, it is possible to obtain a strong joint against a solder reflow temperature or the like when mounting a semiconductor device while joining at a low temperature.
[0023]
In each of the above-described examples, the semiconductor device has a structure in which one semiconductor chip is simply bonded to one insulating substrate. However, two or more semiconductor chips are mounted on one insulating substrate. The same applies to bonding.
[0024]
【The invention's effect】
As described above, according to the present invention, when a semiconductor chip and an insulating substrate (film substrate) are bonded in a CSP type semiconductor device, the bonding can be performed in a very short time. Therefore, there is no possibility of affecting the circuit elements formed on the semiconductor chip, and the reliability of the circuit elements can be greatly improved. Furthermore, a circuit element can be formed under or near the electrode pad, which contributes to high integration.
[0025]
Also, since it is bonded via a metal layer that is easily separated at 300 ° C. or lower, when replacing a semiconductor chip, the replacement can be performed very easily without excessively damaging the semiconductor chip due to excessive temperature rise. Can do. In addition, there is no separation at all due to solder reflow during mounting after bonding, and the reliability of the semiconductor chip and its bonding is greatly improved.
[Brief description of the drawings]
FIG. 1 is a cross-sectional explanatory view showing an embodiment of a semiconductor device according to the present invention and a partially enlarged explanatory view of both before bonding.
2 is an explanatory cross-sectional view of an example in which a package is formed in the semiconductor device shown in FIG. 1;
FIG. 3 is an explanatory cross-sectional view showing a conventional CSP type semiconductor device.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Insulating substrate 3 Au-Sn alloy layer 3a Sn coating 11 Electrode pad 12 Bump 21 Wiring 22 External connection terminal

Claims (1)

回路素子が形成され周囲に外部と接続用の電極パッドが形成される半導体チップと、一面側に、前記半導体チップの電極パッドと接続される部分に一端部を有し、他端部が中央部側に導かれる配線が形成され、他面側に、該配線の他端部と接続して外部接続端子が形成される絶縁性基板とからなり、前記半導体チップの電極パッド上にＡｕからなるバンプが形成され、前記配線がＣｕ膜と表面に形成されるＡｕ膜とからなり、前記バンプの表面または前記配線の接続部のみにスポット的に設けられる０ . ５〜３μｍ厚のＳｎ被膜により、前記バンプと前記絶縁性基板の配線の一端部とが、Ａｕ-Ｓｎ合金層を介して接合されると共に、該接合される部分の面積の半分以上はＡｕが６５ｗｔ％以上のＡｕ - Ｓｎ合金層となるよう接合され、前記絶縁性基板の前記半導体チップが設けられた側のほぼ全面に、前記半導体チップを完全に被覆するように樹脂が設けられることによりパッケージが形成されてなる半導体装置。A semiconductor chip in which circuit elements are formed and electrode pads for connection with the outside are formed around the semiconductor chip, and one end portion is provided on one surface side of the semiconductor chip and the other end portion is a central portion. A bump formed of Au on the electrode pad of the semiconductor chip. The wiring is led to the side, and is formed on the other side of the insulating substrate on which the external connection terminal is formed by connecting to the other end of the wiring. The wiring is composed of a Cu film and an Au film formed on the surface, and is formed by spot coating only on the surface of the bump or the connection portion of the wiring . one end portion of the bump and the wiring of the insulating substrate is joined through the Au-Sn alloy layer Rutotomoni, more than half of the area of the portion engaged該接the Au is 65 wt% or more of Au - and Sn alloy layer so as joined, the absolute Substantially the entire surface, a semiconductor device formed by the package formed by the resin is provided so as to completely cover the semiconductor chips on which the semiconductor chip is provided sex substrate.
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