JP3707481B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP3707481B2
JP3707481B2 JP2003271768A JP2003271768A JP3707481B2 JP 3707481 B2 JP3707481 B2 JP 3707481B2 JP 2003271768 A JP2003271768 A JP 2003271768A JP 2003271768 A JP2003271768 A JP 2003271768A JP 3707481 B2 JP3707481 B2 JP 3707481B2
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JP
Japan
Prior art keywords
resin layer
layer
semiconductor device
resin
manufacturing
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Expired - Fee Related
Application number
JP2003271768A
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English (en)
Japanese (ja)
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JP2004158827A (ja
JP2004158827A5 (https=
Inventor
輝直 花岡
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2003271768A priority Critical patent/JP3707481B2/ja
Priority to US10/679,467 priority patent/US7176572B2/en
Publication of JP2004158827A publication Critical patent/JP2004158827A/ja
Publication of JP2004158827A5 publication Critical patent/JP2004158827A5/ja
Application granted granted Critical
Publication of JP3707481B2 publication Critical patent/JP3707481B2/ja
Priority to US11/649,871 priority patent/US7294933B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W15/00—Highly-doped buried regions of integrated devices
    • H10W15/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/656—Fan-in layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/242—Dispositions, e.g. layouts relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/244—Dispositions, e.g. layouts relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/281—Auxiliary members
    • H10W72/283—Reinforcing structures, e.g. bump collars
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H10W72/9223—Bond pads being integral with underlying chip-level interconnections with redistribution layers [RDL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H10W72/9445—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2003271768A 2002-10-15 2003-07-08 半導体装置の製造方法 Expired - Fee Related JP3707481B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003271768A JP3707481B2 (ja) 2002-10-15 2003-07-08 半導体装置の製造方法
US10/679,467 US7176572B2 (en) 2002-10-15 2003-10-07 Semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US11/649,871 US7294933B2 (en) 2002-10-15 2007-01-05 Semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002300261 2002-10-15
JP2003271768A JP3707481B2 (ja) 2002-10-15 2003-07-08 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2004158827A JP2004158827A (ja) 2004-06-03
JP2004158827A5 JP2004158827A5 (https=) 2005-07-07
JP3707481B2 true JP3707481B2 (ja) 2005-10-19

Family

ID=32827895

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003271768A Expired - Fee Related JP3707481B2 (ja) 2002-10-15 2003-07-08 半導体装置の製造方法

Country Status (2)

Country Link
US (2) US7176572B2 (https=)
JP (1) JP3707481B2 (https=)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7169691B2 (en) * 2004-01-29 2007-01-30 Micron Technology, Inc. Method of fabricating wafer-level packaging with sidewall passivation and related apparatus
DE102004009296B4 (de) * 2004-02-26 2011-01-27 Siemens Ag Verfahren zum Herstellen einer Anordnung eines elektrischen Bauelements
JP2006339189A (ja) * 2005-05-31 2006-12-14 Oki Electric Ind Co Ltd 半導体ウェハおよびそれにより形成した半導体装置
DE102005050127B3 (de) * 2005-10-18 2007-05-16 Infineon Technologies Ag Verfahren zum Aufbringen einer Struktur aus Fügematerial auf die Rückseiten von Halbleiterchips
JP2007115958A (ja) * 2005-10-21 2007-05-10 Seiko Epson Corp 半導体装置
JP2007115957A (ja) 2005-10-21 2007-05-10 Seiko Epson Corp 半導体装置及びその製造方法
US7518211B2 (en) * 2005-11-11 2009-04-14 United Microelectronics Corp. Chip and package structure
JP5268082B2 (ja) * 2006-02-22 2013-08-21 シチズン電子株式会社 光半導体装置
JP4193897B2 (ja) 2006-05-19 2008-12-10 カシオ計算機株式会社 半導体装置およびその製造方法
JP4995551B2 (ja) * 2006-12-01 2012-08-08 ローム株式会社 半導体装置及び半導体装置の製造方法
US20090079072A1 (en) * 2007-09-21 2009-03-26 Casio Computer Co., Ltd. Semiconductor device having low dielectric insulating film and manufacturing method of the same
US8587124B2 (en) 2007-09-21 2013-11-19 Teramikros, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same
JP2009260272A (ja) * 2008-03-25 2009-11-05 Panasonic Corp 基板の加工方法および半導体チップの製造方法ならびに樹脂接着層付き半導体チップの製造方法
JP4666028B2 (ja) 2008-03-31 2011-04-06 カシオ計算機株式会社 半導体装置
US7952200B2 (en) * 2008-07-16 2011-05-31 Infineon Technologies Ag Semiconductor device including a copolymer layer
GB2464549B (en) * 2008-10-22 2013-03-27 Cambridge Silicon Radio Ltd Improved wafer level chip scale packaging
US7875972B2 (en) * 2009-06-25 2011-01-25 International Business Machines Corporation Semiconductor device assembly having a stress-relieving buffer layer
US20110079908A1 (en) * 2009-10-06 2011-04-07 Unisem Advanced Technologies Sdn. Bhd. Stress buffer to protect device features
US8264089B2 (en) 2010-03-17 2012-09-11 Maxim Integrated Products, Inc. Enhanced WLP for superior temp cycling, drop test and high current applications
US9202714B2 (en) * 2012-04-24 2015-12-01 Micron Technology, Inc. Methods for forming semiconductor device packages
JP5968711B2 (ja) * 2012-07-25 2016-08-10 ルネサスエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
US10008413B2 (en) * 2013-08-27 2018-06-26 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level dicing method
US9875913B2 (en) * 2013-10-30 2018-01-23 Taiwan Semiconductor Manufacturing Company, Ltd. Method for singulating packaged integrated circuits and resulting structures

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JP3015712B2 (ja) * 1995-06-30 2000-03-06 日東電工株式会社 フィルムキャリアおよびそれを用いてなる半導体装置
US5773359A (en) * 1995-12-26 1998-06-30 Motorola, Inc. Interconnect system and method of fabrication
TW480636B (en) * 1996-12-04 2002-03-21 Seiko Epson Corp Electronic component and semiconductor device, method for manufacturing and mounting thereof, and circuit board and electronic equipment
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
JP3910694B2 (ja) 1997-09-11 2007-04-25 沖電気工業株式会社 外部端子付半導体素子の製造方法
US6097087A (en) * 1997-10-31 2000-08-01 Micron Technology, Inc. Semiconductor package including flex circuit, interconnects and dense array external contacts
JPH11297873A (ja) 1998-04-13 1999-10-29 Seiko Epson Corp 半導体装置およびその製造方法
US6232666B1 (en) * 1998-12-04 2001-05-15 Mciron Technology, Inc. Interconnect for packaging semiconductor dice and fabricating BGA packages
JP2000311921A (ja) * 1999-04-27 2000-11-07 Sony Corp 半導体装置およびその製造方法
JP2000340588A (ja) 1999-05-26 2000-12-08 Sony Corp 半導体装置の製造方法
KR100298827B1 (ko) * 1999-07-09 2001-11-01 윤종용 재배선 기판을 사용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
KR100298828B1 (ko) * 1999-07-12 2001-11-01 윤종용 재배선 필름과 솔더 접합을 이용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
JP4401527B2 (ja) 2000-04-03 2010-01-20 イビデン株式会社 半導体チップの製造方法
US6242156B1 (en) * 2000-06-28 2001-06-05 Gary Ganghui Teng Lithographic plate having a conformal radiation-sensitive layer on a rough substrate
JP4174174B2 (ja) * 2000-09-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置およびその製造方法並びに半導体装置実装構造体
DE10116069C2 (de) * 2001-04-02 2003-02-20 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zu seiner Herstellung
JP2003007652A (ja) * 2001-06-26 2003-01-10 Mitsubishi Electric Corp 半導体チップの製造方法
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6891248B2 (en) * 2002-08-23 2005-05-10 Micron Technology, Inc. Semiconductor component with on board capacitor

Also Published As

Publication number Publication date
JP2004158827A (ja) 2004-06-03
US7294933B2 (en) 2007-11-13
US20050040523A1 (en) 2005-02-24
US20070120251A1 (en) 2007-05-31
US7176572B2 (en) 2007-02-13

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