JP3707481B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP3707481B2
JP3707481B2 JP2003271768A JP2003271768A JP3707481B2 JP 3707481 B2 JP3707481 B2 JP 3707481B2 JP 2003271768 A JP2003271768 A JP 2003271768A JP 2003271768 A JP2003271768 A JP 2003271768A JP 3707481 B2 JP3707481 B2 JP 3707481B2
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Prior art keywords
resin layer
layer
semiconductor device
resin
manufacturing
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Expired - Fee Related
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JP2003271768A
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English (en)
Japanese (ja)
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JP2004158827A5 (enExample
JP2004158827A (ja
Inventor
輝直 花岡
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Seiko Epson Corp
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Seiko Epson Corp
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Priority to JP2003271768A priority Critical patent/JP3707481B2/ja
Priority to US10/679,467 priority patent/US7176572B2/en
Publication of JP2004158827A publication Critical patent/JP2004158827A/ja
Publication of JP2004158827A5 publication Critical patent/JP2004158827A5/ja
Application granted granted Critical
Publication of JP3707481B2 publication Critical patent/JP3707481B2/ja
Priority to US11/649,871 priority patent/US7294933B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
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    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
JP2003271768A 2002-10-15 2003-07-08 半導体装置の製造方法 Expired - Fee Related JP3707481B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2003271768A JP3707481B2 (ja) 2002-10-15 2003-07-08 半導体装置の製造方法
US10/679,467 US7176572B2 (en) 2002-10-15 2003-10-07 Semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment
US11/649,871 US7294933B2 (en) 2002-10-15 2007-01-05 Semiconductor wafer, semiconductor device and method of manufacturing the same, circuit board, and electronic equipment

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002300261 2002-10-15
JP2003271768A JP3707481B2 (ja) 2002-10-15 2003-07-08 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2004158827A JP2004158827A (ja) 2004-06-03
JP2004158827A5 JP2004158827A5 (enExample) 2005-07-07
JP3707481B2 true JP3707481B2 (ja) 2005-10-19

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JP (1) JP3707481B2 (enExample)

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JP5268082B2 (ja) * 2006-02-22 2013-08-21 シチズン電子株式会社 光半導体装置
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JP4995551B2 (ja) * 2006-12-01 2012-08-08 ローム株式会社 半導体装置及び半導体装置の製造方法
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US8587124B2 (en) 2007-09-21 2013-11-19 Teramikros, Inc. Semiconductor device having low dielectric insulating film and manufacturing method of the same
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KR100298827B1 (ko) * 1999-07-09 2001-11-01 윤종용 재배선 기판을 사용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
KR100298828B1 (ko) * 1999-07-12 2001-11-01 윤종용 재배선 필름과 솔더 접합을 이용한 웨이퍼 레벨 칩 스케일 패키지 제조방법
JP4401527B2 (ja) 2000-04-03 2010-01-20 イビデン株式会社 半導体チップの製造方法
US6242156B1 (en) * 2000-06-28 2001-06-05 Gary Ganghui Teng Lithographic plate having a conformal radiation-sensitive layer on a rough substrate
JP4174174B2 (ja) * 2000-09-19 2008-10-29 株式会社ルネサステクノロジ 半導体装置およびその製造方法並びに半導体装置実装構造体
DE10116069C2 (de) * 2001-04-02 2003-02-20 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip und Verfahren zu seiner Herstellung
JP2003007652A (ja) * 2001-06-26 2003-01-10 Mitsubishi Electric Corp 半導体チップの製造方法
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
US6891248B2 (en) * 2002-08-23 2005-05-10 Micron Technology, Inc. Semiconductor component with on board capacitor

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US20070120251A1 (en) 2007-05-31
US7294933B2 (en) 2007-11-13
US20050040523A1 (en) 2005-02-24
US7176572B2 (en) 2007-02-13

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