JP3391462B2 - パワーハイブリッド集積回路 - Google Patents

パワーハイブリッド集積回路

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Publication number
JP3391462B2
JP3391462B2 JP51743298A JP51743298A JP3391462B2 JP 3391462 B2 JP3391462 B2 JP 3391462B2 JP 51743298 A JP51743298 A JP 51743298A JP 51743298 A JP51743298 A JP 51743298A JP 3391462 B2 JP3391462 B2 JP 3391462B2
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JP
Japan
Prior art keywords
integrated circuit
blind holes
hybrid integrated
substrate
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP51743298A
Other languages
English (en)
Other versions
JP2000516043A (ja
Inventor
イオフダルスキー，ビクトル・アナトーリエビッチ
Original Assignee
サムソン・エレクトロニクス・カンパニー・リミテッド
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Publication of JP2000516043A publication Critical patent/JP2000516043A/ja
Application granted granted Critical
Publication of JP3391462B2 publication Critical patent/JP3391462B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Materials Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Structure Of Printed Boards (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Description

【発明の詳細な説明】 技術分野 本発明は、一般に、電子工学に関し、特に、パワーハ
イブリッド集積回路に関する。
背景技術 従来技術のパワーハイブリッド集積回路として、接続
配線としての金属被覆パターンとたくさんのくぼみを有
する誘電体基板を備えるものが、知られている（US,A,
4,737,235）。半導体チップが、結合材によって固定さ
れ、その結果、ボンディングパッドを有するチップの表
面が基板表面と同一平面上にあり、チップボンディング
パッドは、接続配線としての金属被覆パターンと電気的
に接続されている。
上述の回路構造は、チップから基板への伝熱が小さい
領域を有し、それゆえに、熱消散容量が不十分である。
従来技術ハイブリッド集積回路として、さらに、以下
のものが知られている（EP,A,0334397）。すなわち、お
もて面に接続配線としての金属被覆パターンと、本質的
にくぼみ底の穴のシステムであるヒートシンクにおもて
の基板面のくぼみに位置する少なくとも１つの実装パッ
ドとを有する両面金属被覆の誘電体基板を備え、その穴
は熱伝導性の材料で満たされている。基板は、熱伝導性
のベースに対してその裏面で取り付けられ、裸の電子チ
ップは、実装パッドのくぼみに配置され且つ固定されて
いる。その結果、チップおもて面は、接続配線としての
金属被覆パターンと同一平面上にある。
この回路構造は、半導体デバイスの幅広い範囲で使用
することができない。
発明の概要 本発明の主たる目的は、チップからの熱消散状態を改
良することができるヒートシンクの構造上の配置を有す
るパワーハイブリッド集積回路を提供することである。
前述の目的が、以下のことによって達成される。すな
わち、パワーマイクロ波ハイブリッド集積回路におい
て、そのおもて面に接続配線としての金属被覆パターン
と、熱伝導性の材料で満たされて本質的にくぼみ底の複
数の穴のシステムであるヒートシンク上に基板おもて面
のくぼみに位置決めされた少なくとも１つの実装パッド
とを備える両面金属被覆の誘電体基板を備える。基板
は、熱伝導性のベースに対してその裏面で結合され、裸
の電子回路チップは、実装パッドのくぼみに配置され且
つ固定されている。その結果、チップおもて面は、接続
配線としての金属被覆パターンと同一平面上にあり、く
ぼみの底の複数のヒートシンク穴が行き止まりになって
おり、前記止まり穴の底の残りの厚さが、１μｍ〜999
μｍであり、チップとくぼみの側壁との間のスペース
は、少なくとも部分的に熱伝導性の材料で満たされてい
る。
実装パッドの中に形成され且つ熱伝導性の結合材で満
たされた基板の複数の止まり穴のシステムの中に、熱伝
導性のエレメントを配置することにより、以下のことが
可能になる。すなわち、共通のエミッタ又は共通ベース
の二極式の接合トランジスタを組み込むことができる回
路を備えることができるとともに、そこからの熱消散を
そのままにした状態でチップを電気的絶縁するために基
板に組み込まれたコンデンサーとして、くぼみの金属被
覆とシールド金属被覆との間のギャップを用いることが
できることによって、提案した回路の応用の領域が同時
に広がることができる。
チップのくぼみの側壁との間のスペースを少なくとも
部分的に熱伝導性の結合材で満たすことによって、伝熱
領域が増大して、チップからの熱消散が良くなる。
シールド接地金属被覆からチップを電気的に絶縁する
ために、止まり穴の底の残りの厚さの下限が、必要に応
じて決まるが、その上限は、伝熱領域を増大して伝熱条
件を改良するという最低限の到達できる効果によって決
まる。
基板の裏面に形成され且つくぼみの底の複数の止まり
穴の間に形成されるとともに、熱伝導性の材料で満たさ
れた反対側の複数の止まり穴を設けることによって、伝
熱領域が増大して、チップからの熱消散の速度が増大す
る。複数の止まり穴の間の残りの誘電体厚みは、１μｍ
〜500μｍである。
複数の止まり穴の間の誘電体の残りの厚さの下限は、
シールド接地金属被覆からチップを電気的に絶縁する必
要性によって決まるが、その上限は、チップから熱伝導
性ベースへの伝熱を改良するという最低限の到達できる
効果によって決まる。
面格子の形で複数の止まり穴のシステムを設けること
によって、熱接触領域が増大して、チップからの熱消散
が良くなる。
熱伝導性の材料で満たされ且つくぼみ周辺部に沿って
基板おもて面に位置する行き止まりの溝を設けることに
よって、熱接触領域が増大して、チップからの熱消散が
良くなる。
くぼみ，複数の止まり穴，行き止まりの溝を金属被覆
することによって、ぬれ性が向上して熱伝導性の材料を
満たすことが容易になり、熱接触が促進される。
図面の簡単な説明 本発明は、いくつかの代表的な実施形態について添付
の図面を参照して説明する。
図１は、パワーハイブリッド集積回路の断面図であ
る。
図２は、基板の裏面に止まり穴をもつパワーハイブリ
ッド集積回路の断面図である。
図3a及び図3bは、面格子の形のくぼみの底に複数の止
まり穴のシステムを有するパワーハイブリッド集積回路
の基板の断面図及び平面図である。
図４は、くぼみのおもて面にさらに複数の止まり穴と
面格子の形の基板の裏面に複数の止まり穴のシステムと
をもつパワーハイブリッド集積回路の断面図である。
図５は、くぼみの周辺部に沿って行き止まりの溝をも
つパワーハイブリッド集積回路の平面図である。
詳細な説明 本発明に係るパワーマイクロ波ハイブリッド集積回路
は、例えば、ポリコールからなり、両面に金属被覆した
誘電体基板１（図１）を備える。基板１は、接続配線と
しての金属被覆パターン２をそのおもて面に有し、その
金属被覆は、Ti（100オーム／平方mm）−Pd（0.2μｍ）
−Au（３μｍ）、又はCr（100オーム／平方mm）−Cu
（１μｍ）−Cu（電気化学的に３μｍを形成）−Ni（0.
6μｍ）−Au（３μｍ）の構成を有する。
基板１は、ヒートシンク５上に0.6mm×0.55mm×0.33m
mのくぼみ４の中に位置する１つの実装パッド３を有す
る。ヒートシンクは、本質的に、例えば、0.1mmの直径
と0.2mmのピッチとを有する基板１の複数の止まり穴６
のシステムである。複数の実装パッド３が設けられてい
る。
例えば、合金 エム・デー−50（ＭД−50）から作成
した熱伝導性のベース７は、以下の構成のコーティング
を備える。すなわち、Ni（0.6μｍ）−Au（３μｍ）
が、例えば、ロウ付けによって基板１の裏面の金属被覆
８と結合される。裸の電子チップ９、例えば、0.5mm×
0.15mm×0.3mmのトランジスタ３ペー603ベー−５（３П
603Б−５）のチップは、熱伝導性の結合材10、例え
ば、共晶Au−Siの硬合金によって、実装パッド３とくぼ
み４の側面11とに結合している。そして、それらは、例
えば、30μｍの直径を有する金ワイヤー12によって金属
被覆パターン２と電気的に接続されている。熱伝導性の
結合材10が、複数の止まり穴６を満たしており、少なく
とも部分的に、チップ９とくぼみ４の側壁との間のスペ
ースを満たす。複数の止まり穴６の底の残りの厚さは、
100μｍであるように選択されている。
基板１（図２）の裏面は、複数の止まり穴６の間に形
成され且つくぼみ４の底に形成された反対側の複数の止
まり穴13を有し、前記穴13は、例えば、直径50μｍであ
り、Au−Siの硬ハンダのような熱伝導性の材料10で満た
されている。複数の止まり穴13の間の誘電体の残りの厚
さは、50μｍである。
くぼみ４の底の複数の止まり穴６（図3a,図3b）のシ
ステムは、例えば、厚さ0.1mmでピッチ0.2mmの溝を有す
る面格子の形である。
複数の止まり穴14（図４）が、さらに、くぼみ４の側
面に設けられる。複数の止まり穴15のシステムは、幅50
μm,ピッチ0.25mmで配置された溝を有する面格子の形で
基板１の裏面に設けられる。
行き止まりの溝16（図５）が、くぼみ４の周辺部に沿
って基板１のおもて面に設けられている。その溝は、例
えば、0.05mm×0.5mm×0.3mmの大きさであり、熱伝導性
の材料10で満たされている。
くぼみ４と、複数の止まり穴6,13,14,15と、溝16とは
金属被覆され、金属被覆の構造は、例えば、Pd−Ni（0.
2μｍ）−Au（３μｍ）のようになっている。
本発明による、パワーハイブリッド集積回路は、以下
のように作用する。
トランジスタが動作すると、くぼみ４（図１）の底の
残りの厚さに設けた熱消散システム及びくぼみ４の側壁
によって熱を放散するが、そのことは、より効率的な熱
拡散に寄与してトランジスタの動作時の信頼性が増す。
本願のパワーハイブリッド集積回路を用いることによ
って、電子チップ９デバイスの電気的絶縁を得ることが
できるが、基板１及び熱伝導性のベース７によってチッ
プ９からの熱の消散が維持されるか、さらに増大する。
本発明のいくらかの好ましい実施形態を前述の説明の
中で開示したが、本発明の精神及び範囲から逸脱しない
範囲内で、いろいろな修正と改良が行なえると理解され
るであろう。
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 平４−243154（ＪＰ，Ａ) 特開 平２−72655（ＪＰ，Ａ) 実開 昭60−33437（ＪＰ，Ｕ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 23/12 H01L 23/36 H01L 25/00

Claims (9)

    (57)【特許請求の範囲】
  1. 【請求項１】そのおもて面に金属被覆パターン（２）
    と、本質的にくぼみ（４）の底の複数の止まり穴（６）
    のシステムであり、熱伝導性の材料（10）で満たされた
    ヒートシンク（５）上に基板（１）のおもて面のくぼみ
    （４）に位置決めされた少なくとも１つの実装パッド
    （３）とを有する、両面金属被覆の誘電体基板（１）を
    備えるパワーハイブリッド集積回路であって、 前記基板（１）がその裏面で熱伝導性のベース（７）と
    結合しており、 裸の電子チップ（９）がくぼみ（４）の実装パッド
    （３）に配置され且つ固定され、その結果、チップ
    （９）のおもて面が金属被覆パターン（２）と同一平面
    上にあり、 くぼみ（４）の底のヒートシンク（５）の複数の穴
    （６）が行き止まりであり、前記止まり穴（６）の底の
    残りの厚さが１μｍ〜999μｍであり、くぼみ（４）の
    チップ（９）と側壁との間のスペースは、少なくとも部
    分的に熱伝導性の材料（10）で満たされていることを特
    徴とするパワーハイブリッド集積回路。
  2. 【請求項２】反対側の複数の止まり穴（13）は、基板
    （１）の裏面にあって、くぼみ（４）の底の複数の止ま
    り穴（６）の間に設けられており、前記反対側の複数の
    止まり穴（13）は熱伝導性の材料（10）で満たされてお
    り、前記くぼみ（４）の底の複数の止まり穴（６）と反
    対側の止まり穴（13）との間の誘電体厚みが１μｍ〜50
    0μｍであることを特徴とする、請求項１記載のパワー
    ハイブリッド集積回路。
  3. 【請求項３】くぼみ（４）の底の複数の止まり穴（６）
    のシステムが、面格子の形であることを特徴とする、請
    求項１又は請求項２記載のパワーハイブリッド集積回
    路。
  4. 【請求項４】複数の止まり穴（14）は、くぼみ（４）の
    側面にも設けられていることを特徴とする請求項1,請求
    項２又は請求項３記載のパワーハイブリッド集積回路。
  5. 【請求項５】基板（１）の裏面に設けられた複数の止ま
    り穴（15）システムが、面格子の形であることを特徴と
    する請求項1,請求項２又は請求項３記載のパワーハイブ
    リッド集積回路。
  6. 【請求項６】熱伝導性の材料（10）で満たされた行き止
    まりの溝（16）が、くぼみ（４）の周辺部に沿って基板
    （１）のおもて面に設けられていることを特徴とする、
    請求項1,請求項２又は請求項３記載のパワーハイブリッ
    ド集積回路。
  7. 【請求項７】くぼみ（４）が、金属被覆されていること
    を特徴とする、請求項１記載のパワーハイブリッド集積
    回路。
  8. 【請求項８】複数の止まり穴（6,13,14,15）が、金属被
    覆されていることを特徴とする、請求項１、２、４又は
    ５記載のパワーハイブリッド集積回路。
  9. 【請求項９】行き止まりの溝（16）が、金属被覆されて
    いることを特徴とする、請求項６記載のパワーハイブリ
    ッド集積回路。
JP51743298A 1996-10-10 1996-10-10 パワーハイブリッド集積回路 Expired - Fee Related JP3391462B2 (ja)

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PCT/RU1996/000293 WO1998015980A1 (fr) 1996-10-10 1996-10-10 Circuit integre hybride et de grande puissance

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KR19990072030A (ko) 1999-09-27
US6115255A (en) 2000-09-05
KR100420994B1 (ko) 2004-06-18
JP2000516043A (ja) 2000-11-28
WO1998015980A1 (fr) 1998-04-16

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