JP3361847B2 - 基板上の構造を平坦化する方法 - Google Patents

基板上の構造を平坦化する方法

Info

Publication number
JP3361847B2
JP3361847B2 JP02957193A JP2957193A JP3361847B2 JP 3361847 B2 JP3361847 B2 JP 3361847B2 JP 02957193 A JP02957193 A JP 02957193A JP 2957193 A JP2957193 A JP 2957193A JP 3361847 B2 JP3361847 B2 JP 3361847B2
Authority
JP
Japan
Prior art keywords
layer
tin
planarization
substrate
planarizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP02957193A
Other languages
English (en)
Japanese (ja)
Other versions
JPH06120180A (ja
Inventor
エム.モスレヒ メールダッド
Original Assignee
テキサス インスツルメンツ インコーポレイテツド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by テキサス インスツルメンツ インコーポレイテツド filed Critical テキサス インスツルメンツ インコーポレイテツド
Publication of JPH06120180A publication Critical patent/JPH06120180A/ja
Application granted granted Critical
Publication of JP3361847B2 publication Critical patent/JP3361847B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H10P76/2041
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274Photolithographic processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105After-treatment
    • H01L21/31051Planarisation of the insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/32115Planarisation
    • H01L21/3212Planarisation by chemical mechanical polishing [CMP]
    • H10P52/403
    • H10P95/06

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Formation Of Insulating Films (AREA)
JP02957193A 1991-12-31 1993-01-04 基板上の構造を平坦化する方法 Expired - Fee Related JP3361847B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US816458 1991-12-31
US07/816,458 US5284804A (en) 1991-12-31 1991-12-31 Global planarization process

Publications (2)

Publication Number Publication Date
JPH06120180A JPH06120180A (ja) 1994-04-28
JP3361847B2 true JP3361847B2 (ja) 2003-01-07

Family

ID=25220681

Family Applications (1)

Application Number Title Priority Date Filing Date
JP02957193A Expired - Fee Related JP3361847B2 (ja) 1991-12-31 1993-01-04 基板上の構造を平坦化する方法

Country Status (5)

Country Link
US (1) US5284804A (show.php)
EP (1) EP0549994B1 (show.php)
JP (1) JP3361847B2 (show.php)
DE (1) DE69212295T2 (show.php)
TW (1) TW256934B (show.php)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US6714625B1 (en) * 1992-04-08 2004-03-30 Elm Technology Corporation Lithography device for semiconductor circuit pattern generation
US6355553B1 (en) * 1992-07-21 2002-03-12 Sony Corporation Method of forming a metal plug in a contact hole
US6690044B1 (en) 1993-03-19 2004-02-10 Micron Technology, Inc. Approach to avoid buckling BPSG by using an intermediate barrier layer
US5372974A (en) * 1993-03-19 1994-12-13 Micron Semiconductor, Inc. Approach to avoid buckling in BPSG by using an intermediate barrier layer
US5532188A (en) * 1994-03-30 1996-07-02 Wright; Peter J. Global planarization of multiple layers
KR0159388B1 (ko) * 1995-09-30 1999-02-01 배순훈 평탄화 방법
US5885900A (en) * 1995-11-07 1999-03-23 Lucent Technologies Inc. Method of global planarization in fabricating integrated circuit devices
US5837603A (en) * 1996-05-08 1998-11-17 Harris Corporation Planarization method by use of particle dispersion and subsequent thermal flow
US6551857B2 (en) * 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5915167A (en) * 1997-04-04 1999-06-22 Elm Technology Corporation Three dimensional structure memory
JP2001516970A (ja) * 1997-09-18 2001-10-02 シーブイシー プロダクツ、インコーポレイテッド 高性能集積回路の相互接続製造の方法及び装置
US6335288B1 (en) * 2000-08-24 2002-01-01 Applied Materials, Inc. Gas chemistry cycling to achieve high aspect ratio gapfill with HDP-CVD
US7402897B2 (en) * 2002-08-08 2008-07-22 Elm Technology Corporation Vertical system integration
KR100587635B1 (ko) * 2003-06-10 2006-06-07 주식회사 하이닉스반도체 반도체소자의 제조 방법
US20090074962A1 (en) * 2007-09-14 2009-03-19 Asml Netherlands B.V. Method for the protection of an optical element of a lithographic apparatus and device manufacturing method
JP2014053502A (ja) * 2012-09-07 2014-03-20 Toshiba Corp 半導体装置の製造方法
JP2023002853A (ja) * 2019-12-12 2023-01-11 Agc株式会社 積層基板、及びその製造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4655874A (en) * 1985-07-26 1987-04-07 Advanced Micro Devices, Inc. Process for smoothing a non-planar surface
US4676868A (en) * 1986-04-23 1987-06-30 Fairchild Semiconductor Corporation Method for planarizing semiconductor substrates
US4775550A (en) * 1986-06-03 1988-10-04 Intel Corporation Surface planarization method for VLSI technology
US4708770A (en) * 1986-06-19 1987-11-24 Lsi Logic Corporation Planarized process for forming vias in silicon wafers
US4732658A (en) * 1986-12-03 1988-03-22 Honeywell Inc. Planarization of silicon semiconductor devices
US4810335A (en) * 1987-01-20 1989-03-07 Siemens Aktiengesellschaft Method for monitoring etching processes
US4983545A (en) * 1987-03-20 1991-01-08 Nec Corporation Planarization of dielectric films on integrated circuits
US4839311A (en) * 1987-08-14 1989-06-13 National Semiconductor Corporation Etch back detection
JPH063804B2 (ja) * 1988-01-21 1994-01-12 シャープ株式会社 半導体装置製造方法
KR920000708B1 (ko) * 1988-07-22 1992-01-20 현대전자산업 주식회사 포토레지스트 에치백 기술을 이용한 트렌치 캐패시터 형성방법
US4962063A (en) * 1988-11-10 1990-10-09 Applied Materials, Inc. Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing
US5183781A (en) * 1990-01-12 1993-02-02 Nec Corporation Method of manufacturing semiconductor device
JP2518435B2 (ja) * 1990-01-29 1996-07-24 ヤマハ株式会社 多層配線形成法
US5143867A (en) * 1991-02-13 1992-09-01 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes

Also Published As

Publication number Publication date
EP0549994A3 (en) 1993-07-28
TW256934B (show.php) 1995-09-11
US5284804A (en) 1994-02-08
DE69212295D1 (de) 1996-08-22
EP0549994B1 (en) 1996-07-17
EP0549994A2 (en) 1993-07-07
JPH06120180A (ja) 1994-04-28
DE69212295T2 (de) 1997-02-06

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