JP2014053502A - 半導体装置の製造方法 - Google Patents
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Abstract
【解決手段】半導体装置の製造方法は、半導体基板10上に層間絶縁膜13を形成する工程と、前記層間絶縁膜の表面に形成された凹部および凸部を覆うように、前記層間絶縁膜上に膜14を形成する工程と、前記層間絶縁膜が露出するように、CMPにより前記膜を研磨する工程と、前記膜と前記層間絶縁膜とのエッチング速度が同じになるように、前記膜および前記層間絶縁膜をエッチング工程と、を具備する。
【選択図】 図1
Description
図1乃至図9を用いて、本実施形態に係る半導体装置の製造方法について説明する。本実施形態は、素子11が配置された半導体基板10上に形成される層間絶縁膜13の平坦化方法である。より具体的には、表面に凹凸を有する層間絶縁膜13上に有機膜14を形成し、CMPにより有機膜14を平坦化した後、有機膜14および層間絶縁膜13をRIE(Reactive Ion Etching)によりエッチバックする。これにより、層間絶縁膜13へのダメージを軽減しつつ、所望の平坦性を得ることができる。以下に、本実施形態について詳説する。
以下に、図1乃至図7を用いて、本実施形態に係る半導体装置の製造方法について説明する。
以下に、図9を用いて、本実施形態に係るCMP装置について説明する。
以下に、図10および図11を用いて、比較例1に係る半導体装置の製造方法について説明する。比較例1において、本実施形態と異なる点は、有機膜14を形成せず、セリア系スラリーを用いたCMPにより層間絶縁膜13が平坦化される点である。なお、比較例1において、本実施形態と同様の点については、適宜説明を省略する。
以下に、図12および図13を用いて、比較例2に係る半導体装置の製造方法について説明する。比較例2において、本実施形態と異なる点は、有機膜14を形成した後に有機膜14のCMPを行わず、RIEにより層間絶縁膜13および有機膜14が平坦化される点である。なお、比較例2において、本実施形態と同様の点については、適宜説明を省略する。
以下に、図14を用いて、本実施形態および比較例1,2における層間絶縁膜13の平坦化によるダメージおよび平坦性に関する実験結果について説明する。
平坦性…○:25nm以下、×:25nmを超える(凹凸表面の差)
これらダメージおよび平坦性の評価の基準は、配線間のショートが起こる可能性があるか否かで判断されたものである。
上記本実施形態によれば、表面に凹凸を有する層間絶縁膜13(シリコン酸化膜)の平坦化工程において、凹凸を覆うように層間絶縁膜13上に有機膜14を形成する。その後、有機膜14に樹脂粒子スラリーを用いたCMPを行い、有機膜14と層間絶縁膜13との表面を平坦化する。そして、有機膜14および層間絶縁膜13をRIEによりエッチバックする。これにより、平坦化工程における層間絶縁膜13へのダメージを軽減することができる。また、層間絶縁膜13の凹部の底面からの除去量を100nm(より望ましくは50nm)以下にしても、所望の平坦性を得ることができる。すなわち、シリコン酸化膜に対して、セリア系スラリーを用いたCMPよりも高性能な平坦化方法を提供することができる。
Claims (7)
- 半導体基板上に層間絶縁膜を形成する工程と、
前記層間絶縁膜の表面に形成された凹部および凸部を覆うように、前記層間絶縁膜上にノボラック系樹脂を主成分とするレジスト膜で構成される膜を形成する工程と、
前記膜に対して100℃以上170℃以下の温度の第1ベークを行う工程と、
前記層間絶縁膜が露出するように、樹脂粒子スラリーを用いたCMPにより前記膜を研磨する工程と、
前記膜に対して200℃以上400℃以下の温度の第2ベークを行う工程と、
前記膜と前記層間絶縁膜とのエッチング速度が同じになるように、かつ、前記凹部の底面からの前記層間絶縁膜の除去量が100nm以下になるように前記膜および前記層間絶縁膜をエッチングする工程と、
を具備する半導体装置の製造方法。 - 半導体基板上に層間絶縁膜を形成する工程と、
前記層間絶縁膜の表面に形成された凹部および凸部を覆うように、前記層間絶縁膜上に膜を形成する工程と、
前記層間絶縁膜が露出するように、CMPにより前記膜を研磨する工程と、
前記膜と前記層間絶縁膜とのエッチング速度が同じになるように、前記膜および前記層間絶縁膜をエッチングする工程と、
を具備する半導体装置の製造方法。 - 前記膜および前記層間絶縁膜をエッチングする工程は、前記凹部の底面からの前記層間絶縁膜の除去量が100nm以下になるように行われることを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記膜を研磨する工程の前に、前記膜に対して第1ベークを行う工程と、
前記膜および前記層間絶縁膜をエッチバックする工程の前に、前記膜に対して前記第1ベークよりも高温の第2ベークを行う工程と、
をさらに具備することを特徴とする請求項2または請求項3に記載の半導体装置の製造方法。 - 前記第1ベークは100℃以上170℃以下の温度で行われ、前記第2ベークは200℃以上400℃以下の温度で行われることを特徴とする請求項4に記載の半導体装置の製造方法。
- 前記CMPは、樹脂粒子スラリーを用いて行われることを特徴とする請求項2乃至請求項5のいずれか1項に記載の半導体装置の製造方法。
- 前記膜は、ノボラック系樹脂を主成分とするレジスト膜で構成されることを特徴とする請求項2乃至請求項6のいずれか1項に記載の半導体装置の製造方法。
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JP2019510364A (ja) * | 2016-01-25 | 2019-04-11 | キャボット マイクロエレクトロニクス コーポレイション | カチオン重合体助剤を含む研磨組成物 |
CN110544628A (zh) * | 2018-05-28 | 2019-12-06 | 东京毅力科创株式会社 | 对膜进行蚀刻的方法和等离子体处理装置 |
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