JP3167668B2 - 基板の分割方法 - Google Patents

基板の分割方法

Info

Publication number
JP3167668B2
JP3167668B2 JP2186298A JP2186298A JP3167668B2 JP 3167668 B2 JP3167668 B2 JP 3167668B2 JP 2186298 A JP2186298 A JP 2186298A JP 2186298 A JP2186298 A JP 2186298A JP 3167668 B2 JP3167668 B2 JP 3167668B2
Authority
JP
Japan
Prior art keywords
silicon
substrate
nitride
layer
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2186298A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10256193A (ja
Inventor
サージ・エル・ラダス
ポール・エス・マーティン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agilent Technologies Inc
Original Assignee
Agilent Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agilent Technologies Inc filed Critical Agilent Technologies Inc
Publication of JPH10256193A publication Critical patent/JPH10256193A/ja
Application granted granted Critical
Publication of JP3167668B2 publication Critical patent/JP3167668B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)
  • Led Devices (AREA)
  • Processing Of Stones Or Stones Resemblance Materials (AREA)
JP2186298A 1997-02-28 1998-02-03 基板の分割方法 Expired - Fee Related JP3167668B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US80873497A 1997-02-28 1997-02-28
US808,734 1997-02-28

Publications (2)

Publication Number Publication Date
JPH10256193A JPH10256193A (ja) 1998-09-25
JP3167668B2 true JP3167668B2 (ja) 2001-05-21

Family

ID=25199579

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2186298A Expired - Fee Related JP3167668B2 (ja) 1997-02-28 1998-02-03 基板の分割方法

Country Status (6)

Country Link
JP (1) JP3167668B2 (zh)
KR (1) KR19980070042A (zh)
CN (1) CN1192043A (zh)
DE (1) DE19753492A1 (zh)
GB (1) GB2322737A (zh)
TW (1) TW353202B (zh)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2298491C (en) 1997-07-25 2009-10-06 Nichia Chemical Industries, Ltd. Nitride semiconductor device
JP3770014B2 (ja) 1999-02-09 2006-04-26 日亜化学工業株式会社 窒化物半導体素子
US6711191B1 (en) 1999-03-04 2004-03-23 Nichia Corporation Nitride semiconductor laser device
US6350664B1 (en) 1999-09-02 2002-02-26 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method of manufacturing the same
JP2001110755A (ja) * 1999-10-04 2001-04-20 Tokyo Seimitsu Co Ltd 半導体チップ製造方法
JP3368876B2 (ja) 1999-11-05 2003-01-20 株式会社東京精密 半導体チップ製造方法
WO2001084640A1 (de) 2000-04-26 2001-11-08 Osram Opto Semiconductors Gmbh LUMINESZENZDIODENCHIP AUF DER BASIS VON GaN UND VERFAHREN ZUM HERSTELLEN EINES LUMINESZENZDIODENBAUELEMENTS
DE10026255A1 (de) * 2000-04-26 2001-11-08 Osram Opto Semiconductors Gmbh Lumineszenzdiosdenchip auf der Basis von GaN und Verfahren zum Herstellen eines Lumineszenzdiodenbauelements mit einem Lumineszenzdiodenchip auf der Basis von GaN
JP2003532298A (ja) 2000-04-26 2003-10-28 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツング 発光半導体素子
DE10051465A1 (de) 2000-10-17 2002-05-02 Osram Opto Semiconductors Gmbh Verfahren zur Herstellung eines Halbleiterbauelements auf GaN-Basis
TWI292227B (en) 2000-05-26 2008-01-01 Osram Opto Semiconductors Gmbh Light-emitting-dioed-chip with a light-emitting-epitaxy-layer-series based on gan
JP4710148B2 (ja) * 2001-02-23 2011-06-29 パナソニック株式会社 窒化物半導体チップの製造方法
TWI326274B (en) * 2005-07-20 2010-06-21 Sfa Engineering Corp Scribing apparatus and method, and multi-breaking system
KR100681828B1 (ko) * 2005-07-20 2007-02-12 주식회사 에스에프에이 멀티 절단 시스템
TWI362769B (en) 2008-05-09 2012-04-21 Univ Nat Chiao Tung Light emitting device and fabrication method therefor
CN101958383B (zh) * 2010-10-07 2012-07-11 安徽三安光电有限公司 一种倒装磷化铝镓铟发光二极管的制作方法
CN102837369B (zh) * 2012-09-18 2015-06-03 广东工业大学 一种绿激光划片蓝宝石的工艺方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2121455A1 (de) * 1971-04-30 1972-11-02 Siemens AG, 1000 Berlin u. 8000 München Verfahren zum Aufteilen von plattenförmigen Werkstücken
EP0613765B1 (de) * 1993-03-02 1999-12-15 CeramTec AG Innovative Ceramic Engineering Verfahren zum Herstellen von unterteilbaren Platten aus sprödem Material mit hoher Genauigkeit
US5418190A (en) * 1993-12-30 1995-05-23 At&T Corp. Method of fabrication for electro-optical devices

Also Published As

Publication number Publication date
GB9804385D0 (en) 1998-04-22
DE19753492A1 (de) 1998-09-03
JPH10256193A (ja) 1998-09-25
TW353202B (en) 1999-02-21
CN1192043A (zh) 1998-09-02
GB2322737A (en) 1998-09-02
KR19980070042A (ko) 1998-10-26

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