JP3167668B2 - Substrate splitting method - Google Patents
Substrate splitting methodInfo
- Publication number
- JP3167668B2 JP3167668B2 JP2186298A JP2186298A JP3167668B2 JP 3167668 B2 JP3167668 B2 JP 3167668B2 JP 2186298 A JP2186298 A JP 2186298A JP 2186298 A JP2186298 A JP 2186298A JP 3167668 B2 JP3167668 B2 JP 3167668B2
- Authority
- JP
- Japan
- Prior art keywords
- silicon
- substrate
- nitride
- layer
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000758 substrate Substances 0.000 title claims description 41
- 238000000034 method Methods 0.000 title claims description 33
- 239000011248 coating agent Substances 0.000 claims description 26
- 238000000576 coating method Methods 0.000 claims description 26
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 20
- 229910052594 sapphire Inorganic materials 0.000 claims description 12
- 239000010980 sapphire Substances 0.000 claims description 12
- 235000012239 silicon dioxide Nutrition 0.000 claims description 12
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 229910002601 GaN Inorganic materials 0.000 claims description 9
- 239000011521 glass Substances 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 229910005540 GaP Inorganic materials 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims description 5
- 239000010453 quartz Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 238000003776 cleavage reaction Methods 0.000 claims description 4
- 230000007017 scission Effects 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 238000012545 processing Methods 0.000 claims description 2
- 238000005520 cutting process Methods 0.000 description 6
- 238000000926 separation method Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 3
- 230000000977 initiatory effect Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- 239000002699 waste material Substances 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229960001716 benzalkonium Drugs 0.000 description 1
- CYDRXTMLKJDRQH-UHFFFAOYSA-N benzododecinium Chemical compound CCCCCCCCCCCC[N+](C)(C)CC1=CC=CC=C1 CYDRXTMLKJDRQH-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000012805 post-processing Methods 0.000 description 1
- 239000011029 spinel Substances 0.000 description 1
- 229910052596 spinel Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
- H01L21/3043—Making grooves, e.g. cutting
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Led Devices (AREA)
- Processing Of Stones Or Stones Resemblance Materials (AREA)
Description
【0001】[0001]
【発明の属する技術分野】本願発明は、半導体デバイス
の製造法に関し、詳細には、モノリシック基板上に成長
させたデバイスを分離する法に関する。The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for separating a device grown on a monolithic substrate.
【0002】[0002]
【発明の背景】ブルー/グリーン発光デバイスは、厚い
サファイヤ基板(約100−500μm厚で直径が50
−150mmの範囲にある円盤状基板ウェハである)の
上に成長させた六方晶の結晶対称性(ウルツァイト型)
を有する薄い(約1−10μmの)GaNベースの化合
物デバイス構造である。該デバイスは、一辺が典型的に
は200−500μmの方形形状であることが多い。そ
れ故、1つの基板上に多くの個別デバイスが近接して組
立てられることになる。GaNとサファイヤはダイヤモ
ンドに近い硬さであるため、またサファイヤの自然へき
開面はその表面に直角でないという理由から、デバイス
の分離(即ち、個々の″ダイ”への″ウェハ″の単離)
は、極めて困難である。従って、ウェハ中の単離破断面
は、滑らかもでもなく、平坦でもなく且つ垂直でもな
く、これらのことがデバイスの性能と信頼性に大きな影
響を及ぼす。BACKGROUND OF THE INVENTION Blue / green light emitting devices have been developed using thick sapphire substrates (approximately 100-500 μm thick and 50 mm diameter).
Hexagonal crystal symmetry (wurzite type) grown on a disc-shaped substrate wafer in the range of -150 mm)
Is a thin (about 1-10 μm) GaN-based compound device structure with The device, often a side are typically rectangular shape 200-500. Would therefore many individual devices on a single substrate are assembled in close proximity. Because GaN and sapphire are nearly as hard as diamond, and because the natural cleavage plane of sapphire is not perpendicular to its surface, device isolation (ie, isolation of the "wafer" into individual "dies").
Is extremely difficult. Thus, isolated fracture surface in the wafer, also smooth but rather, and neither the vertical nor flat, these things great influence on the performance and reliability of the device.
【0003】デバイスを分離するための1つの従来法
は、デバイスを鋸(ダイシングソー)で切断する方法で
ある。サファイヤとGaNベースの化合物はあまりにも
硬いので、鋸の刃は、小デバイスの切断には実際上使え
ないほど短寿命となる(典型的には直線で250cm以
下である)。加えて、鋸引きは、約150μm以上の広
い切り溝が必要で、鋸引き用の無駄を必要とする。鋸引
きはまた、過度のチッピングと望ましくないクラックを
引き起こし、それがデバイスの活性領域の中まで伝わっ
てその性能及び信頼性を劣化させる。[0003] One conventional method for separating devices is to cut the device with a saw (dicing saw). Because sapphire and GaN-based compounds are too hard, the saw blade has a life so short that it is practically unusable for cutting small devices (typically less than 250 cm in a straight line). In addition, sawing requires a wide kerf of about 150 μm or more, which requires waste for sawing. Sawing also causes excessive chipping and unwanted cracks, which propagate into the active area of the device, degrading its performance and reliability.
【0004】別の従来法は、ダイをレーザカットで切り
離す方法である。不運にも、サファイヤは極めて短いレ
ーザ放射波長(230nm未満)を要し、そのためレー
ザの使用で非常に高い熱を生ずる。そしてダイは望まし
くない熱膨張を起こす。その上、分離品質は、鋸引きで
得られたものと比べてもそれほど際だって優れてはいな
い。[0004] Another conventional method is a method to separate the die with a laser cut. Unfortunately, sapphire requires very short laser emission wavelengths (less than 230 nm), which produces very high heat with the use of lasers. The die then undergoes undesired thermal expansion. Moreover, the separation quality is not significantly better than that obtained by sawing.
【0005】さらに別の従来法、″罫書して破断″で
は、罫書線を用いてダイの分離域を定め、この線に沿っ
て罫書マークで始まる破断の伝播によってダイを分離す
るものである。この方法は、ダイ間の″通路″が50−
150μmのオーダであり、ウェハ上に広い地所を占
め、スループット及びコストの面では全く不適切であ
る。また、前述のような硬い表面では、罫書工具の有効
寿命が、典型的には、直線で500cmを下回る。[0005] Yet another conventional method, "scribe and break", uses a scribe line to define a die separation area and separates the dies along the line by propagation of the break beginning at the scribe mark. In this method, the "passage" between the dies is 50-
It is of the order of 150 μm, occupies a large area on the wafer, and is completely unsuitable in terms of throughput and cost. Also, with a hard surface as described above, the useful life of the scoring tool is typically less than 500 cm in a straight line.
【0006】[0006]
【発明が解決しようとする課題】前述の従来法は全て高
価な基板材料を浪費し且つ平滑度も不十分な破断面を生
ずる。コストのかかる、罫書困難な基板を効率よく用い
得る方法が望まれる。その方法が切断工具の寿命を延ば
すものであればさらにコスト及びスループット的に有益
であろう。最終的に、清浄で、平滑な、垂直の破断面を
生ずる方法によって、最終デバイスの性能と信頼性が改
善されるであろう。All of the above-mentioned conventional methods waste expensive substrate material and produce a fracture surface with insufficient smoothness. A method that can efficiently use a costly and difficult-to-scribe substrate is desired. It would be more cost and throughput beneficial if the method would extend the life of the cutting tool. Ultimately, methods that produce clean, smooth, vertical fracture surfaces will improve the performance and reliability of the final device.
【0007】同様の問題は、GaN基板(又はサファイ
ヤ以外の基板)上に成長されたGaNベースのデバイ
ス;平面パネルディスプレイの製造に用いるある種のガ
ラス;又はその他のガラス又は石英ベースのデバイス
(例えば、ウェハ結合型夜間可視系)のような、その他
のへき開困難な材料系のデバイスを分離しようとする時
に遭遇する。その他の問題系は、リン化ガリウム(Ga
P)又は化合物半導体のような、罫書が開始される基板
又はウェハ層がデバイスの他のいくつかの層とは異なっ
た材料系であるような、罫書困難な半導体である。な
お、「罫書困難」とは、基板を罫書して破断する場合
に、上記の課題を解決できるような罫書を行った状態と
するのが困難であるとの意味です。 [0007] A similar problem is that GaN-based devices grown on GaN substrates (or substrates other than sapphire); certain glasses used in the manufacture of flat panel displays; or other glass or quartz-based devices (eg, This is encountered when trying to separate other hard-to-cleavable material-based devices, such as wafer-attached night-visible systems. Other problem systems include gallium phosphide (Ga
Difficult semiconductors, such as P) or compound semiconductors, in which the substrate or wafer layer from which the scribing is initiated is a different material system than some other layers of the device. What
Note that "scribing difficult" is when the board is scored and broken
In addition, the state where the ruled line that can solve the above-mentioned problem was done
It is difficult to do.
【0008】[0008]
【課題を解決するための手段】本発明では、まずデバイ
ス表面を有する罫書困難な基板を、(例えば、ラッピン
グ、グラインディング、エッチング、リフトオフ、等の
ような処理によって)薄くして後段のへき開処理に適す
る厚さにする。基板のもう一方の面上には、誘電体又は
他の非延性材料の層(″被覆″)を成長させるか堆積す
る。According to the present invention, a difficult-to-scribe substrate having a device surface is first thinned (for example, by a process such as lapping, grinding, etching, lift-off, etc.) and a subsequent cleavage process is performed. To an appropriate thickness. On the other side of the substrate, a layer ("coating") of dielectric or other non-ductile material is grown or deposited.
【0009】この″被覆″面を罫書く時、″被覆″材料
は、罫書助長層の役割を演ずる。すなわち、基板より軟
らかく且つきれいな罫書線を付けられるよう被覆材料を
選択する。その厚さは、十分な破断伝播を生ずるよう最
適化される。任意選択の金属層を罫書助長層の上に載せ
る。この金属層は、切断工具を圧電気放電から遮蔽する
とともに、ダイの罫書及び分離によって生ずる熱を消散
させる働きがある。When scoring this "cover" surface, the "cover" material plays the role of a scribing aid layer. That is, the coating material is selected so that the scored line is softer and cleaner than the substrate. Its thickness is optimized to produce sufficient break propagation. An optional metal layer is placed over the scoring aid layer. This metal layer serves to shield the cutting tool from the piezoelectric discharge and to dissipate the heat generated by the scoring and separation of the die.
【0010】″被覆″表面に罫書をせずに、基板のもう
一方の面上に罫書を施す時は、″被覆″の厚さと硬さ
は、きれいな破断伝播を実現すべくその罫書表面を最適
の張力状態に保つよう選択する。任意選択の金属層を罫
書助長層の上に載せる。この金属層は、切断工具を圧電
気放電から遮蔽するとともに、ダイの罫書及び分離によ
って生ずる熱を消散させる働きがある。[0010] When scribing on the other side of the substrate without scribing on the "coating" surface, the thickness and hardness of the "coating" will optimize the scoring surface to achieve clean break propagation. To maintain tension at An optional metal layer is placed over the scoring aid layer. This metal layer serves to shield the cutting tool from the piezoelectric discharge and to dissipate the heat generated by the scoring and separation of the die.
【0011】[0011]
【発明の実施の形態】図1A−Cは、破断伝播が改善さ
れた本発明の一実施例のウェハの断面を図解したもので
ある。図1Aでは、誘電体層2を、サファイヤ又は窒化
ガリウム(GaN)又はリン化ガリウム(GaP)等の
罫書困難な基板4の薄膜化した裏面に成長させたもので
ある。図1Bでは、誘電性″被覆″をサファイヤ基板の
デバイス層4aの表面に堆積したものである。図1A、
図1Bのいずれにおいても、アルミニウムなどの任意選
択の金属層6を誘電体層2の上に堆積している。また図
1A、図1Bのいずれにおいても、罫書は薄膜化基板4
の最終的に金属を被覆した側で行う。任意選択の第二の
誘電体層と第二の金属層を前記誘電体層と金属層の堆積
された側の反対側に堆積してもよい(図示せず)。図1
Cでは、単一の誘電体層8を薄膜化した基板側に堆積さ
せる一方、罫書を未被覆のままのデバイス側で行う。1A-C illustrate a cross section of a wafer according to one embodiment of the present invention with improved rupture propagation. In FIG. 1A, a dielectric layer 2 is grown on a thinned back surface of a substrate 4 that is difficult to score, such as sapphire, gallium nitride (GaN), or gallium phosphide (GaP). In FIG. 1B, a dielectric "coating" is deposited on the surface of the device layer 4a of the sapphire substrate. FIG. 1A,
1B, an optional metal layer 6, such as aluminum, is deposited on the dielectric layer 2. In FIG. In each of FIGS. 1A and 1B, the scribe is made on the thinned substrate 4.
And finally on the side coated with metal . An optional second dielectric layer and a second metal layer may be deposited on the side opposite the deposited side of the dielectric and metal layers (not shown). FIG.
In C, a single dielectric layer 8 is deposited on the thinned substrate side, while scribing is performed on the uncoated device side.
【0012】罫書を″被覆″側で行う時はいつも、″被
覆″は罫書助長層の役割を演ずる。すなわち、被覆とし
ては、二酸化シリコン(SiO2)などのサファイヤよ
り軟らかく容易にへき開できる材料を選択する。結果と
して、″被覆″材料上の罫書線は、サファイヤ上より清
浄で且つ良好に定められる。綺麗な破断開始により、硬
い材料に渉り良好な破断伝播が達成される。加えて、そ
の破断は、綺麗な破断伝播に導く応力をウェハにかける
ことによってさらに助長される。結果として、罫書工具
の寿命は長くなり且つデバイス分離の歩留り改善及びデ
バイス組立コスト低減が達成される。Whenever a score is made on the "cover" side, the "cover" plays the role of a scribing aid layer. That is, a material that is softer than sapphire and can be easily cleaved, such as silicon dioxide (SiO 2 ), is selected as the coating. As a result, the score lines on the "coating" material are cleaner and better defined than on sapphire. With a good break initiation, good break propagation over hard materials is achieved. In addition, the fracture is further promoted by applying stresses to the wafer that lead to clean fracture propagation. As a result, the life of the scribing tool is extended, and the yield of device separation is improved and the device assembly cost is reduced.
【0013】任意選択の金属層6は、ダイ切断工具を滑
り易くさせて基板に及ぼす工具の衝撃を緩和し、且つ熱
を消散させる作用がある。切断処理によって生ずる熱
は、罫書品質を低下させる工具磨耗の一因となる。加え
て、この層は、やはり磨耗と磨損を増大させるであろう
圧電気放電から工具を遮蔽するよう作用する。The optional metal layer 6 has the effect of making the die cutting tool slippery, reducing the impact of the tool on the substrate and dissipating heat. The heat generated by the cutting process contributes to tool wear which reduces the score quality. In addition, this layer acts to shield the tool from piezoelectric discharges which would also increase wear and wear.
【0014】罫書助長層2は、窒化アルミニウム、アル
ミナ、窒化シリコン、シリコン・オキシ−ナイトライ
ド、又はそれに匹敵する誘電性又は非延性層であってよ
いが、酸化シリコン又は二酸化シリコンも望ましいもの
である。あるいは、罫書困難な基板4は、半導体、即
ち、GaP、シリコン、炭化シリコン、又はGaN、ス
ピネル、ガラス例えばG7、又は大きい石英板であって
もよい。The scribing aid layer 2 may be aluminum nitride, alumina, silicon nitride, silicon oxy-nitride, or a comparable dielectric or non-ductile layer, but silicon oxide or silicon dioxide is also desirable. . Alternatively, the difficult-to-scribe substrate 4 may be a semiconductor, i.e. GaP, silicon, silicon carbide, or GaN, spinel, glass such as G7, or a large quartz plate.
【0015】図2A及び図2Bは、本発明に従って実施
されるプロセスのフローチャートの例を示す。図2Aの
プロセスでは罫書が被覆側でおこなわれ、図2Bのプロ
セスでは罫書が被覆側とは反対側でおこなわれる。ステ
ップ10において、厚い基板上に薄いデバイス層を備え
た板すなわちウェハを組立てる。つぎに、ステップ20
においてウェハを処理して互いに繋がった多数のデバイ
スを形成するステップ30では、まずデバイス表面を有
する罫書困難な基板を、(例えば、ラッピング、グライ
ンディング、エッチング、リフトオフ、等のような処理
によって)薄くして後段のへき開処理に適する厚さにす
る。たとえば、基板の裏面をラップしてほとんどの材料
系に使える厚さである約50−150μmの厚さにす
る。ステップ30はステップ20とステップ40A、4
0Bの間におかれるのが典型的であるが、ステップ10
のあとステップ60A,60Bのまえのどこにおいても
良い。ステップ40A,40Bでは、典型的に5−10
00nm間の厚さを有する誘電体層を基板の所望の面上
に成長させる。その誘電体層は、スパッタリング、蒸
発、イオンビーム蒸着、化学的気相成長(CVD)、プ
ラスマ増強CVDによって、さらにはスピン・オン・ガ
ラスによって堆積させてよい。ステップ40Aでは、誘
電体層等の被覆は後工程の罫書線の品質を上げ、破断開
始を良好にするための適切な厚さと硬さを有する分割助
長層とされる。ステップ40Bでは、誘電体層等の被覆
は反対側でおこなわれる後工程の罫書線の品質を上げ、
破断開始を良好にするための適切な張力を生ずるように
適切な厚さと硬さを有する分割助長層とされる。ステッ
プ50A,50Bでは、任意選択の金属層を被罫書表面
上に堆積する。ステップ50Aでは金属層は被覆の上に
堆積され、ステップ50Bでは金属層は被覆がない側に
堆積される。該金属層は良好な展性と良好な導電性と良
好な熱伝導性とを有することが好ましい。ステップ60
A,60Bでは、ウェハ構造を罫書き、その後、その罫
書線に沿って破断して個別デバイスが得られる。ステッ
プ60Aでは被覆のある側を、ステップ60Bでは被覆
が存在しない側で罫書と破断が行われる。2A and 2B show an example of a flowchart of a process performed in accordance with the present invention. In the process of FIG. 2A, the scribe is made on the coated side, and in the process of FIG. 2B, the scribe is made on the side opposite to the coated side. In step 10, a plate or wafer with a thin device layer on a thick substrate is assembled. Next, step 20
In step 30 of processing the wafer at to form a large number of interconnected devices, a difficult scoring substrate having a device surface is first thinned (eg, by a process such as lapping, grinding, etching, lift-off, etc.). To a thickness suitable for the subsequent cleavage treatment. For example, to a thickness of about 50-150μm in thickness that used in most material systems by wrapping the rear face of the substrate. Step 30 consists of steps 20 and 40A, 4
0B, typically at step 10B.
After that, it may be anywhere before steps 60A and 60B. In steps 40A and 40B, typically 5-10
A dielectric layer having a thickness between 00 nm is grown on the desired surface of the substrate. The dielectric layer may be deposited by sputtering, evaporation, ion beam evaporation, chemical vapor deposition (CVD), plasma enhanced CVD, and even spin-on-glass. In step 40A, the coating of the dielectric layer or the like is formed into a division promoting layer having an appropriate thickness and hardness for improving the quality of the score line in the subsequent process and improving the onset of fracture. In step 40B, the coating of the dielectric layer or the like is performed on the opposite side to increase the quality of the post-processing score line,
The split promoting layer has an appropriate thickness and hardness so as to generate an appropriate tension for improving the onset of rupture. In steps 50A and 50B, an optional metal layer is deposited on the surface to be scored. In step 50A, a metal layer is deposited over the coating, and in step 50B, the metal layer is deposited on the uncoated side. The metal layer preferably has good malleability, good electrical conductivity and good thermal conductivity. Step 60
In A and 60B, the wafer structure is scribed and then broken along the scribe lines to obtain individual devices. In step 60A, scoring and breaking are performed on the side with the coating, and in step 60B, on the side without the coating.
【0016】誘電性又は非延性の層である被覆は、好ま
しくは、被罫書表面が引張られた状態になるようにその
選択表面上に堆積させる。これにより、綺麗な破断伝播
を促進し且つダイのエッジのチッピングが減りダイ間に
要する通路が縮小される。[0016] The coating, which is a dielectric or non-ductile layer, is preferably deposited on the selected surface such that the surface to be scored is in tension. This promotes clean break propagation and reduces die edge chipping and reduces the path required between the dies.
【0017】図2Aと図2Bに示したプロセス間の主な
る差異は、誘電性又は非延性層(″被覆″)の役割に関
してである。図2Aでは、(″被覆″)は比較的軟らか
く(例えば二酸化シリコン)且つ主として綺麗な罫書と
破断開始(罫書の容易化)を考慮したものである。そこ
で、罫書表面を適当な引張り状態におく被覆は二次的な
問題である。図2Bでは、(″被覆″)の主要な目的
は、破断開始後に最適の破断伝播ができるよう(破断の
容易化)反対側の罫書表面を適当な引張り状態におく被
覆である。この時は、罫書工具は材料に接触しない故、
その材料はかなり硬くてもよい(例えば窒化シリコ
ン)。The main difference between the processes shown in FIGS. 2A and 2B is in the role of the dielectric or non-ductile layer ("coating"). In FIG. 2A, ("coating") is relatively soft (eg, silicon dioxide) and is primarily intended for clean scoring and break initiation (simplification of scoring). Thus, coating to place the scribing surface in a suitable tension is a secondary problem. In FIG. 2B, the primary purpose of ("coating") is to coat the opposite scoring surface in an appropriate tension for optimal break propagation after break initiation (facilitation of breakage). At this time, since the scribing tool does not contact the material,
The material can be quite hard (eg, silicon nitride).
【0018】最後に、被罫書表面を比較的軟らかく、へ
き開し易い材料で被覆し且つ他面を比較的硬い材料で被
覆する被覆により、図2Aと図2Bに示したプロセスを
合併する被覆は可能であり;比較的軟らかい(″被
覆″)材料の及び比較的硬い(″被覆″)材料の厚さ
を、それぞれ、罫書開始(罫書の容易化)及び破断開始
(破断の容易化)に向くように最適化することもでき
る。Finally, a coating that combines the process shown in FIGS. 2A and 2B is possible by coating the surface to be scored with a relatively soft and easily cleavable material and coating the other surface with a relatively hard material. The thicknesses of the relatively soft ("coating") material and the relatively hard ("coating") material are oriented towards the start of scoring (easy scoring) and the onset of breaking (easy breaking), respectively. Can also be optimized.
【0019】以上、実施例に即して本発明を説明した
が、本発明の実施は上記に限定されるものではなく、以
下に本発明の実施態様を例示して本発明の実施に当たっ
ての参考し供する。 (実施態様1) 罫書困難な基板(30)を容易するステップと;罫書困
難な基板を薄膜化するステップと;罫書を施す面と非罫
書面とを有する、薄膜化した罫書困難な基板の第一の面
上に第一の非延性層を付けるステップ(40A、40
B)と;罫書困難な基板の罫書を施す面上に罫書線を罫
書くステップと;該罫書線に沿って基板を破断するステ
ップとを設けて成る罫書困難基板の分割方法。 (実施態様2) 罫書困難な基板が、サファイヤ、シリコン(ケイ素)、
炭化シリコン、窒化ガリウム、リン化ガリウム、ガラ
ス、及び石英から成る群から選択されることを特徴とす
る実施態様1記載の罫書困難基板の分割方法。Although the present invention has been described with reference to the embodiments, the embodiments of the present invention are not limited to the above, and the embodiments of the present invention will be exemplified below for reference. Serve. (Embodiment 1) A step of facilitating a substrate that is difficult to score, a step of thinning the substrate that is difficult to score, and a step of thinning the substrate that is difficult to score, having a surface to be scribed and a non-scribed surface. Applying a first non-ductile layer on one side (40A, 40A);
B); a step of scribing a scribing line on the surface of the board on which scribing is difficult, and a step of breaking the board along the scribing line; (Embodiment 2) Substrates which are difficult to score are sapphire, silicon (silicon),
Silicon carbide, gallium nitride, gallium phosphide, glass, and scribed difficult substrate dividing method embodiment 1, wherein the benzalkonium selected from the group consisting of quartz.
【0020】(実施態様3) 第一の非延性層が、窒化アルミニウム、アルミナ、酸化
シリコン、二酸化シリコン、窒化シリコン、及びシリコ
ン・オキシ−ナイトライドから成る群から選択される材
料からなる被覆であることを特徴とする実施態様1記載
の罫書困難基板の分割方法。 (実施態様4) さらに、前記罫書くステップに先立ち、罫書困難な基板
の罫書を施す面に金属層を上張りするステップ(40
A、40B)を含む実施態様1記載の罫書困難基板の分
割方法。 (実施態様5) さらに、前記罫書くステップに先立ち、罫書困難な基板
の前記第一の面に対する第二の面上に第二の非延性層を
付けるステップ(40A、40B)を含む実施態様1記
載の罫書困難基板の分割方法。(Embodiment 3) The first non-ductile layer is a coating made of a material selected from the group consisting of aluminum nitride, alumina, silicon oxide, silicon dioxide, silicon nitride, and silicon oxy-nitride. The method for dividing a substrate having difficulty in scoring according to the first embodiment. (Embodiment 4) Further, prior to the step of scribing, a step (40) of overlaying a metal layer on the surface of the substrate on which scoring is difficult to be scored.
A, 40B). (Embodiment 5) An embodiment 1 further comprising a step (40A, 40B) of applying a second non-ductile layer on a second surface of the substrate that is difficult to score, on the second surface with respect to the first surface, prior to the scribing step. How to divide the hard-to-scribe board described.
【0021】(実施態様6) 第二の非延性層が、窒化アルミニウム、アルミナ、酸化
シリコン、二酸化シリコン、窒化シリコン、及びシリコ
ン・オキシ−ナイトライドから成る群から選択される材
料から成る被覆であることを特徴とする実施態様5記載
の罫書困難基板の分割方法。 (実施態様7) さらに、前記罫書くステップに先立ち、罫書困難な基板
の罫書を施す面に金属層を上張りするステップ(50
A、50B)を含む実施態様6記載の罫書困難基板の分
割方法。Embodiment 6 The second non-ductile layer is a coating made of a material selected from the group consisting of aluminum nitride, alumina, silicon oxide, silicon dioxide, silicon nitride, and silicon oxy-nitride. The method for dividing a substrate having difficulty in scoring according to the fifth embodiment, characterized in that: (Embodiment 7) Further, prior to the step of scoring, a step (50) of overlaying a metal layer on the surface of the substrate on which scoring is difficult to be scored.
A, 50B).
【図1A】罫書及び破断が改善された本発明の第一の実
施例に係るウェハの断面図である。FIG. 1A is a cross-sectional view of a wafer according to a first embodiment of the present invention with improved scoring and breaking.
【図1B】罫書及び破断が改善された本発明の第二の実
施例に係るウェハの断面図である。FIG. 1B is a cross-sectional view of a wafer according to a second embodiment of the present invention with improved scribing and breakage.
【図1C】罫書及び破断が改善された本発明の第三の実
施例に係るウェハの断面図である。FIG. 1C is a cross-sectional view of a wafer according to a third embodiment of the present invention with improved scribing and breakage.
【図2A】本願発明の第一のプロセスのフローチャート
である。FIG. 2A is a flowchart of a first process of the present invention.
【図2B】本願発明の第二のプロセスのフローチャート
である。FIG. 2B is a flowchart of a second process of the present invention.
2 誘電体層 4 罫書困難な基板 4aデバイス層 6 金属層 8 誘電体層 2 Dielectric layer 4 Substrate difficult to score 4a Device layer 6 Metal layer 8 Dielectric layer
───────────────────────────────────────────────────── フロントページの続き (73)特許権者 399117121 395 Page Mill Road Palo Alto,Californ ia U.S.A. (56)参考文献 特開 平5−166923(JP,A) 特開 昭62−54938(JP,A) 特開 昭61−251051(JP,A) 特開 昭61−251050(JP,A) 特開 昭60−253241(JP,A) 特開 昭55−86133(JP,A) 特開 昭54−140460(JP,A) 実開 平2−116739(JP,U) 実開 昭58−83143(JP,U) (58)調査した分野(Int.Cl.7,DB名) H01L 21/301 ──────────────────────────────────────────────────続 き Continued on the front page (73) Patent owner 399117121 395 Page Mill Road Palo Alto, California U.S.A. S. A. (56) References JP-A-5-166923 (JP, A) JP-A-62-54938 (JP, A) JP-A-61-251051 (JP, A) JP-A-61-251050 (JP, A) JP-A-60-253241 (JP, A) JP-A-55-86133 (JP, A) JP-A-54-140460 (JP, A) JP-A-2-116739 (JP, U) JP-A 58-86 83143 (JP, U) (58) Field surveyed (Int. Cl. 7 , DB name) H01L 21/301
Claims (7)
化するステップと; 罫書を施す面と非罫書面とを有する、薄膜化した前記基
板の第一の前記面上に第一の前記面と前記基板とに応じ
て厚さと硬さを選択した第一の非延性層を付けるステッ
プと;前記基板の罫書を施す面に金属層を上張りするステップ
と; 前記金属層を上張りした前記 罫書を施す面上に罫書線を
罫書くステップと; 該罫書線に沿って基板を破断するステップと; を設けて成る基板の分割方法。1. A step and providing a base plate; step and thinning to a thickness suitable to board the cleavage processing of the substrate; and a performing scribed surface and Hikei writing the obtained by thinning a method applying a first non-ductile layer selected thickness and hardness according to the first said surface and front Kimoto plate on a first of said surfaces of the base <br/>plate; scribed in the substrate Step of overlaying a metal layer on the surface to be treated
When; steps and breaking the substrate along the該罫document line; division method adult Ru board provided steps and which scribed a scribed line on a surface to be the scribe that overlay the metal layer.
シリコン、窒化ガリウム、リン化ガリウム、ガラス、及
び石英から成る群から選択されることを特徴とする請求
項1記載の基板の分割方法。Wherein said substrate is sapphire, silicon, silicon carbide, gallium nitride, a method of dividing gallium phosphide, glass, and board according to claim 1, characterized in that it is selected from the group consisting of quartz.
ルミナ、酸化シリコン、二酸化シリコン、窒化シリコ
ン、及びシリコン・オキシ−ナイトライドから成る群か
ら選択される材料からなる被覆であることを特徴とする
請求項1記載の基板の分割方法。3. The method of claim 1, wherein the first non-ductile layer is a coating comprising a material selected from the group consisting of aluminum nitride, alumina, silicon oxide, silicon dioxide, silicon nitride, and silicon oxy-nitride. dividing method based board according to claim 1 wherein.
に先立ち、前記基板の第一の前記面に対する第二の前記
面上に第二の非延性層を付けるステップを含む請求項1
記載の基板の分割方法。4. The method according to claim 1, further comprising the step of applying a second non-ductile layer on a second said surface relative to said first surface of said substrate prior to said step of overlaying said metal layer.
Board dividing method according.
ルミナ、酸化シリコン、二酸化シリコン、窒化シリコ
ン、及びシリコン・オキシ−ナイトライドから成る群か
ら選択される材料から成る被覆であることを特徴とする
請求項4記載の基板の分割方法。5. The method of claim 1, wherein the second non-ductile layer is a coating comprising a material selected from the group consisting of aluminum nitride, alumina, silicon oxide, silicon dioxide, silicon nitride, and silicon oxy-nitride. dividing method based board according to claim 4,.
記基板の非罫書面に金属層を上張りするステップを含む
請求項5記載の基板の分割方法。6. Furthermore, prior to the ruffled writing step, before
Dividing method according to claim 5, wherein the base plate including a step of overlay metal layer to the non-scribed surface of serial board.
化ガリウム、リン化ガリウム、ガラス、及び石英から成
る群から選択されることを特徴とする請求項1記載の基
板の分割方法。Wherein said substrate is silicon, silicon carbide, gallium nitride, gallium phosphide, glass, and the division of the group <br/> board according to claim 1, wherein a is selected from the group consisting of quartz Method.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US80873497A | 1997-02-28 | 1997-02-28 | |
US808,734 | 1997-02-28 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10256193A JPH10256193A (en) | 1998-09-25 |
JP3167668B2 true JP3167668B2 (en) | 2001-05-21 |
Family
ID=25199579
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2186298A Expired - Fee Related JP3167668B2 (en) | 1997-02-28 | 1998-02-03 | Substrate splitting method |
Country Status (6)
Country | Link |
---|---|
JP (1) | JP3167668B2 (en) |
KR (1) | KR19980070042A (en) |
CN (1) | CN1192043A (en) |
DE (1) | DE19753492A1 (en) |
GB (1) | GB2322737A (en) |
TW (1) | TW353202B (en) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU747260B2 (en) | 1997-07-25 | 2002-05-09 | Nichia Chemical Industries, Ltd. | Nitride semiconductor device |
JP3770014B2 (en) | 1999-02-09 | 2006-04-26 | 日亜化学工業株式会社 | Nitride semiconductor device |
EP1168539B1 (en) | 1999-03-04 | 2009-12-16 | Nichia Corporation | Nitride semiconductor laser device |
US6350664B1 (en) * | 1999-09-02 | 2002-02-26 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP2001110755A (en) * | 1999-10-04 | 2001-04-20 | Tokyo Seimitsu Co Ltd | Method of manufacturing semiconductor chip |
JP3368876B2 (en) | 1999-11-05 | 2003-01-20 | 株式会社東京精密 | Semiconductor chip manufacturing method |
CN1292494C (en) | 2000-04-26 | 2006-12-27 | 奥斯兰姆奥普托半导体有限责任公司 | Radiation-emitting semiconductor element and method for producing same |
US7319247B2 (en) | 2000-04-26 | 2008-01-15 | Osram Gmbh | Light emitting-diode chip and a method for producing same |
DE10051465A1 (en) | 2000-10-17 | 2002-05-02 | Osram Opto Semiconductors Gmbh | Method for producing a GaN-based semiconductor component |
DE10026255A1 (en) * | 2000-04-26 | 2001-11-08 | Osram Opto Semiconductors Gmbh | Radiation-emitting semiconductor element has a semiconductor body formed by a stack of different semiconductor layers based on gallium nitride |
TWI289944B (en) | 2000-05-26 | 2007-11-11 | Osram Opto Semiconductors Gmbh | Light-emitting-diode-element with a light-emitting-diode-chip |
JP4710148B2 (en) * | 2001-02-23 | 2011-06-29 | パナソニック株式会社 | Manufacturing method of nitride semiconductor chip |
KR100681828B1 (en) * | 2005-07-20 | 2007-02-12 | 주식회사 에스에프에이 | Multi braking system |
TWI326274B (en) * | 2005-07-20 | 2010-06-21 | Sfa Engineering Corp | Scribing apparatus and method, and multi-breaking system |
TWI362769B (en) | 2008-05-09 | 2012-04-21 | Univ Nat Chiao Tung | Light emitting device and fabrication method therefor |
CN101958383B (en) * | 2010-10-07 | 2012-07-11 | 安徽三安光电有限公司 | Manufacturing method of inversed AlGaInP light emitting diode |
CN102837369B (en) * | 2012-09-18 | 2015-06-03 | 广东工业大学 | Process method for green laser scribing sapphire |
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DE2121455A1 (en) * | 1971-04-30 | 1972-11-02 | Siemens AG, 1000 Berlin u. 8000 München | Method for dividing plate-shaped workpieces |
EP0613765B1 (en) * | 1993-03-02 | 1999-12-15 | CeramTec AG Innovative Ceramic Engineering | Method for the manufacture of subdividable tiles from a brittle material |
US5418190A (en) * | 1993-12-30 | 1995-05-23 | At&T Corp. | Method of fabrication for electro-optical devices |
-
1997
- 1997-10-22 TW TW086115595A patent/TW353202B/en active
- 1997-10-27 KR KR1019970055213A patent/KR19980070042A/en not_active Application Discontinuation
- 1997-12-02 DE DE19753492A patent/DE19753492A1/en not_active Withdrawn
- 1997-12-03 CN CN97125355A patent/CN1192043A/en active Pending
-
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- 1998-02-03 JP JP2186298A patent/JP3167668B2/en not_active Expired - Fee Related
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GB9804385D0 (en) | 1998-04-22 |
TW353202B (en) | 1999-02-21 |
CN1192043A (en) | 1998-09-02 |
JPH10256193A (en) | 1998-09-25 |
DE19753492A1 (en) | 1998-09-03 |
KR19980070042A (en) | 1998-10-26 |
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