JP2867138B2 - 半導体装置及び製造方法 - Google Patents

半導体装置及び製造方法

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Publication number
JP2867138B2
JP2867138B2 JP591888A JP591888A JP2867138B2 JP 2867138 B2 JP2867138 B2 JP 2867138B2 JP 591888 A JP591888 A JP 591888A JP 591888 A JP591888 A JP 591888A JP 2867138 B2 JP2867138 B2 JP 2867138B2
Authority
JP
Japan
Prior art keywords
semiconductor device
dicing
pad electrode
wiring
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP591888A
Other languages
English (en)
Other versions
JPH01186652A (ja
Inventor
肇 奈良
次視 今野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP591888A priority Critical patent/JP2867138B2/ja
Publication of JPH01186652A publication Critical patent/JPH01186652A/ja
Application granted granted Critical
Publication of JP2867138B2 publication Critical patent/JP2867138B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05624—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に関し、特に半導体基板のスクラ
イブ部分における配線、及びPAD電極構造に関する。
〔従来の技術〕
従来のスクライブ部分の配線及びPAD電極は、その内
部がパターニングされていない、一面に金属あるいは、
金属合金で構成された構造のものであった。
〔発明が解決しようとする課題〕
しかし、前述の従来技術では、ダイシングを実施する
事により、金属あるいは金属合金がめくれ上がり、実装
工程におけるボンディングワイヤー等の配線材料と接触
する事で不良となる問題点があった。
本発明はこの様な問題点を解決するもので、その目的
とする所は、金属あるいは金属合金のめくれ上がりであ
るバリを低減するようなスクライブ上の配線及びPAD電
極構造を提供することにある。
〔課題を解決するための手段〕
本発明は、半導体基板上にスクライブ領域を有する半
導体装置において、前記スクライブ領域に設けられた金
属パッドは、前貴金属パッド内部に設けられた短冊状の
スリットを有し、前記スリットは、ダイシング方向に対
して平行にのみ設けられており、ダイシング後の前記パ
ッド電極の残部が複数個に分割されないことを特徴とす
る。また、半導体基板上にスクライブ領域を有する半導
体装置の製造方法において、前記スクライブ領域に配線
もしくは、パッド電極をエッチングすると同時に前記配
線もしくは前記パッド電極の内部にダイシング方向に対
して平行方向にのみ設けられた短冊状のスリットをパタ
ーニングすることを特徴とする。
〔実 施 例〕
以下、本発明について、実施例に基づき説明する。
第１図は半導体基板のスクライブ部分に形成された本
発明の構造を使用したPAD電極の一実施例である。まず
半導体素子が形成されると同時にモニター用半導体素子
が形成される。
次いで前記モニター用半導体素子の特性を確認するた
めに形成されるAL配線及びPAD電極は、第１図に示すよ
うに、ダイシング方向に平行なALのない部分ができるよ
うなパターンを含めた形で同時に形成する。
次いで前記PAD電極を使用して特性が良好と確認され
た後、ダイシング工程に流動される。
次いで前記ダイシング工程を終了し、外部電極とチッ
プ内ボンディングPADがボンディングワイヤで結線され
た時、第２図に示す様にスクライブPADのバリがボンデ
ィングワイヤに接触する事無く、実装工程を終了する。
〔発明の効果〕
上述の如く、ダイシング工程によって生じた、スクラ
イブ部分のPAD電極片であるバリが小さくなる事によ
り、実装工程に於けるベンディングワイヤとの接触が防
止出来、ボンディグ不良が低減される。又金属をダイシ
ングする事により寿命が短くなるダイシングソーの耐久
性も向上される事になる。
【図面の簡単な説明】
第１図は本発明の半導体装置の配線及びPAD電極構造の
一実施例を示す図である。 第２図は本発明の半導体装置の配線又はPAD電極をダイ
シングした後、実装工程におけるボンディングを終了し
た一実施例を示す図である。 １……スクライブ領域内PAD電極 ２……電極材料のない部分 ３……チップ内ボンディングPAD電極 ４……ボンディグワイヤ ５……ダイシング後のスクライブ領域内PADのバリ

Claims (2)

    (57)【特許請求の範囲】
  1. 【請求項１】半導体基板上にスクライブ領域を有する半
    導体装置において、前記スクライブ領域に設けられた金
    属パッドは、前貴金属パッド内部に設けられた短冊状の
    スリットを有し、前記スリットは、ダイシング方向に対
    して平行にのみ設けられており、ダイシング後の前記パ
    ッド電極の残部が複数個に分割されないことを特徴とす
    る半導体装置。
  2. 【請求項２】半導体基板上にスクライブ領域を有する半
    導体装置の製造方法において、前記スクライブ領域に配
    線もしくは、パッド電極をエッチングすると同時に前記
    配線もしくは前記パッド電極の内部にダイシング方向に
    対して平行方向にのみ設けられた短冊状のスリットをパ
    ターニングすることを特徴とする半導体装置の製造方
    法。
JP591888A 1988-01-14 1988-01-14 半導体装置及び製造方法 Expired - Lifetime JP2867138B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP591888A JP2867138B2 (ja) 1988-01-14 1988-01-14 半導体装置及び製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP591888A JP2867138B2 (ja) 1988-01-14 1988-01-14 半導体装置及び製造方法

Publications (2)

Publication Number Publication Date
JPH01186652A JPH01186652A (ja) 1989-07-26
JP2867138B2 true JP2867138B2 (ja) 1999-03-08

Family

ID=11624273

Family Applications (1)

Application Number Title Priority Date Filing Date
JP591888A Expired - Lifetime JP2867138B2 (ja) 1988-01-14 1988-01-14 半導体装置及び製造方法

Country Status (1)

Country Link
JP (1) JP2867138B2 (ja)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03139862A (ja) * 1989-10-25 1991-06-14 Fujitsu Ltd 半導体装置
JP6095523B2 (ja) * 2013-08-28 2017-03-15 三菱電機株式会社 半導体ウエハ

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0514513Y2 (ja) * 1987-01-21 1993-04-19

Also Published As

Publication number Publication date
JPH01186652A (ja) 1989-07-26

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