JP2680801B2 - 集積装置を製造するための半導体材料のウェハ、およびその製造方法 - Google Patents

集積装置を製造するための半導体材料のウェハ、およびその製造方法

Info

Publication number
JP2680801B2
JP2680801B2 JP7327021A JP32702195A JP2680801B2 JP 2680801 B2 JP2680801 B2 JP 2680801B2 JP 7327021 A JP7327021 A JP 7327021A JP 32702195 A JP32702195 A JP 32702195A JP 2680801 B2 JP2680801 B2 JP 2680801B2
Authority
JP
Japan
Prior art keywords
layer
silicon
wafer
insulating layer
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP7327021A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0927604A (ja
Inventor
ブルーノ・ムラーリ
フラーヴィオ・ヴィッラ
ウバルド・マストロマッテオ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Thomson Microelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics SRL filed Critical SGS Thomson Microelectronics SRL
Publication of JPH0927604A publication Critical patent/JPH0927604A/ja
Application granted granted Critical
Publication of JP2680801B2 publication Critical patent/JP2680801B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding

Landscapes

  • Recrystallisation Techniques (AREA)
  • Element Separation (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
JP7327021A 1994-10-13 1995-12-15 集積装置を製造するための半導体材料のウェハ、およびその製造方法 Expired - Fee Related JP2680801B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT94TO000818A IT1268123B1 (it) 1994-10-13 1994-10-13 Fetta di materiale semiconduttore per la fabbricazione di dispositivi integrati e procedimento per la sua fabbricazione.
EP94830577.6 1994-12-15

Publications (2)

Publication Number Publication Date
JPH0927604A JPH0927604A (ja) 1997-01-28
JP2680801B2 true JP2680801B2 (ja) 1997-11-19

Family

ID=11412833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7327021A Expired - Fee Related JP2680801B2 (ja) 1994-10-13 1995-12-15 集積装置を製造するための半導体材料のウェハ、およびその製造方法

Country Status (4)

Country Link
US (1) US5855693A (esLanguage)
EP (1) EP0707338A2 (esLanguage)
JP (1) JP2680801B2 (esLanguage)
IT (1) IT1268123B1 (esLanguage)

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EP0720223B1 (en) * 1994-12-30 2003-03-26 STMicroelectronics S.r.l. Process for the production of a semiconductor device having better interface adhesion between dielectric layers
US6045625A (en) * 1996-12-06 2000-04-04 Texas Instruments Incorporated Buried oxide with a thermal expansion matching layer for SOI
FR2767605B1 (fr) * 1997-08-25 2001-05-11 Gec Alsthom Transport Sa Circuit integre de puissance, procede de fabrication d'un tel circuit et convertisseur incluant un tel circuit
US6194290B1 (en) * 1998-03-09 2001-02-27 Intersil Corporation Methods for making semiconductor devices by low temperature direct bonding
US20020089016A1 (en) 1998-07-10 2002-07-11 Jean-Pierre Joly Thin layer semi-conductor structure comprising a heat distribution layer
FR2781082B1 (fr) * 1998-07-10 2002-09-20 Commissariat Energie Atomique Structure semiconductrice en couche mince comportant une couche de repartition de chaleur
US6320206B1 (en) * 1999-02-05 2001-11-20 Lumileds Lighting, U.S., Llc Light emitting devices having wafer bonded aluminum gallium indium nitride structures and mirror stacks
US6500694B1 (en) * 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6166411A (en) * 1999-10-25 2000-12-26 Advanced Micro Devices, Inc. Heat removal from SOI devices by using metal substrates
US6552395B1 (en) * 2000-01-03 2003-04-22 Advanced Micro Devices, Inc. Higher thermal conductivity glass for SOI heat removal
US6476446B2 (en) 2000-01-03 2002-11-05 Advanced Micro Devices, Inc. Heat removal by removal of buried oxide in isolation areas
US6613643B1 (en) 2000-01-28 2003-09-02 Advanced Micro Devices, Inc. Structure, and a method of realizing, for efficient heat removal on SOI
US6635552B1 (en) 2000-06-12 2003-10-21 Micron Technology, Inc. Methods of forming semiconductor constructions
DE60125952T2 (de) * 2000-08-16 2007-08-02 Massachusetts Institute Of Technology, Cambridge Verfahren für die herstellung eines halbleiterartikels mittels graduellem epitaktischen wachsen
US6429070B1 (en) 2000-08-30 2002-08-06 Micron Technology, Inc. DRAM cell constructions, and methods of forming DRAM cells
US6940089B2 (en) * 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US6717212B2 (en) * 2001-06-12 2004-04-06 Advanced Micro Devices, Inc. Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure
US6995430B2 (en) * 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20030227057A1 (en) * 2002-06-07 2003-12-11 Lochtefeld Anthony J. Strained-semiconductor-on-insulator device structures
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US7608927B2 (en) 2002-08-29 2009-10-27 Micron Technology, Inc. Localized biasing for silicon on insulator structures
US6989314B2 (en) * 2003-02-12 2006-01-24 S.O.I.Tec Silicon On Insulator Technologies S.A. Semiconductor structure and method of making same
FR2851079B1 (fr) * 2003-02-12 2005-08-26 Soitec Silicon On Insulator Structure semi-conductrice sur substrat a forte rugosite
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
DE10326578B4 (de) 2003-06-12 2006-01-19 Siltronic Ag Verfahren zur Herstellung einer SOI-Scheibe
DE102004053016A1 (de) * 2004-11-03 2006-05-04 Atmel Germany Gmbh Halbleiteranordnung und Verfahren zur Herstellung einer Halbleiteranordnung
JP2006173349A (ja) * 2004-12-15 2006-06-29 Sony Corp 固体撮像素子の製造方法及び固体撮像素子
JP2007012897A (ja) * 2005-06-30 2007-01-18 Nec Electronics Corp 半導体装置およびその製造方法
JP5368996B2 (ja) * 2006-12-26 2013-12-18 ソイテック 半導体オンインシュレータ構造体を製造する方法
US7781256B2 (en) * 2007-05-31 2010-08-24 Chien-Min Sung Semiconductor-on-diamond devices and associated methods
US9466719B2 (en) 2009-07-15 2016-10-11 Qualcomm Incorporated Semiconductor-on-insulator with back side strain topology
TWI538173B (zh) * 2009-07-15 2016-06-11 瑟藍納半導體美國股份有限公司 具背側散熱能力之絕緣體上半導體結構、自絕緣體上半導體元件進行散熱之方法及製造具有絕緣體上半導體晶圓之積體電路之方法
US9390974B2 (en) 2012-12-21 2016-07-12 Qualcomm Incorporated Back-to-back stacked integrated circuit assembly and method of making
GB2483702A (en) * 2010-09-17 2012-03-21 Ge Aviat Systems Ltd Method for the manufacture of a Silicon Carbide, Silicon Oxide interface having reduced interfacial carbon gettering
FR2967812B1 (fr) * 2010-11-19 2016-06-10 S O I Tec Silicon On Insulator Tech Dispositif electronique pour applications radiofrequence ou de puissance et procede de fabrication d'un tel dispositif
US9142448B2 (en) * 2011-11-04 2015-09-22 The Silanna Group Pty Ltd Method of producing a silicon-on-insulator article
WO2013067572A1 (en) * 2011-11-07 2013-05-16 The Silanna Group Pty Ltd A semiconductor-on-insulator structure and process for producing same
US9425248B2 (en) 2011-12-22 2016-08-23 Shin-Etsu Chemical Co., Ltd. Composite substrate
US8741739B2 (en) 2012-01-03 2014-06-03 International Business Machines Corporation High resistivity silicon-on-insulator substrate and method of forming
US9231063B2 (en) 2014-02-24 2016-01-05 International Business Machines Corporation Boron rich nitride cap for total ionizing dose mitigation in SOI devices
JP6206786B2 (ja) * 2014-07-10 2017-10-04 株式会社サイコックス 半導体基板および半導体基板の製造方法
CN107548521A (zh) * 2015-02-18 2018-01-05 华威大学 功率半导体器件
FR3079662B1 (fr) * 2018-03-30 2020-02-28 Soitec Substrat pour applications radiofrequences et procede de fabrication associe
WO2022094587A1 (en) 2020-10-29 2022-05-05 Invensas Bonding Technologies, Inc. Direct bonding methods and structures

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0665210B2 (ja) * 1985-04-17 1994-08-22 日本電気株式会社 基板の製造方法
SE465492B (sv) * 1990-01-24 1991-09-16 Asea Brown Boveri Halvledarkomponent innehaallande ett diamantskikt som aer anordnat mellan ett substrat och ett aktivt skikt och foerfarande foer dess framstaellning
WO1993001617A1 (en) * 1991-07-08 1993-01-21 Asea Brown Boveri Ab Method for the manufacture of a semiconductor component
US5276338A (en) * 1992-05-15 1994-01-04 International Business Machines Corporation Bonded wafer structure having a buried insulation layer
US5413952A (en) * 1994-02-02 1995-05-09 Motorola, Inc. Direct wafer bonded structure method of making

Also Published As

Publication number Publication date
ITTO940818A0 (it) 1994-10-13
ITTO940818A1 (it) 1996-04-13
EP0707338A3 (esLanguage) 1996-05-15
JPH0927604A (ja) 1997-01-28
US5855693A (en) 1999-01-05
IT1268123B1 (it) 1997-02-20
EP0707338A2 (en) 1996-04-17

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