CN107548521A - 功率半导体器件 - Google Patents

功率半导体器件 Download PDF

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CN107548521A
CN107548521A CN201580076511.4A CN201580076511A CN107548521A CN 107548521 A CN107548521 A CN 107548521A CN 201580076511 A CN201580076511 A CN 201580076511A CN 107548521 A CN107548521 A CN 107548521A
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silicon layer
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P·甘蒙
C·W·陈
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University of Warwick
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Abstract

描述了功率半导体器件。所述器件包括碳化硅衬底(2)以及具有不大于5μm的厚度tsi的单晶硅层(3)，单晶硅层(3)直接设置在所述衬底上或直接设置在具有不大于100nm的厚度的界面层(22；图2)上的，所述界面层直接设置在所述衬底上。所述器件包括横向晶体管(1)，例如横向扩散金属氧化物半导体(LDMOS)晶体管或横向绝缘栅双极晶体管(LIGBT)，其包括设置在所述单晶硅层中的第一和第二触点(151、152)横向间隔的接触区。

Description

功率半导体器件
技术领域
本发明涉及一种功率半导体器件，特别是一种碳化硅上硅(silicon-on-silicon)半导体器件。
背景技术
能够在恶劣环境和/或高温(例如>300℃)下运行的半导体器件在广泛领域中受到极大关注，包括(但不限于)石油和天然气勘探、航空航天、运输和可再生能源。
然而，高温趋于对现有的硅基器件具有不利影响。当环境温度升高到300℃及以上时，p-n结漏电流呈指数增加，并且漂移电阻和沟道电阻线性增加，导致功率损耗增加，并且导致由于自热引起的较大的热失控敏感性。功率半导体器件，例如绝缘栅双极晶体管(IGBT)和金属氧化物半导体场效应晶体管(MOSFET)特别容易受到损害，因为由于导电损耗和开关损耗引起的自热效应可能导致高的结壳(junction-to-case)温度。
碳化硅(SiC)半导体器件在高达300℃和300℃以上是稳定的，并且由于碳化硅具有高热导率(硅的热导率的三倍)和极低的本征载流子浓度，而不易于自热。然而，SiC/SiO2界面倾向于经受差的沟道迁移率，这导致非常高的沟道电阻。因此，硅基器件倾向于在低于300℃的温度下的低电压至中等电压应用(即低于600V)中使用。事实上，低电压至中等电压应用最常用于垂直的体硅器件，例如(按照额定电压排序)MOSFET、超结MOSFET和IGBT。
已经在具有厚的掩埋氧化物(即二氧化硅)的厚膜绝缘体上硅(SOI)中实现了呈现出高达600V及以上的阻断电压的横向功率MOSFET。这种类型的器件具有这样的优点：其可以在同一衬底上支持电源和逻辑电路，而使用掩埋氧化物来隔离电路的不同部分。然而，这种布置并未被广泛采用，部分上由于较高的加工成本，但主要是因为差的热性能：掩埋氧化物不仅是电绝缘的，而且是隔热的。所以，没有有效地去除由欧姆损耗和器件开关导致的热量。因此，即使在低环境温度下，结壳温度(即有源半导体区和周围环境之间的温度差)也可能超过100℃。然而，在恶劣环境中，环境温度可能超过200℃。
尽管已经针对开发硅衬底上三阶(three-step)立方碳化硅(3C-SiC)器件做出相当大的努力，但是相对较少的工作深入研究涉及碳化硅衬底上硅的器件。
如以下所描述的，例如F.Udrea等：“Silicon/Oxide/Silicon Carbide(SiOSiC)-ANew Approach to High-Voltage，High-Frequency Integrated Circuits”，MaterialsScience Forum，第389-393卷，第1255页(2002)和S.G.Whipple“Demonstration of HybridSilicon-on-Silicon Carbide Wafers and Electrical Test Structures withImproved Thermal Performance”，MRS Proceedings，第911卷(2006)，已经制造了其中硅结合到氧化的碳化硅衬底上的结构。当器件断开时，引入氧化物层可以有助于减少通过衬底的泄漏，更好地隔离功率器件并且使结合过程更容易。然而，这种途径重新引入自热效应。
还研究了异质结构，其中硅与下面的碳化硅衬底直接接触。
M.R.Jennings等：“Si/SiC Heterojunctions Manufacture by Direct WaferBonding”Electrochemical and Solid State Letters，第11卷，第H306-H308页(2008)和A.Pérez-Tomás等：“Si/SiC bonded wafer:A route to carbon free SiO2on SiC”，Applied Physic Letters，第94卷，第103510页(2009)，描述了使用层转移工艺生产的硅-碳化硅异质结结构。
H.Shinohara等：“Si metal-oxide-semiconductor field-effect transistoron Si-on-SiC directly bonded wafer with high thermal conductance”，AppliedPhysics Letters，第93卷，第122110页(2008)和Y.Sasada等“Junction formation viadirect bonding of Si and 6H-SiC”，Materials Science Forum，第778-780卷，第714页(2014)描述了将硅晶片直接结合到6H-SiC晶片上。使用晶片薄化和抛光来将晶片厚度减小到1μm。在300℃时，CMOS类Si/SiC MOSFET的沟道迁移率以及由此导通状态的电导率仅降低了10％，相比之下，体硅器件降低了83％。
S.Lotfi等：“LDMOS-transistor on semi-insulator silicon-on-polys-silicon-SiC substrate for improved RF and thermal properties”，Solid-StateElectronics，第70卷，第14-19页(2012)和L.G.Li等：“Dynamics of SiO2Buried LayerRemoval from Si-SiO2-Si and Si-SiO2-SiC Bonded Substrates by Annealing in Ar”，Journal of Electronic Materials，第43卷，第541-547页(2014)描述了实现用于室温、低压RF应用的硅/多晶硅/多晶碳化硅(polysilicon carbide)衬底上的横向MOSFET结构。
硅/碳化硅器件显示出，与对比SOI器件不同，避免了正向特性中的自热。然而，在硅/碳化硅器件中，截止状态的漏电流略有增加，而在最坏的情况下，击穿电压(尽管未优化)减半。此外，SOI器件表现出更好的导通电压、亚阈值斜率和最大振荡频率。
发明内容
根据本发明的第一方面，提供了一种功率半导体器件。该器件包括碳化硅、金刚石或氮化铝衬底，以及具有不大于5μm的厚度的单晶硅层，该单晶硅层直接设置在衬底上或直接设置在具有不大于100nm的厚度的界面层上，该界面层直接设置在衬底上。该器件包括横向晶体管，该横向晶体管包括设置在单晶硅层中的第一和第二触点(contact)横向间隔的接触区。
因此，衬底允许使用较薄的硅层，例如，薄至300nm或甚至更小，以增加击穿电压。
衬底优选地包括6H-SiC衬底。衬底可以是半绝缘的。衬底可以掺杂n型或p型。衬底的可以具有不大于300μm或不大于50μm的厚度。
硅层可以具有不大于2μm、不大于1μm或不大于300nm的厚度。硅层可以包括n型区。硅层可以包括p型区
界面层可以包括介电材料(例如二氧化硅(SiO2)、氮化硅(SixNy)、氮氧化硅(SiOxNy)、氧化铝(Al2O3)或氧化铪(HfO2))层。界面层可以包括半导体材料，例如多晶硅层。
界面层可以具有不大于50nm的厚度。界面层可以具有至少5nm的厚度。
横向晶体管可以是金属氧化物半导体场效应晶体管(MOSFET)或绝缘栅双极晶体管(IGBT)。
根据本发明的第二方面，提供了一种在至少200℃的温度下操作功率半导体器件的方法。该方法包括施加至少100V的漏源电压。该方法可以包括施加高达600V或甚至1200V的漏源电压。该温度可以是至少250℃。
附图说明
现在将参考附图，通过示例的方式描述本发明的某些实施方式，在附图中：
图1是第一半导体器件的垂直截面；
图2是第二半导体器件的垂直截面；
图3是第三半导体器件的垂直截面；
图4是第四半导体器件的垂直截面；
图5是第五半导体器件的垂直截面；
图6是第六半导体器件的垂直截面；
图7是制造半导体器件的方法的工艺流程图；
图8A至图8D是在制造期间在不同阶段通过半导体器件的垂直截面；
图9示出模拟电流密度相对于反向漏源偏压(reverse drain-source bias)的图；
图10是电场分布的灰度图；并且
图11示出电流密度和内部结温的模拟图。
具体实施方式
以下，相同的部件由相同的附图标记表示。
器件结构
第一功率半导体器件
参考图1，示出了包括第一横向扩散金属氧化物半导体(LDMOS)晶体管1的第一功率半导体器件。
该器件包括半绝缘六阶(six-step)六方碳化硅(6H-SiC)衬底2。衬底2具有300μm的厚度t衬底。衬底2可以更薄，并且衬底厚度t衬底可以小至50μm。
在衬底2的上表面4上设置轻掺杂n型单晶硅层3。场氧化物5位于硅层3的上表面6处，并且具有第一和第二窗口71、72，其限定硅层3的第一和第二横向分离的上表面61、62。
在硅层3的上表面61上的第一窗口71内设置栅极氧化物8。栅极氧化物8沿着硅层3的上表面61延伸并邻接场氧化物5，从而形成台阶9。重掺杂n型多晶硅层10(其也可被称为“多晶硅栅(gate poly)”)被设置在栅极氧化物8上并且从台阶9上经过到场氧化物5上。另外或者可替换地，可以使用金属化(例如铝(Al))层。多晶硅栅10包括延伸部11。在多晶硅栅10的侧面上可以形成二氧化硅间隔物(未示出)。硅层3提供漂移区12。
在第一上表面61处的硅层3内设置轻掺杂p型扩散阱形式的p型体13。p型体13在栅极氧化物8的下方横向延伸。在第二上表面62处的硅层3内设置中度掺杂n型阱形式的n型缓冲区。在第一和第二上表面61、62处的p型阱13和n型缓冲区14中设置分别重掺杂浅n型扩散阱的形式的第一和第二接触区151、152(本文中分别称为“源区”和“漏区”)。在与源极触点151相邻的第一上表面61处设置重掺杂浅p型扩散阱形式的体接触区16。
使用以氧化物衬里的多晶硅填充沟槽171、172形式的深沟槽隔离(其从场氧化物5向下延伸穿过硅层3到衬底2)来将晶体管1与相邻晶体管(未示出)电隔离。
二氧化硅层18从多晶硅栅10和场氧化物5上经过，并且具有窗口191、192。在二氧化硅层18上设置金属化层201、202，覆盖窗口191、192。第一金属化层201提供源端子S，并且第二金属化层202提供漏端子D。金属化层201、202各自包括双层，该双层包括高阻隔金属硅化物基层(其包括例如硅化铂(PtSi))和高电导率覆盖层(其包括例如铝(Al))。
硅层3具有1μm的厚度tsi。然而，硅层3可以更厚，例如，高达2μm甚至5μm。然而，优选地，硅层3尽可能薄，并且可以薄至300nm。通过使栅极宽度更大，可以增加器件的额定电流。栅极宽度可为至少100μm、至少500μm、至少1mm或至少2mm。
接触区151、152、源极S和漏极D可以具有一个或多个不同的几何形状或布局。
例如，接触区151、152、源极S和漏极D可以沿y轴延伸，以形成大致平行的条纹。接触区151、152沿y轴可以具有相同长度。然而，一个接触区151、152(及其对应的金属化层S、D)可以比另一个接触区151、152(及其对应的金属化层S、D)更长，从而使器件1在平面图中呈楔形外观。
或者，器件1可以被这样布置使得接触区151、152(及其对应的金属化层S、D)中的一个被设置在器件1的中心并且另一个接触区151、152(及其对应的金属化层S、D)被布置为同心环，从而使器件在平面图中呈圆形外观。
功率半导体器件可以具有一个或多个优点。
作为硅基，晶体管1可能不经受碳化硅器件通常出现的高沟道电阻问题。
此外，6H-SiC衬底2可以是半绝缘的，并且由于具有导致低电导率的宽带隙而可以提供电隔离：衬底的电阻率可以超过107Ωcm。6H-SiC衬底2具有高的击穿电场，其可以使击穿电压增加约2至3倍，因为允许垂直电场通过碳化硅扩展。此外，6H-SiC具有所有常见碳化硅多型体的最高热导率，并且因此可以有效地将热量从器件的有源区传导出去，从而降低自热的影响。
因此，与体硅器件或绝缘体上硅器件相比，功率半导体器件可以在较高环境温度下的环境中使用，从而在给定温度下更有效地运行和/或以更高的功率吞吐量运转。
第二功率半导体器件
参考图2，示出了包括第二LDMOS晶体管21的第二功率半导体器件。
第二功率半导体器件与第一功率半导体器件基本上相同，只是界面层22介于衬底2和硅层3之间。界面层22与衬底的上表面4直接接触，并且硅层3与界面层22的上表面直接接触。
界面层22可以辅助硅层3和衬底2的结合。
界面层22可以由介电材料(例如二氧化硅、氮化硅(SixNy)、氧化铝(Al2O3)或氧化铪(HfO2))组成。界面层22可以由多晶硅组成。
界面层22(无论是电介质还是半导体)具有不大于100nm的厚度t界面层。优选地，界面层22具有约50nm的厚度。
第三功率半导体器件
参考图3，示出了包括第三LDMOS晶体管31的第三功率半导体器件。
第三功率半导体器件与第一功率半导体器件基本上相同，只是它沿着漂移区12'的长度采用所谓的“线性掺杂”，这有助于提高阻断电压。具体地，硅层3中的掺杂剂浓度从源极到漏极增加。掺杂浓度增加一个数量级，即nd2＝10.nd1其中n是漏极下面的掺杂浓度(在这种情况下，供体的掺杂浓度)，并且nd1是源极下面的掺杂浓度。
第四功率半导体器件
参考图4，示出了包括第四LDMOS晶体管41的第四功率半导体器件。
第四功率半导体器件与第一功率半导体器件基本上相同，只是它采用减小的表面场(RESURF)掺杂分布(profile)，这有助于提高击穿电压并最小化导通电阻。具体地，在n型漂移区12和衬底2之间提供p型区42。
第五功率半导体器件
参考图5，示出了包括第五LDMOS晶体管51的第五功率半导体器件。
第五功率半导体器件与第一功率半导体器件基本上相同，只是使用较厚的硅层3。这可以将额定电流与击穿电压的权衡转换回当前的吞吐量。具体地，硅层3可以具有大于2μm、高达5μm的厚度tSi。
第六功率半导体器件
在上文描述的实施方式中，横向晶体管采取场效应晶体管的形式。然而，晶体管可以采取其他形式。
参考图6，示出了包括绝缘栅双极晶体管(IGBT)61的第六功率半导体器件。
第六功率半导体器件与第一功率半导体器件基本上相同，只是第二接触区152是相反极性类型的，即，位于n型体区14中的重掺杂p型浅阱。这种类型的器件中的第一和第二接触区151、152分别被称为发射区和集电区。
制造
参考图7和图8A至8D，现在将描述制造功率半导体器件的方法。
使用溶剂和酸浸(未示出)以及兆声波冲洗(未示出)来清洗(步骤S1)包括硅衬底82(或“柄(handle)”)、掩埋氧化硅层83和表面氧化物层84的SOI晶片81以及衬底晶片2(例如6H-SiC晶片)。可选地，可以在SOI晶片81的表面86上沉积二氧化硅薄层(未示出)，以使表面亲水(步骤S2)。然后例如使用EVG(RTM)LT 810系列等离子体激活系统来等离子体激活表面86(步骤S3)。
将SOI晶片81的表面86和衬底晶片2的表面4对准并且拼在一起以形成复合晶片88(步骤S4)。复合晶片88在1000～1200℃下退火30秒以强化界面结合(步骤S5)。
然后对SOI晶片81进行研磨和抛光以去除柄82(步骤S6)。然后使用氢氟酸(未示出)除去氧化物层83(步骤S7)，并且将所得表面87进行化学机械抛光(步骤S8)以使硅层84变薄从而产生所需厚度的硅层3(图1)。
然后制造晶体管(步骤S9)。这可以开始于通过使用LOCOS工艺的热氧化来在硅层3的表面处形成场氧化物5(图1)。可以以本身公知的方式制造晶体管。
模拟器件特性
参考图9、10和11，示出了使用SILVACO(RTM)Atlas软件进行的具有直接设置在半绝缘6H-SiC衬底上的硅层的LDMOS晶体管(“Si/SiC MOSFET”)的模拟特性，以及设置在绝缘体上硅(SOI)衬底上的LDMOS晶体管(“SOI MOSFET”)(包括p型掺杂柄晶片(NA＝1×1017cm-3)和1μm的掩埋氧化物)形式的对比例的模拟特性。
两个晶体管都具有相同的结构和尺寸。所述晶体管具有厚度为2μm的硅层。在源区和漏区之间的漂移区长45μm，并且在场氧化物下方变窄至1μm。
对于Si/SiC MOSFET，漂移区是轻掺杂n型Si(ND＝1×1015cm-3)。然而，对于SOIMOSFET，使用线性掺杂，使得漂移区中的掺杂从源极处的ND＝1×1015cm-3增加到漏极处的ND＝1×1016cm-3，以使晶体管的击穿电压最大化。
图9示出了模拟击穿电压，其中源极至漏极电压增加直至漏电流开始呈指数增长。从图1中看出，尽管具有类似的结构，Si/SiC MOSFET达到600V，相比之下，线性掺杂SOIMOSFET达到210V(没有线性掺杂，击穿电压仅为110V)。
图10示出了在雪崩击穿点处的Si/SiC和SOI MOSFET中的电场分布。在每个器件结构中轮廓(当它们超过Si的临界电场时是黑色的)显示出具有非常不同的分布。
在SOI MOSFET中，电场朝漂移区的漏极端高度集中，其中绝缘掩埋氧化物不允许电场的任何显著垂直扩展。
然而，在Si/SiC MOSFET中，有电场的显著垂直扩展到衬底中。这导致电场沿着漂移区从源极到漏极横向地更均匀地扩展。
通过观察正向偏压特性来测试Si/SiC和SOI MOSFET的自热特性。
参考图11，实心形状表示每个器件的输出JDS-VDS特性，而不考虑温度的影响。对每个器件施加7V的栅偏压，并且随着VDS斜升该栅偏压被充分地驱动到饱和区中，从而增加器件中消耗的功率。中空形状表示使用电热模拟的结果。下图显示随着VDS斜升时的器件的局部温度。减小的电流是被称为负电阻的效应，其中温度升高导致漂移区的内部电阻升高，从而降低总电流吞吐量。在VDS＝200V时，自热致使Si/SiC MOSFET的电流吞吐量降低10％，相比之下，SOI MOSFET降低20％。此外，此时SOI MOSFET的内部结温上升了108℃，温度升高比Si/SiC MOSFET大三倍以上。
修改
将理解的是，可以对上文描述的实施方式做出各种修改。这样的修改可以包括功率半导体器件及其组成部件的设计、制造和使用中已知的等效方式和其他特征，并且该等效方式和其他特征可以代替本文已经描述的特征使用或另外使用。一个实施方式的特征可以被另一个实施方式的特征替换或补充。例如，第二功率半导体器件的界面层可以与第二功率半导体器件的线性掺杂组合使用。
晶体管可以是p型而非n型的。因此，可以使用p型硅层，并且体区和接触区可以是合适的导电类型。
不需要使用半绝缘6H-SiC衬底。可以使用n型或p型掺杂6H-SiC衬底。可以使用SiC的其它多型体，例如4H-SiC。
可以使用具有高热导率的除SiC以外的衬底，比如，例如金刚石或氮化铝(AlN)。
不需要通过将绝缘体上硅晶片晶片结合到衬底晶片(具有或不具有薄介电层)上，研磨柄晶片，蚀刻(使用氢氟酸)氧化物并抛光表面来形成硅层。可以使用Smartcut(RTM)形成硅层。可以通过将硅晶片结合到衬底晶片(具有或不具有薄的介电层)，然后研磨并抛光硅晶片来形成硅层。可以通过使用分子束外延(MBE)或化学气相沉积(CVD)在衬底上外延生长硅层来形成硅晶片。

Claims (15)

1.一种功率半导体器件，包括：
碳化硅、金刚石或氮化铝衬底；
具有不大于5μm的厚度的单晶硅层，所述单晶硅层直接设置在所述衬底上或直接设置在具有不大于100nm的厚度的界面层上，所述界面层直接设置在所述衬底上；以及
横向晶体管，所述横向晶体管包括：
设置在所述单晶硅层中的第一和第二触点横向间隔的接触区。
2.根据权利要求1所述的器件，其中所述衬底包括6H-SiC衬底。
3.根据权利要求1或2所述的器件，其中所述衬底是半绝缘的。
4.根据前述权利要求中任一项所述的器件，其中所述衬底具有不大于300μm的厚度。
5.根据前述权利要求中任一项所述的器件，其中所述衬底具有不大于50μm的厚度。
6.根据前述权利要求中任一项所述的器件，其中所述单晶硅层具有不大于2μm的厚度。
7.根据前述权利要求中任一项所述的器件，其中所述单晶硅层具有不大于1μm的厚度。
8.根据前述权利要求中任一项所述的器件，其中所述单晶硅层具有不大于300nm的厚度。
9.根据前述权利要求中任一项所述的器件，其中所述单晶硅层包括n型区或p型区。
10.根据前述权利要求中任一项所述的器件，其中所述界面层包括介电材料。
11.根据前述权利要求中任一项所述的器件，其中所述界面层包括半导体材料。
12.根据前述权利要求中任一项所述的器件，其中所述横向晶体管是金属氧化物半导体场效应晶体管。
13.根据前述权利要求中任一项所述的器件，其中所述横向晶体管是绝缘栅双极晶体管。
14.一种在至少200℃的温度下操作根据前述权利要求中任一项所述的器件的方法，所述方法包括：
施加至少100V的漏源电压。
15.根据权利要求14所述的方法，包括：
施加高达600V的漏源电压。
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Application publication date: 20180105