JP2581902B2 - パターン重ね合せ精度測定マークの製造法 - Google Patents

パターン重ね合せ精度測定マークの製造法

Info

Publication number
JP2581902B2
JP2581902B2 JP6250559A JP25055994A JP2581902B2 JP 2581902 B2 JP2581902 B2 JP 2581902B2 JP 6250559 A JP6250559 A JP 6250559A JP 25055994 A JP25055994 A JP 25055994A JP 2581902 B2 JP2581902 B2 JP 2581902B2
Authority
JP
Japan
Prior art keywords
layer
outer box
forming
measurement mark
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP6250559A
Other languages
English (en)
Japanese (ja)
Other versions
JPH07231022A (ja
Inventor
▲べー▼相満
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hyundai Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Industries Co Ltd filed Critical Hyundai Electronics Industries Co Ltd
Publication of JPH07231022A publication Critical patent/JPH07231022A/ja
Application granted granted Critical
Publication of JP2581902B2 publication Critical patent/JP2581902B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • G03F7/70633—Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70681—Metrology strategies
    • G03F7/70683—Mark designs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/975—Substrate or mask aligning feature

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
JP6250559A 1993-10-15 1994-10-17 パターン重ね合せ精度測定マークの製造法 Expired - Fee Related JP2581902B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019930021405A KR960014963B1 (ko) 1993-10-15 1993-10-15 반도체 장치의 제조 방법
KR93-21405 1993-10-15

Publications (2)

Publication Number Publication Date
JPH07231022A JPH07231022A (ja) 1995-08-29
JP2581902B2 true JP2581902B2 (ja) 1997-02-19

Family

ID=19365886

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6250559A Expired - Fee Related JP2581902B2 (ja) 1993-10-15 1994-10-17 パターン重ね合せ精度測定マークの製造法

Country Status (4)

Country Link
US (2) US5578423A (enExample)
JP (1) JP2581902B2 (enExample)
KR (1) KR960014963B1 (enExample)
TW (1) TW280014B (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101996866B (zh) * 2009-08-27 2013-04-24 上海华虹Nec电子有限公司 保护套刻标记图形的方法

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0170909B1 (ko) * 1995-09-27 1999-03-30 김주용 반도체 소자의 오버레이 검사방법
US5879994A (en) * 1997-04-15 1999-03-09 National Semiconductor Corporation Self-aligned method of fabricating terrace gate DMOS transistor
US5952132A (en) * 1997-09-12 1999-09-14 Taiwan Semiconductor Mfg. Co. Method for forming a stepper focus pattern through determination of overlay error
US6093640A (en) * 1999-01-11 2000-07-25 Taiwan Semiconductor Manufacturing Company Overlay measurement improvement between damascene metal interconnections
KR100292063B1 (ko) * 1999-03-26 2001-06-01 황인길 임계치수 및 중첩도 측정방법
JP3348783B2 (ja) 1999-07-28 2002-11-20 日本電気株式会社 重ね合わせ用マーク及び半導体装置
JP3677426B2 (ja) * 2000-02-21 2005-08-03 Ｎｅｃエレクトロニクス株式会社 位置合わせ精度計測マーク
US6350548B1 (en) 2000-03-15 2002-02-26 International Business Machines Corporation Nested overlay measurement target
US6552790B1 (en) 2001-02-20 2003-04-22 Advanced Micro Devices, Inc. System and method for facilitating wafer alignment by mitigating effects of reticle rotation on overlay
JP2002221801A (ja) * 2001-01-29 2002-08-09 Hitachi Ltd 配線基板の製造方法
US6436595B1 (en) 2001-02-08 2002-08-20 International Business Machines Corporation Method of aligning lithographically printed product layers using non-zero overlay targets
US7190823B2 (en) * 2002-03-17 2007-03-13 United Microelectronics Corp. Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same
US7175951B1 (en) 2002-04-19 2007-02-13 Taiwan Semiconductor Manufacturing Company Two mask in-situ overlay checking method
DE10224164B4 (de) * 2002-05-31 2007-05-10 Advanced Micro Devices, Inc., Sunnyvale Eine zweidimensionale Struktur zum Bestimmen einer Überlagerungsgenauigkeit mittels Streuungsmessung
US20040063007A1 (en) * 2002-09-27 2004-04-01 Satoshi Machida Precision-of-register measuring mark and measuring method
JP4979283B2 (ja) * 2006-06-29 2012-07-18 株式会社日立製作所 半導体装置の製造方法および半導体装置
US8031329B2 (en) * 2007-04-16 2011-10-04 Macronix International Co., Ltd. Overlay mark, and fabrication and application of the same
JP5737922B2 (ja) * 2010-12-14 2015-06-17 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体デバイスの製造方法
CN114167693A (zh) * 2020-09-10 2022-03-11 中国科学院微电子研究所 用于套刻精度测量的标记系统及量测方法
CN113394198A (zh) * 2021-05-28 2021-09-14 上海华力微电子有限公司 光刻对准标记及其形成方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106432A (en) * 1989-05-16 1992-04-21 Oki Electric Industry Co., Ltd. Wafer alignment mark utilizing parallel grooves and process
US4992394A (en) * 1989-07-31 1991-02-12 At&T Bell Laboratories Self aligned registration marks for integrated circuit fabrication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101996866B (zh) * 2009-08-27 2013-04-24 上海华虹Nec电子有限公司 保护套刻标记图形的方法

Also Published As

Publication number Publication date
KR950012591A (ko) 1995-05-16
JPH07231022A (ja) 1995-08-29
TW280014B (enExample) 1996-07-01
US5578423A (en) 1996-11-26
KR960014963B1 (ko) 1996-10-23
US5635336A (en) 1997-06-03

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