TW280014B - - Google Patents

Info

Publication number
TW280014B
TW280014B TW083109477A TW83109477A TW280014B TW 280014 B TW280014 B TW 280014B TW 083109477 A TW083109477 A TW 083109477A TW 83109477 A TW83109477 A TW 83109477A TW 280014 B TW280014 B TW 280014B
Authority
TW
Taiwan
Application number
TW083109477A
Original Assignee
Hyundai Electronics Ind
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hyundai Electronics Ind filed Critical Hyundai Electronics Ind
Application granted granted Critical
Publication of TW280014B publication Critical patent/TW280014B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • GPHYSICS
    • G03PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03FPHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605Workpiece metrology
    • G03F7/70616Monitoring the printed patterns
    • G03F7/70633Overlay, i.e. relative alignment between patterns printed by separate exposures in different layers, or in the same layer in multiple exposures or stitching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/544Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54453Marks applied to semiconductor devices or parts for use prior to dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/975Substrate or mask aligning feature
TW083109477A 1993-10-15 1994-10-13 TW280014B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930021405A KR960014963B1 (ko) 1993-10-15 1993-10-15 반도체 장치의 제조 방법

Publications (1)

Publication Number Publication Date
TW280014B true TW280014B (zh) 1996-07-01

Family

ID=19365886

Family Applications (1)

Application Number Title Priority Date Filing Date
TW083109477A TW280014B (zh) 1993-10-15 1994-10-13

Country Status (4)

Country Link
US (2) US5578423A (zh)
JP (1) JP2581902B2 (zh)
KR (1) KR960014963B1 (zh)
TW (1) TW280014B (zh)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0170909B1 (ko) * 1995-09-27 1999-03-30 김주용 반도체 소자의 오버레이 검사방법
US5879994A (en) * 1997-04-15 1999-03-09 National Semiconductor Corporation Self-aligned method of fabricating terrace gate DMOS transistor
US5952132A (en) * 1997-09-12 1999-09-14 Taiwan Semiconductor Mfg. Co. Method for forming a stepper focus pattern through determination of overlay error
US6093640A (en) * 1999-01-11 2000-07-25 Taiwan Semiconductor Manufacturing Company Overlay measurement improvement between damascene metal interconnections
KR100292063B1 (ko) * 1999-03-26 2001-06-01 황인길 임계치수 및 중첩도 측정방법
JP3348783B2 (ja) * 1999-07-28 2002-11-20 日本電気株式会社 重ね合わせ用マーク及び半導体装置
JP3677426B2 (ja) * 2000-02-21 2005-08-03 Necエレクトロニクス株式会社 位置合わせ精度計測マーク
US6350548B1 (en) 2000-03-15 2002-02-26 International Business Machines Corporation Nested overlay measurement target
US6552790B1 (en) 2001-02-20 2003-04-22 Advanced Micro Devices, Inc. System and method for facilitating wafer alignment by mitigating effects of reticle rotation on overlay
JP2002221801A (ja) * 2001-01-29 2002-08-09 Hitachi Ltd 配線基板の製造方法
US6436595B1 (en) 2001-02-08 2002-08-20 International Business Machines Corporation Method of aligning lithographically printed product layers using non-zero overlay targets
US7190823B2 (en) * 2002-03-17 2007-03-13 United Microelectronics Corp. Overlay vernier pattern for measuring multi-layer overlay alignment accuracy and method for measuring the same
US7175951B1 (en) 2002-04-19 2007-02-13 Taiwan Semiconductor Manufacturing Company Two mask in-situ overlay checking method
DE10224164B4 (de) * 2002-05-31 2007-05-10 Advanced Micro Devices, Inc., Sunnyvale Eine zweidimensionale Struktur zum Bestimmen einer Überlagerungsgenauigkeit mittels Streuungsmessung
US20040063007A1 (en) * 2002-09-27 2004-04-01 Satoshi Machida Precision-of-register measuring mark and measuring method
JP4979283B2 (ja) * 2006-06-29 2012-07-18 株式会社日立製作所 半導体装置の製造方法および半導体装置
US8031329B2 (en) * 2007-04-16 2011-10-04 Macronix International Co., Ltd. Overlay mark, and fabrication and application of the same
CN101996866B (zh) * 2009-08-27 2013-04-24 上海华虹Nec电子有限公司 保护套刻标记图形的方法
JP5737922B2 (ja) * 2010-12-14 2015-06-17 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. 半導体デバイスの製造方法
CN114167693A (zh) * 2020-09-10 2022-03-11 中国科学院微电子研究所 用于套刻精度测量的标记系统及量测方法
CN113394198A (zh) * 2021-05-28 2021-09-14 上海华力微电子有限公司 光刻对准标记及其形成方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5106432A (en) * 1989-05-16 1992-04-21 Oki Electric Industry Co., Ltd. Wafer alignment mark utilizing parallel grooves and process
US4992394A (en) * 1989-07-31 1991-02-12 At&T Bell Laboratories Self aligned registration marks for integrated circuit fabrication

Also Published As

Publication number Publication date
KR950012591A (ko) 1995-05-16
US5578423A (en) 1996-11-26
JPH07231022A (ja) 1995-08-29
US5635336A (en) 1997-06-03
KR960014963B1 (ko) 1996-10-23
JP2581902B2 (ja) 1997-02-19

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees