JP2554423Y2 - メモリ制御装置 - Google Patents

メモリ制御装置

Info

Publication number
JP2554423Y2
JP2554423Y2 JP14212088U JP14212088U JP2554423Y2 JP 2554423 Y2 JP2554423 Y2 JP 2554423Y2 JP 14212088 U JP14212088 U JP 14212088U JP 14212088 U JP14212088 U JP 14212088U JP 2554423 Y2 JP2554423 Y2 JP 2554423Y2
Authority
JP
Japan
Prior art keywords
cpu
port ram
dual
read
interrupt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP14212088U
Other languages
English (en)
Japanese (ja)
Other versions
JPH0265296U (cs
Inventor
久司 永原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Yokogawa Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp filed Critical Yokogawa Electric Corp
Priority to JP14212088U priority Critical patent/JP2554423Y2/ja
Publication of JPH0265296U publication Critical patent/JPH0265296U/ja
Application granted granted Critical
Publication of JP2554423Y2 publication Critical patent/JP2554423Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Static Random-Access Memory (AREA)
JP14212088U 1988-10-31 1988-10-31 メモリ制御装置 Expired - Lifetime JP2554423Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14212088U JP2554423Y2 (ja) 1988-10-31 1988-10-31 メモリ制御装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14212088U JP2554423Y2 (ja) 1988-10-31 1988-10-31 メモリ制御装置

Publications (2)

Publication Number Publication Date
JPH0265296U JPH0265296U (cs) 1990-05-16
JP2554423Y2 true JP2554423Y2 (ja) 1997-11-17

Family

ID=31407796

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14212088U Expired - Lifetime JP2554423Y2 (ja) 1988-10-31 1988-10-31 メモリ制御装置

Country Status (1)

Country Link
JP (1) JP2554423Y2 (cs)

Also Published As

Publication number Publication date
JPH0265296U (cs) 1990-05-16

Similar Documents

Publication Publication Date Title
JPS63255759A (ja) 制御システム
US4729090A (en) DMA system employing plural bus request and grant signals for improving bus data transfer speed
JP2554423Y2 (ja) メモリ制御装置
JPH0343804A (ja) シーケンス制御装置
JPS603747A (ja) プログラム選択制御方式
JP2522412B2 (ja) プログラマブルコントロ―ラと入出力装置の間の通信方法
JPH03134712A (ja) プログラマブルコントローラ
JPS6130300B2 (cs)
JP2722908B2 (ja) シングルチップマイクロコンピュータ
JPH02211571A (ja) 情報処理装置
JPH0236016B2 (cs)
JP2610971B2 (ja) 中央処理装置間ダイレクトメモリアクセス方式
JPS6022383B2 (ja) 入出力制御装置
JPH01251156A (ja) デュアルポートメモリ回路
JPS59201153A (ja) スタンドアロン型画像処理システムのホスト接続方式
JPS6068462A (ja) マルチプロセッサ・システム
JPS63279359A (ja) マルチｃｐｕのデ−タ受け渡し装置
JPH0437946A (ja) 通信方式
JPH03219359A (ja) インタフェース回路
JPH02219105A (ja) プログラマブルコントローラ
JPH0592856U (ja) １チップｃｐｕの外部メモリへのｄｍａ転送制御装置
JPH01248264A (ja) システムバス競合制御方式
JPH04328667A (ja) ２ポートｒａｍデータ送受方式及び装置
JPS6127790B2 (cs)
JPH0247751A (ja) チャネル制御方式